Xen Test Framework
processor.h
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1#ifndef XTF_X86_PROCESSOR_H
2#define XTF_X86_PROCESSOR_H
3
4/*
5 * EFLAGS bits.
6 */
7#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
8#define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */
9#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
10#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
11#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
12#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
13#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
14#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
15#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
16#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
17#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
18#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
19#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
20#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
21#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
22#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
23#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
24#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
25
26/*
27 * CPU flags in CR0.
28 */
29#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
30#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
31#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
32#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
33#define X86_CR0_ET 0x00000010 /* Extension type (RO) */
34#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
35#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
36#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
37#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
38#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
39#define X86_CR0_PG 0x80000000 /* Paging (RW) */
40
41/*
42 * CPU features in CR4.
43 */
44#define X86_CR4_VME 0x00000001 /* VM86 extensions */
45#define X86_CR4_PVI 0x00000002 /* Virtual interrupts flag */
46#define X86_CR4_TSD 0x00000004 /* Disable time stamp at ipl 3 */
47#define X86_CR4_DE 0x00000008 /* Debugging extensions */
48#define X86_CR4_PSE 0x00000010 /* Page size extensions */
49#define X86_CR4_PAE 0x00000020 /* Physical address extensions */
50#define X86_CR4_MCE 0x00000040 /* Machine check */
51#define X86_CR4_PGE 0x00000080 /* Global pages */
52#define X86_CR4_PCE 0x00000100 /* Performance counters at ipl 3 */
53#define X86_CR4_OSFXSR 0x00000200 /* Fast FPU save and restore */
54#define X86_CR4_OSXMMEXCPT 0x00000400 /* Unmasked SSE exceptions */
55#define X86_CR4_UMIP 0x00000800 /* UMIP */
56#define X86_CR4_VMXE 0x00002000 /* VMX */
57#define X86_CR4_SMXE 0x00004000 /* SMX */
58#define X86_CR4_FSGSBASE 0x00010000 /* {rd,wr}{fs,gs}base */
59#define X86_CR4_PCIDE 0x00020000 /* PCID */
60#define X86_CR4_OSXSAVE 0x00040000 /* XSAVE/XRSTOR */
61#define X86_CR4_SMEP 0x00100000 /* SMEP */
62#define X86_CR4_SMAP 0x00200000 /* SMAP */
63
64/*
65 * CPU features in XCR0.
66 */
67#define _XSTATE_FP 0
68#define XSTATE_FP (1ULL << _XSTATE_FP)
69#define _XSTATE_SSE 1
70#define XSTATE_SSE (1ULL << _XSTATE_SSE)
71#define _XSTATE_YMM 2
72#define XSTATE_YMM (1ULL << _XSTATE_YMM)
73#define _XSTATE_BNDREGS 3
74#define XSTATE_BNDREGS (1ULL << _XSTATE_BNDREGS)
75#define _XSTATE_BNDCSR 4
76#define XSTATE_BNDCSR (1ULL << _XSTATE_BNDCSR)
77#define _XSTATE_OPMASK 5
78#define XSTATE_OPMASK (1ULL << _XSTATE_OPMASK)
79#define _XSTATE_ZMM 6
80#define XSTATE_ZMM (1ULL << _XSTATE_ZMM)
81#define _XSTATE_HI_ZMM 7
82#define XSTATE_HI_ZMM (1ULL << _XSTATE_HI_ZMM)
83#define _XSTATE_PKRU 9
84#define XSTATE_PKRU (1ULL << _XSTATE_PKRU)
85#define _XSTATE_LWP 62
86#define XSTATE_LWP (1ULL << _XSTATE_LWP)
87
88/*
89 * Media eXtentions Control and Status Register.
90 */
91#define X86_MXCSR_IE 0x00000001 /* Invalid-Operation Exception */
92#define X86_MXCSR_DE 0x00000002 /* Denormal-Operation Exception */
93#define X86_MXCSR_ZE 0x00000004 /* Zero-divide Exception */
94#define X86_MXCSR_OE 0x00000008 /* Overflow Exception */
95#define X86_MXCSR_UE 0x00000010 /* Underflow Exception */
96#define X86_MXCSR_PE 0x00000020 /* Precision Exception */
97#define X86_MXCSR_STATUS_MASK 0x0000003f /* `- All of the above */
98
99/*
100 * Exception mnemonics.
101 */
102#define X86_EXC_DE 0 /* Divide Error. */
103#define X86_EXC_DB 1 /* Debug Exception. */
104#define X86_EXC_NMI 2 /* NMI. */
105#define X86_EXC_BP 3 /* Breakpoint. */
106#define X86_EXC_OF 4 /* Overflow. */
107#define X86_EXC_BR 5 /* BOUND Range. */
108#define X86_EXC_UD 6 /* Invalid Opcode. */
109#define X86_EXC_NM 7 /* Device Not Available. */
110#define X86_EXC_DF 8 /* Double Fault. */
111#define X86_EXC_CSO 9 /* Coprocessor Segment Overrun. */
112#define X86_EXC_TS 10 /* Invalid TSS. */
113#define X86_EXC_NP 11 /* Segment Not Present. */
114#define X86_EXC_SS 12 /* Stack-Segment Fault. */
115#define X86_EXC_GP 13 /* General Protection Fault. */
116#define X86_EXC_PF 14 /* Page Fault. */
117#define X86_EXC_SPV 15 /* PIC Spurious Interrupt Vector. */
118#define X86_EXC_MF 16 /* Maths fault (x87 FPU). */
119#define X86_EXC_AC 17 /* Alignment Check. */
120#define X86_EXC_MC 18 /* Machine Check. */
121#define X86_EXC_XM 19 /* SIMD Exception. */
122#define X86_EXC_VE 20 /* Virtualisation Exception. */
123
124/* Bitmap of exceptions which have error codes. */
125#define X86_EXC_HAVE_EC ((1 << X86_EXC_DF) | (1 << X86_EXC_TS) | \
126 (1 << X86_EXC_NP) | (1 << X86_EXC_SS) | \
127 (1 << X86_EXC_GP) | (1 << X86_EXC_PF) | \
128 (1 << X86_EXC_AC))
129
130/* Bitmap of exceptions which are classified as faults. */
131#define X86_EXC_FAULTS ((1 << X86_EXC_DE) | (1 << X86_EXC_BR) | \
132 (1 << X86_EXC_UD) | (1 << X86_EXC_NM) | \
133 (1 << X86_EXC_CSO) | (1 << X86_EXC_TS) | \
134 (1 << X86_EXC_NP) | (1 << X86_EXC_SS) | \
135 (1 << X86_EXC_GP) | (1 << X86_EXC_PF) | \
136 (1 << X86_EXC_MF) | (1 << X86_EXC_AC) | \
137 (1 << X86_EXC_XM) | (1 << X86_EXC_VE))
138
139/* Bitmap of exceptions which are classified as interrupts. */
140#define X86_EXC_INTERRUPTS (1 << X86_EXC_NMI)
141
142/* Bitmap of exceptions which are classified as traps. */
143#define X86_EXC_TRAPS ((1 << X86_EXC_BP) | (1 << X86_EXC_OF))
144
145/* Bitmap of exceptions which are classified as aborts. */
146#define X86_EXC_ABORTS ((1 << X86_EXC_DF) | (1 << X86_EXC_MC))
147
148/* Number of reserved vectors for exceptions. */
149#define X86_NR_RESERVED_VECTORS 32
150
151/*
152 * Error Code mnemonics.
153 */
154/* Segment-based Error Code - architecturally defined. */
155#define X86_EC_EXT (1U << 0) /* External event. */
156#define X86_EC_IDT (1U << 1) /* Descriptor Location. IDT, or LDT/GDT */
157#define X86_EC_TI (1U << 2) /* Only if !IDT. LDT or GDT. */
158
159/* Segment-based Error Code - supplemental constants. */
160#define X86_EC_TABLE_MASK (3 << 1)
161#define X86_EC_SEL_SHIFT 3
162#define X86_EC_SEL_MASK (~0U << X86_EC_SEL_SHIFT)
163#define X86_EC_GDT 0
164#define X86_EC_LDT X86_EC_TI
165
166/* Pagefault Error Code - architecturally defined. */
167#define X86_PFEC_PRESENT (1U << 0)
168#define X86_PFEC_WRITE (1U << 1)
169#define X86_PFEC_USER (1U << 2)
170#define X86_PFEC_RSVD (1U << 3)
171#define X86_PFEC_INSN (1U << 4)
172#define X86_PFEC_PK (1U << 5)
173
174/* Pagefault Error Code - Short form mnemonics. */
175#define X86_PFEC_P X86_PFEC_PRESENT
176#define X86_PFEC_W X86_PFEC_WRITE
177#define X86_PFEC_U X86_PFEC_USER
178#define X86_PFEC_R X86_PFEC_RSVD
179#define X86_PFEC_I X86_PFEC_INSN
180#define X86_PFEC_K X86_PFEC_PK
181
182/*
183 * Selector mnemonics.
184 */
185/* Architecturally defined. */
186#define X86_SEL_TI (1U << 2) /* Table Indicator. */
187
188/* Supplemental constants. */
189#define X86_SEL_RPL_MASK 3 /* RPL is the bottom two bits. */
190#define X86_SEL_GDT 0
191#define X86_SEL_LDT X86_SEL_TI
192
193#endif /* XTF_X86_PROCESSOR_H */
194
195/*
196 * Local variables:
197 * mode: C
198 * c-file-style: "BSD"
199 * c-basic-offset: 4
200 * tab-width: 4
201 * indent-tabs-mode: nil
202 * End:
203 */
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