diff --git a/xen/arch/x86/hvm/io.c b/xen/arch/x86/hvm/io.c
-index 0d7f5ff..8be35e5 100644
+index 0d7f5ff..940ff1f 100644
--- a/xen/arch/x86/hvm/io.c
+++ b/xen/arch/x86/hvm/io.c
@@ -278,6 +278,7 @@ void dpci_ioport_write(uint32_t mport, ioreq_t *p)
for ( i = 0; i < p->count; i++ )
{
-@@ -286,6 +287,19 @@ void dpci_ioport_write(uint32_t mport, ioreq_t *p)
+@@ -286,6 +287,27 @@ void dpci_ioport_write(uint32_t mport, ioreq_t *p)
(void)hvm_copy_from_guest_phys(
&data, p->data + (sign * i * p->size), p->size);
+ if (d->igfx_ioport)
+ {
-+ if (mport == d->igfx_ioport) {
-+ d->igfx_index = data;
-+ } else if (mport == (d->igfx_ioport+4)) {
-+ if ((d->igfx_index & 1) && (d->igfx_index < 0x10000)) {
-+ //gdprintk(XENLOG_DEBUG, "iGFXIo: Skip outl(0x%04x,0x%08x) idx=0x%08x\n",
-+ // (u16)(mport), data, d->igfx_index);
++ if ( mport == d->igfx_ioport )
++ {
++ if ((d->igfx_index & 1) && (d->igfx_index < 0x10000))
++ {
++ d->igfx_index = data & ~3;
+ continue;
++ } else {
++ d->igfx_index = 0;
+ }
+ }
++ else if (mport == d->igfx_ioport+4 && d->igfx_index)
++ {
++ (void)hvm_copy_to_guest_phys(
++ d->igfx_mmio + 0x200000 + (d->igfx_index & ~3),
++ &data, p->size);
++ continue;
++ }
+ }
+
switch ( p->size )
{
case 1:
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
-index ff56a19..2e8efff 100644
+index ff56a19..adeaa55 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
-@@ -1395,6 +1395,24 @@ static int domain_context_unmap(struct domain *domain, u8 bus, u8 devfn)
+@@ -1395,6 +1395,22 @@ static int domain_context_unmap(struct domain *domain, u8 bus, u8 devfn)
return ret;
}
+ deviceid = pci_conf_read16(bus, d, f, PCI_DEVICE_ID);
+ if ((vendorid == 0x8086) && (deviceid == 0x2a42)) {
+ u32 iobase = pci_conf_read32(bus, d, f, PCI_BASE_ADDRESS_0 + 4*4) & PCI_BASE_ADDRESS_IO_MASK;
-+ printk(XENLOG_DEBUG "Found Intel 8086:2a42 gfx with I/O at 0x%04x\n", iobase);
-+ if (iobase > 0xffff) {
-+ printk(XENLOG_ERR "Intel 8086:2a42 gfx has invalid I/O base 0x%08x\n", iobase);
-+ } else {
-+ domain->igfx_ioport = (iobase & 0xffff);
-+ }
++ u32 mem0base = pci_conf_read32(bus, d, f, PCI_BASE_ADDRESS_0 + 0*4) & PCI_BASE_ADDRESS_MEM_MASK;
++ printk(XENLOG_DEBUG "Found Intel 8086:2a42 gfx with I/O at 0x%04x, MMIO at 0x%08x\n", iobase, mem0base);
++ domain->igfx_ioport = iobase;
++ domain->igfx_mmio = mem0base;
+ }
+}
+
static int reassign_device_ownership(
struct domain *source,
struct domain *target,
-@@ -1423,6 +1441,8 @@ static int reassign_device_ownership(
+@@ -1423,6 +1439,8 @@ static int reassign_device_ownership(
list_move(&pdev->domain_list, &target->arch.pdev_list);
pdev->domain = target;
{
drhd = acpi_find_matched_drhd_unit(pdev);
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
-index 46731a5..06a9016 100644
+index 46731a5..ad76a28 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
-@@ -206,6 +206,8 @@ struct domain
+@@ -206,6 +206,9 @@ struct domain
/* I/O capabilities (access to IRQs and memory-mapped I/O). */
struct rangeset *iomem_caps;
struct rangeset *irq_caps;
-+ u16 igfx_ioport;
++ u32 igfx_ioport;
+ u32 igfx_index;
++ u32 igfx_mmio;
/* Is this an HVM guest? */
bool_t is_hvm;