intel: Don't shutdown the pipe when we switch to linear

diff --git a/master/intel b/master/intel
index 433c9ecc96ff499c36bbe5155254299036106b37..660798dbbc248629166f70e06aadd8573e0edf1a 100644 (file)
--- a/master/intel
+++ b/master/intel
@@ -201,10 +201,10 @@ index 90bd544..e4e27a9 100644
      vga_update_display(s);
 diff --git a/intel.c b/intel.c
 new file mode 100644
-index 0000000..c1a8c45
+index 0000000..5820935
 --- /dev/null
 +++ b/intel.c
-@@ -0,0 +1,663 @@
+@@ -0,0 +1,581 @@
 +#include <stdio.h>
 +#include <stdlib.h>
 +#include <stdint.h>
@@ -316,68 +316,28 @@ index 0000000..c1a8c45
 +
 +    struct timeval start_decompress;
 +
-+    unsigned int surfa = 0, surfb = 0, pipea = 0, pipeb = 0;
-+    char pipeaenabled = !!(*pipeaconf & (1 << 30));
-+    char pipebenabled = !!(*pipebconf & (1 << 30));
-+
-+    INTEL_DEBUG("DSPASURF CTRL: 0x%x\n", intel_get_reg(REG_DR_DSPACNTR));
-+
-+    if (pipeaenabled)
-+    {
-+        INTEL_DEBUG("PIPEACONF enabled.\n");
-+        /* Disable surface */
-+        pipea = *pipeaconf & (0x3 << 18);
-+        *pipeaconf &= ~(0x3 << 18);
-+        *dspacntr |= (1 << 31);
-+        /* Address of the surface to map to */
-+        surfa = *dspasurf;
-+        *dspasurf = 0x00000000;
-+        *dspacntr &= ~(1 << 31);
-+        *dspasurf = 0x00000000;
-+        *pipeaconf |= pipea;
-+    }
-+
-+    if (pipebenabled) {
-+        INTEL_DEBUG("PIPEBCONF enabled.\n");
-+
-+        /* Disable surface */
-+        pipeb = *pipebconf & (0x3 << 18);
-+        *pipebconf &= ~(0x3 << 18);
-+        *dspbcntr |= (1 << 31);
-+        /* Address of the surface to map to */
-+        surfb = *dspbsurf;
-+        *dspbsurf = 0x00000000;
-+        *dspbcntr &= ~(1 << 31);
-+        *dspbsurf = 0x00000000;
-+        *pipebconf |= pipeb;
-+    }
-+
-+    usleep(50 * 1000); /* 50 ms */
-+
-+    if (pipeaenabled)
-+    {
-+        *pipeaconf &= ~(0x3 << 18);
-+        /* Enable surface linear mode */
-+        *dspacntr &= ~(1 << 10);
-+        if (linesize) *dspastride = linesize;
-+        *dspasurf = surfa;
-+        *dspacntr |= (1 << 31);
-+        *pipeaconf |= pipea;
-+    }
-+
-+    if (pipebenabled) {
-+        *pipebconf &= ~(0x3 << 18);
-+        /* Enable surface linear mode */
-+        *dspbcntr &= ~(1 << 10);
-+        if (linesize) *dspbstride = linesize;
-+        *dspbsurf = surfb;
-+        *dspbcntr |= (1 << 31);
-+        *pipebconf |= pipeb;
-+    }
++    unsigned int surfa = 0, surfb = 0;
++
++    INTEL_DEBUG("Force linear\n");
++
++    /* Enable surface linear mode */
++    surfa = *dspasurf;
++    INTEL_DEBUG("DSPASURF : 0x%x, DSPACNTR: 0x%x\n", surfa, *dspacntr);
++    *dspacntr &= ~(1 << 10);
++    if (linesize) *dspastride = linesize;
++    *dspasurf = surfa;
++    INTEL_DEBUG("DSPASURF : 0x%x, DSPACNTR: 0x%x\n", *dspasurf, *dspacntr);
++    
++    /* Enable surface linear mode */
++    surfb = *dspbsurf;
++    INTEL_DEBUG("DSPBSURF : 0x%x, DSPBCNTR: 0x%x\n", surfb, *dspbcntr);
++    *dspbcntr &= ~(1 << 10);
++    if (linesize) *dspbstride = linesize;
++    *dspbsurf = surfb;
++    INTEL_DEBUG("DSPBSURF : 0x%x, DSPBCNTR: 0x%x\n", *dspbsurf, *dspbcntr);
++    
 +    if (linesize) IntelPitch = linesize;
 +
-+    usleep(50 * 1000); /* 50 ms */
-+
 +    /* Clear the compression bit */
 +    *fbc_ctl &= ~(1 << 31);
 +
@@ -438,69 +398,27 @@ index 0000000..c1a8c45
 +
 +    struct timeval start_compress;
 +
-+    unsigned int surfa = 0, surfb = 0, pipea = 0, pipeb = 0;
-+    char pipeaenabled = !!(*pipeaconf & (1 << 30));
-+    char pipebenabled = !!(*pipebconf & (1 << 30));
++    unsigned int surfa = 0, surfb = 0;
 +
 +    INTEL_DEBUG("restore intel registers\n");
 +    INTEL_DEBUG("   intel_a_was_tiled: %d\n", !!intel_a_was_tiled);
 +    INTEL_DEBUG("   intel_b_was_tiled: %d\n", !!intel_b_was_tiled);
-+    INTEL_DEBUG("DSPASURF CTRL: 0x%x\n", intel_get_reg(REG_DR_DSPACNTR));
-+
-+    if (pipeaenabled)
-+    {
-+        INTEL_DEBUG("PIPEACONF enabled.\n");
-+        /* Disable surface */
-+        pipea = *pipeaconf & (0x3 << 18);
-+        *pipeaconf &= ~(0x3 << 18);
-+        *dspacntr |= (1 << 31);
-+        /* Address of the surface to map to */
-+        surfa = *dspasurf;
-+        *dspasurf = 0x00000000;
-+        *dspacntr &= ~(1 << 31);
-+        *dspasurf = 0x00000000;
-+        *pipeaconf |= pipea;
-+    }
-+
-+    if (pipebenabled) {
-+        INTEL_DEBUG("PIPEBCONF enabled.\n");
-+
-+        /* Disable surface */
-+        pipeb = *pipebconf & (0x3 << 18);
-+        *pipebconf &= ~(0x3 << 18);
-+        *dspbcntr |= (1 << 31);
-+        /* Address of the surface to map to */
-+        surfb = *dspbsurf;
-+        *dspbsurf = 0x00000000;
-+        *dspbcntr &= ~(1 << 31);
-+        *dspbsurf = 0x00000000;
-+        *pipebconf |= pipeb;
-+    }
-+
-+    usleep(50 * 1000); /* 50 ms */
-+
-+    if (pipeaenabled)
-+    {
-+        *pipeaconf &= ~(0x3 << 18);
-+        /* If surface was tiled enable tiled mode */
-+        *dspacntr |= (!!intel_a_was_tiled << 10);
-+        *dspastride = intel_a_stride;
-+        *dspasurf = surfa;
-+        *dspacntr |= (1 << 31);
-+        *pipeaconf |= pipea;
-+    }
-+
-+    if (pipebenabled) {
-+        *pipebconf &= ~(0x3 << 18);
-+        /* If surface was tiled enable tiled mode */
-+        *dspbcntr |= (!!intel_b_was_tiled << 10);
-+        *dspbstride = intel_b_stride;
-+        *dspbsurf = surfb;
-+        *dspbcntr |= (1 << 31);
-+        *pipebconf |= pipeb;
-+    }
 +
-+    usleep(50 * 1000); /* 50 ms */
++    /* If surface was tiled enable tiled mode */
++    surfa = *dspasurf;
++    INTEL_DEBUG("DSPASURF : 0x%x, DSPACNTR: 0x%x\n", surfa, *dspacntr);
++    *dspacntr |= (!!intel_a_was_tiled << 10);
++    *dspastride = intel_a_stride;
++    *dspasurf = surfa;
++    INTEL_DEBUG("DSPASURF : 0x%x, DSPACNTR: 0x%x\n", *dspasurf, *dspacntr);
++    
++    /* If surface was tiled enable tiled mode */
++    surfb = *dspbsurf;
++    INTEL_DEBUG("DSPBSURF : 0x%x, DSPBCNTR: 0x%x\n", surfb, *dspbcntr);
++    *dspbcntr |= (!!intel_b_was_tiled << 10);
++    *dspbstride = intel_b_stride;
++    *dspbsurf = surfb;
++    INTEL_DEBUG("DSPBSURF : 0x%x, DSPBCNTR: 0x%x\n", *dspbsurf, *dspbcntr);
 +
 +    /* enabled compression if it was enabled */
 +    *fbc_ctl &= ~(!!intel_was_compressed << 31);