fix guilt's undereagerness and add back intel.h and intel_reg.h

diff --git a/master/fix-video b/master/fix-video
index 6fa1a1d4892f815249ef2d03aa36b485ea6e2505..69474362bcc56b58f3f88fda96ed3f664cf14866 100644 (file)
--- a/master/fix-video
+++ b/master/fix-video
@@ -11,7 +11,7 @@ index 8c9b09b..def586a 100644
  int is_graphic_console(void);
  int is_fixedsize_console(void);
 diff --git a/hw/vga.c b/hw/vga.c
-index a2b8744..91a08f4 100644
+index a2b8744..e4e27a9 100644
 --- a/hw/vga.c
 +++ b/hw/vga.c
 @@ -34,6 +34,8 @@
@@ -23,7 +23,7 @@ index a2b8744..91a08f4 100644
  //#define DEBUG_VGA
  //#define DEBUG_VGA_MEM
  //#define DEBUG_VGA_REG
-@@ -631,7 +634,8 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
+@@ -631,7 +633,8 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
                  !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
                  int h, shift_control;
  
@@ -33,7 +33,7 @@ index a2b8744..91a08f4 100644
                       set_vram_mapping(s, s->lfb_addr, s->lfb_end);
                  }
  
-@@ -1686,7 +1690,8 @@ static void vga_draw_graphic(VGAState *s, int full_update)
+@@ -1686,7 +1689,8 @@ static void vga_draw_graphic(VGAState *s, int full_update)
          }
      }
  
@@ -148,3 +148,49 @@ index dbf08d2..46949f6 100644
  }
  
  int intel_enter(void)
+@@ -514,5 +495,6 @@ void intel_display_init(DisplayState *ds)
+         ds->surface = surf;
+         dpy_resize(ds);
+     }
++
+     lds = ds;
+ }
+diff --git a/intel.h b/intel.h
+new file mode 100644
+index 0000000..25086be
+--- /dev/null
++++ b/intel.h
+@@ -0,0 +1,5 @@
++extern int intel_output;
++#define INTEL_OUTPUT_UNDEF    0
++#define INTEL_OUTPUT_MAPPED   1
++#define INTEL_OUTPUT_BLITTED  2
++
+diff --git a/intel_reg.h b/intel_reg.h
+new file mode 100644
+index 0000000..cd7855e
+--- /dev/null
++++ b/intel_reg.h
+@@ -0,0 +1,22 @@
++
++#define TileW           128
++#define TileH           8
++
++#define REG_DR_DSPASURF         0x7019C
++#define REG_DR_DSPACNTR         0x70180
++#define REG_DR_DSPASTRIDE       0x70188
++#define REG_DR_PIPEACONF        0x70008
++
++#define REG_DR_DSPBSURF         0x7119C
++#define REG_DR_DSPBCNTR         0x71180
++#define REG_DR_DSPBSTRIDE       0x71188
++#define REG_DR_PIPEBCONF      0x71008
++
++#define REG_DE_PIPEASRC               0x6001c
++#define REG_DE_PIPEBSRC               0x6101c
++
++#define REG_FBC_CONTROL         0x03208
++#define REG_FBC_STATUS          0x03210
++
++
++