The main surface can be surfaceb.

So create an abstraction to get current available surface
and use it.

diff --git a/master/intel b/master/intel
index 684b9034b62d174718acfa522f587387c82269b3..750c6317550cfd0acbffd6f9a23fa86a63028683 100644 (file)
--- a/master/intel
+++ b/master/intel
@@ -33,7 +33,7 @@ index 97214c0..8c9b09b 100644
 +void intel_display_init(DisplayState *ds);
  #endif
 diff --git a/dom0_driver.c b/dom0_driver.c
-index 2dbe199..5806b34 100644
+index d98a458..22501ed 100644
 --- a/dom0_driver.c
 +++ b/dom0_driver.c
 @@ -43,6 +43,7 @@
@@ -215,10 +215,10 @@ index 90bd544..a2b8744 100644
      vga_update_display(s);
 diff --git a/intel.c b/intel.c
 new file mode 100644
-index 0000000..c071866
+index 0000000..f205dfa
 --- /dev/null
 +++ b/intel.c
-@@ -0,0 +1,453 @@
+@@ -0,0 +1,487 @@
 +#include <stdio.h>
 +#include <stdlib.h>
 +#include <stdint.h>
@@ -240,17 +240,18 @@ index 0000000..c071866
 +#define TileW           128
 +#define TileH           8
 +
-+#define REG_DR_DSPASURF               0x7019C
-+#define REG_DR_DSPACNTR               0x70180
-+#define REG_DR_DSPASTRIDE     0x70188
-+#define REG_DR_PIPEACONF      0x70008
++#define REG_DR_DSPASURF         0x7019C
++#define REG_DR_DSPACNTR         0x70180
++#define REG_DR_DSPASTRIDE       0x70188
++#define REG_DR_PIPEACONF        0x70008
 +
-+#define REG_DR_DSPBSURF               0x7119C
-+#define REG_DR_DSPBCNTR               0x71180
-+#define REG_DR_DSPBSTRIDE     0x71188
++#define REG_DR_DSPBSURF         0x7119C
++#define REG_DR_DSPBCNTR         0x71180
++#define REG_DR_DSPBSTRIDE       0x71188
 +#define REG_DR_PIPEBCONF      0x71008
 +
 +#define REG_DE_PIPEASRC               0x6001c
++#define REG_DE_PIPEBSRC               0x6101c
 +
 +extern int                      vga_passthrough;
 +uint32_t                        guest_framebuffer;
@@ -279,6 +280,19 @@ index 0000000..c071866
 +    return *(unsigned int*)(intel_mmio + reg);
 +}
 +
++static char surfaenabled(void)
++{
++    return intel_get_reg(REG_DR_DSPACNTR) & (1 << 31);
++}
++
++static inline unsigned int intel_get_surface(void)
++{
++    if (surfaenabled())
++        return intel_get_reg(REG_DR_DSPASURF);
++    else
++        return intel_get_reg(REG_DR_DSPBSURF);
++}
++
 +static inline int is_linear(void)
 +{
 +    unsigned int *dspacntr = (unsigned int *)(intel_mmio + REG_DR_DSPACNTR);
@@ -288,12 +302,26 @@ index 0000000..c071866
 +        return 0;
 +}
 +
-+static inline unsigned int intel_get_pitch(void)
++static inline void intel_get_res(unsigned int   *x,
++                                 unsigned int   *y,
++                                 unsigned int   *pitch)
 +{
-+    unsigned int *dspastride = (unsigned int *)(intel_mmio + REG_DR_DSPASTRIDE);
-+    return *dspastride;
++    if (surfaenabled())
++    {
++        *pitch = intel_get_reg(REG_DR_DSPASTRIDE);
++        *x = ((intel_get_reg(REG_DE_PIPEASRC) >> 16) & 0xfff) + 1;
++        *y = (intel_get_reg(REG_DE_PIPEASRC) & 0xfff) + 1;
++    }
++    else
++    {
++        *pitch = intel_get_reg(REG_DR_DSPBSTRIDE);
++        *x = ((intel_get_reg(REG_DE_PIPEBSRC) >> 16) & 0xfff) + 1;
++        *y = (intel_get_reg(REG_DE_PIPEBSRC) & 0xfff) + 1;
++    }
 +}
 +
++
++
 +static void intel_force_linear(int linesize)
 +{
 +    unsigned int *dspacntr = (unsigned int *)(intel_mmio + REG_DR_DSPACNTR);
@@ -307,21 +335,26 @@ index 0000000..c071866
 +    unsigned int *dspbstride = (unsigned int *)(intel_mmio + REG_DR_DSPBSTRIDE);
 +
 +    unsigned int surfa = 0, surfb = 0, pipea = 0, pipeb = 0;
++    char pipeaenabled = !!(*pipeaconf & (1 << 30));
 +    char pipebenabled = !!(*pipebconf & (1 << 30));
 +
 +
 +    INTEL_DEBUG("DSPASURF CTRL: 0x%x\n", intel_get_reg(REG_DR_DSPACNTR));
 +
-+    /* Disable surface */
-+    pipea = *pipeaconf & (0x3 << 18);
-+    *pipeaconf &= ~(0x3 << 18);
-+    *dspacntr |= (1 << 31);
-+    /* Address of the surface to map to */
-+    surfa = *dspasurf;
-+    *dspasurf = 0x00000000;
-+    *dspacntr &= ~(1 << 31);
-+    *dspasurf = 0x00000000;
-+    *pipeaconf |= pipea;
++    if (pipeaenabled)
++    {
++        INTEL_DEBUG("PIPEACONF enabled.\n");
++        /* Disable surface */
++        pipea = *pipeaconf & (0x3 << 18);
++        *pipeaconf &= ~(0x3 << 18);
++        *dspacntr |= (1 << 31);
++        /* Address of the surface to map to */
++        surfa = *dspasurf;
++        *dspasurf = 0x00000000;
++        *dspacntr &= ~(1 << 31);
++        *dspasurf = 0x00000000;
++        *pipeaconf |= pipea;
++    }
 +
 +    if (pipebenabled) {
 +        INTEL_DEBUG("PIPEBCONF enabled.\n");
@@ -340,13 +373,16 @@ index 0000000..c071866
 +
 +    usleep(50 * 1000); /* 50 ms */
 +
-+    *pipeaconf &= ~(0x3 << 18);
-+    /* Enable surface linear mode */
-+    *dspacntr &= ~(1 << 10);
-+    if (linesize) *dspastride = linesize;
-+    *dspasurf = surfa;
-+    *dspacntr |= (1 << 31);
-+    *pipeaconf |= pipea;
++    if (pipeaenabled)
++    {
++        *pipeaconf &= ~(0x3 << 18);
++        /* Enable surface linear mode */
++        *dspacntr &= ~(1 << 10);
++        if (linesize) *dspastride = linesize;
++        *dspasurf = surfa;
++        *dspacntr |= (1 << 31);
++        *pipeaconf |= pipea;
++    }
 +
 +    if (pipebenabled) {
 +        *pipebconf &= ~(0x3 << 18);
@@ -369,22 +405,22 @@ index 0000000..c071866
 +    unsigned long nr_pfn;
 +
 +    unset_vga_acc();
-+    INTEL_DEBUG("set_fb_mapping: %x %x\n", (intel_fb_base + intel_get_reg(REG_DR_DSPASURF)), guest_framebuffer);
++    INTEL_DEBUG("set_fb_mapping: %x %x\n", (intel_fb_base + intel_get_surface()), guest_framebuffer);
 +    nr_pfn = (ds_get_linesize(lds) * ds_get_height(lds)) >> TARGET_PAGE_BITS;
 +
 +    rc = xc_domain_memory_mapping(xc_handle,
 +            domid,
 +            (guest_framebuffer >> TARGET_PAGE_BITS),
-+            ((intel_fb_base + intel_get_reg(REG_DR_DSPASURF)) >> TARGET_PAGE_BITS),
++            ((intel_fb_base + intel_get_surface()) >> TARGET_PAGE_BITS),
 +            nr_pfn,
 +            DPCI_ADD_MAPPING);
 +    if (rc) {
 +        fprintf(stderr, "xc_domain_memory_mapping failed %d\n", rc);
 +        return;
 +    }
-+    memcpy((uint8_t *)(intel_mem + intel_get_reg(REG_DR_DSPASURF)),
++    memcpy((uint8_t *)(intel_mem + intel_get_surface()),
 +            ds_get_data(lds), ds_get_linesize(lds) * ds_get_height(lds));
-+    map_s = ((intel_fb_base + intel_get_reg(REG_DR_DSPASURF)) >> TARGET_PAGE_BITS);
++    map_s = ((intel_fb_base + intel_get_surface()) >> TARGET_PAGE_BITS);
 +    map_d = (guest_framebuffer >> TARGET_PAGE_BITS);
 +    map_size = nr_pfn;
 +}
@@ -408,7 +444,7 @@ index 0000000..c071866
 +
 +    set_vga_acc();
 +    memcpy(ds_get_data(lds),
-+            (uint8_t *) (intel_mem + intel_get_reg(REG_DR_DSPASURF)),
++            (uint8_t *) (intel_mem + intel_get_surface()),
 +            ds_get_linesize(lds) * ds_get_height(lds));
 +    map_s = 0;
 +    map_d = 0;
@@ -433,7 +469,7 @@ index 0000000..c071866
 +        h = IntelY - y;
 +
 +    s = ds_get_data(ds);
-+    d = (unsigned char *)(intel_mem + intel_get_reg(REG_DR_DSPASURF));
++    d = (unsigned char *)(intel_mem + intel_get_surface());
 +    /* Center the screen */
 +    if (ds_get_width(ds) < IntelX && ds_get_height(ds) < IntelY)
 +        d += IntelPitch * ((IntelY - ds_get_height(ds)) / 2) +
@@ -543,7 +579,7 @@ index 0000000..c071866
 +
 +static void set_data_pointer(DisplaySurface *surf)
 +{
-+    surf->data = (unsigned char *)(intel_mem + intel_get_reg(REG_DR_DSPASURF));
++    surf->data = (unsigned char *)(intel_mem + intel_get_surface());
 +    memset(surf->data, 0x00, surf->linesize * IntelY);
 +    surf->data = surf->data +
 +                surf->linesize * ((IntelY - surf->height) / 2) +
@@ -562,13 +598,11 @@ index 0000000..c071866
 +
 +    intel_have_focus = focus;
 +    if (intel_have_focus) {
-+        IntelPitch = intel_get_reg(REG_DR_DSPASTRIDE);
-+        IntelX = ((intel_get_reg(REG_DE_PIPEASRC) >> 16) & 0xfff) + 1;
-+        IntelY = (intel_get_reg(REG_DE_PIPEASRC) & 0xfff) + 1;
++        intel_get_res(&IntelX, &IntelY, &IntelPitch);
 +
 +        if (!guest_framebuffer)
 +            intel_force_linear(0);
-+        memset((uint8_t *)(intel_mem + intel_get_reg(REG_DR_DSPASURF)), 0,
++        memset((uint8_t *)(intel_mem + intel_get_surface()), 0,
 +                IntelX * IntelY * 4);
 +    }
 +    vga_hw_invalidate();
@@ -641,7 +675,7 @@ index 0000000..c071866
 +
 +    intel_init_mapping();
 +
-+    INTEL_DEBUG("Frambuffer is at 0x%x\n", intel_get_reg(REG_DR_DSPASURF));
++    INTEL_DEBUG("Frambuffer is at 0x%x\n", intel_get_surface());
 +
 +    dcl = qemu_mallocz(sizeof(DisplayChangeListener));
 +    if (!dcl)