From 09ffeaa39e22c82e507e9ec33af08c799c2dabab Mon Sep 17 00:00:00 2001 From: Jean Guyader Date: Wed, 9 Sep 2009 18:48:06 +0100 Subject: [PATCH] Disable framebuffer compression when we switch to a svm. --- master/intel | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/master/intel b/master/intel index 3d944da..b7d469f 100644 --- a/master/intel +++ b/master/intel @@ -215,10 +215,10 @@ index 90bd544..a2b8744 100644 vga_update_display(s); diff --git a/intel.c b/intel.c new file mode 100644 -index 0000000..85968cb +index 0000000..df9ebf7 --- /dev/null +++ b/intel.c -@@ -0,0 +1,508 @@ +@@ -0,0 +1,517 @@ +#include +#include +#include @@ -254,6 +254,9 @@ index 0000000..85968cb +#define REG_DE_PIPEASRC 0x6001c +#define REG_DE_PIPEBSRC 0x6101c + ++#define REG_FBC_CONTROL 0x03208 ++#define REG_FBC_STATUS 0x03210 ++ +extern int vga_passthrough; +uint32_t guest_framebuffer; +int intel_output; @@ -328,12 +331,12 @@ index 0000000..85968cb + unsigned int *pipebconf = (unsigned int *)(intel_mmio + REG_DR_PIPEBCONF); + unsigned int *dspbsurf = (unsigned int *)(intel_mmio + REG_DR_DSPBSURF); + unsigned int *dspbstride = (unsigned int *)(intel_mmio + REG_DR_DSPBSTRIDE); ++ volatile unsigned int *fbc_ctl = (unsigned int *)(intel_mmio + REG_FBC_CONTROL); + + unsigned int surfa = 0, surfb = 0, pipea = 0, pipeb = 0; + char pipeaenabled = !!(*pipeaconf & (1 << 30)); + char pipebenabled = !!(*pipebconf & (1 << 30)); + -+ + INTEL_DEBUG("DSPASURF CTRL: 0x%x\n", intel_get_reg(REG_DR_DSPACNTR)); + + if (pipeaenabled) @@ -390,7 +393,13 @@ index 0000000..85968cb + } + if (linesize) IntelPitch = linesize; + -+ usleep(50 * 1000); /* 500 ms */ ++ usleep(50 * 1000); /* 50 ms */ ++ ++ /* Clear the compression bit */ ++ *fbc_ctl &= ~(1 << 31); ++ /* Wait for the status register */ ++ while (intel_get_reg(REG_FBC_STATUS) & (1 << 31)) ++ ; +} + +static void set_fb_mapping(void) -- 2.39.5