1 diff --git a/drivers/xen/pciback/controller.c b/drivers/xen/pciback/controller.c
2 --- a/drivers/xen/pciback/controller.c
3 +++ b/drivers/xen/pciback/controller.c
7 spin_unlock_irqrestore(&dev_data->lock, flags);
8 - pcistub_put_pci_dev(found_dev);
9 + pcistub_put_pci_dev(found_dev, 0);
12 int pciback_init_devices(struct pciback_device *pdev)
14 list_for_each_entry_safe(dev_entry, d,
15 &cntrl_entry->dev_list, list) {
16 list_del(&dev_entry->list);
17 - pcistub_put_pci_dev(dev_entry->dev);
18 + pcistub_put_pci_dev(dev_entry->dev, 0);
21 list_del(&cntrl_entry->list);
22 diff --git a/drivers/xen/pciback/passthrough.c b/drivers/xen/pciback/passthrough.c
23 --- a/drivers/xen/pciback/passthrough.c
24 +++ b/drivers/xen/pciback/passthrough.c
26 spin_unlock_irqrestore(&dev_data->lock, flags);
29 - pcistub_put_pci_dev(found_dev);
30 + pcistub_put_pci_dev(found_dev, 1);
33 int pciback_init_devices(struct pciback_device *pdev)
36 list_for_each_entry_safe(dev_entry, t, &dev_data->dev_list, list) {
37 list_del(&dev_entry->list);
38 - pcistub_put_pci_dev(dev_entry->dev);
39 + pcistub_put_pci_dev(dev_entry->dev, 1);
43 diff --git a/drivers/xen/pciback/pci_stub.c b/drivers/xen/pciback/pci_stub.c
44 --- a/drivers/xen/pciback/pci_stub.c
45 +++ b/drivers/xen/pciback/pci_stub.c
47 * We want to avoid in middle of AER ops, pciback devices is being removed
49 static DECLARE_RWSEM(pcistub_sem);
50 -module_param_named(hide, pci_devs_to_hide, charp, 0444);
51 +module_param_named(hide, pci_devs_to_hide, charp, S_IRUGO);
53 +static char *pci_devs_use_sbr = NULL;
54 +module_param_named(sbr, pci_devs_use_sbr, charp, S_IRUGO);
56 +static char *pci_devs_use_d3r = NULL;
57 +module_param_named(d3r, pci_devs_use_d3r, charp, S_IRUGO);
59 +static char *pci_devs_no_flr = NULL;
60 +module_param_named(noflr, pci_devs_no_flr, charp, S_IRUGO);
62 +/* Device id list holding different device type listings
63 + * for hiding devices and reset logic.
65 +#define PCIBACK_ID_TYPE_HIDE 1
66 +#define PCIBACK_ID_TYPE_SBR 2
67 +#define PCIBACK_ID_TYPE_D3R 3
68 +#define PCIBACK_ID_TYPE_NOFLR 4
70 struct pcistub_device_id {
71 struct list_head slot_list;
77 static int initialize_devices = 0;
78 static LIST_HEAD(seized_devices);
80 +static int disable_all_flr = 0;
82 static struct pcistub_device *pcistub_device_alloc(struct pci_dev *dev)
84 struct pcistub_device *psdev;
86 spin_lock_init(&psdev->lock);
91 +static struct pciback_dev_data *pcistub_dev_data_alloc(struct pci_dev *dev)
93 + struct pciback_dev_data *dev_data;
95 + dev_dbg(&dev->dev, "pcistub_dev_data_alloc\n");
97 + dev_data = kzalloc(sizeof(*dev_data) + dev->cfg_size, GFP_ATOMIC);
101 + pci_set_drvdata(dev, dev_data);
103 + dev_data->cfg_space = (u8*)(dev_data) + sizeof(*dev_data);
108 /* Don't call this directly as it's called by pcistub_device_put */
113 -void pcistub_put_pci_dev(struct pci_dev *dev)
114 +void pcistub_put_pci_dev(struct pci_dev *dev, int do_flr)
116 struct pcistub_device *psdev, *found_psdev = NULL;
119 * pcistub and pciback when AER is in processing
121 down_write(&pcistub_sem);
123 + /* For pass-through devices, do an FLR (or approximate) for the device
124 + * before it is put back and ready for the next domain
126 + if (!disable_all_flr && do_flr)
127 + pciback_flr_device(dev);
129 /* Cleanup our device
130 * (so it's ready for the next domain)
134 pcistub_device_put(found_psdev);
135 up_write(&pcistub_sem);
138 +struct pci_dev *pcistub_ref_pci_dev(struct pci_dev *dev)
140 + struct pcistub_device *psdev;
141 + struct pci_dev *found_dev = NULL;
142 + unsigned long flags;
144 + spin_lock_irqsave(&pcistub_devices_lock, flags);
146 + list_for_each_entry(psdev, &pcistub_devices, dev_list) {
147 + if (psdev->dev == dev) {
148 + pcistub_device_get(psdev); /* just a ref count */
149 + found_dev = psdev->dev;
154 + spin_unlock_irqrestore(&pcistub_devices_lock, flags);
158 +void pcistub_unref_pci_dev(struct pci_dev *dev)
160 + struct pcistub_device *psdev;
161 + unsigned long flags;
163 + spin_lock_irqsave(&pcistub_devices_lock, flags);
165 + list_for_each_entry(psdev, &pcistub_devices, dev_list) {
166 + if (psdev->dev == dev) {
167 + pcistub_device_get(psdev); /* just an unref count */
172 + spin_unlock_irqrestore(&pcistub_devices_lock, flags);
175 static int __devinit pcistub_match_one(struct pci_dev *dev,
180 -static int __devinit pcistub_match(struct pci_dev *dev)
181 +static int __devinit pcistub_match(struct pci_dev *dev, int type)
183 struct pcistub_device_id *pdev_id;
187 spin_lock_irqsave(&device_ids_lock, flags);
188 list_for_each_entry(pdev_id, &pcistub_device_ids, slot_list) {
189 + if (pdev_id->type != type)
191 if (pcistub_match_one(dev, pdev_id)) {
194 @@ -285,12 +368,11 @@
195 * would need to be called somewhere to free the memory allocated
196 * here and then to call kfree(pci_get_drvdata(psdev->dev)).
198 - dev_data = kzalloc(sizeof(*dev_data), GFP_ATOMIC);
199 + dev_data = pcistub_dev_data_alloc(dev);
204 - pci_set_drvdata(dev, dev_data);
206 dev_dbg(&dev->dev, "initializing config\n");
210 dev_dbg(&dev->dev, "reset device\n");
211 pciback_reset_device(dev);
213 + /* Classify the device so we know if it is PCI/PCIe and if it is
214 + * a bridge - this information is used for FLR logic. Also store
215 + * values if SBR/D3R reset logic was requested.
217 + pciback_classify_device(dev);
218 + dev_data->no_flr = pcistub_match(dev, PCIBACK_ID_TYPE_NOFLR);
219 + if (!dev_data->no_flr) {
220 + dev_data->use_sbr = pcistub_match(dev, PCIBACK_ID_TYPE_SBR);
221 + dev_data->use_d3r = pcistub_match(dev, PCIBACK_ID_TYPE_D3R);
224 + /* Store the config space here where the device is off and ready to be
225 + * exported before any FLRs or other resets are done
227 + pciback_store_config_space(dev);
233 dev_dbg(&dev->dev, "probing...\n");
235 - if (pcistub_match(dev)) {
236 + if (pcistub_match(dev, PCIBACK_ID_TYPE_HIDE)) {
238 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL
239 && dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
244 -static int pcistub_device_id_add(int domain, int bus, int slot, int func)
245 +static int pcistub_device_id_add(int domain, int bus, int slot, int func, int type)
247 struct pcistub_device_id *pci_dev_id;
249 @@ -860,12 +958,13 @@
253 + pci_dev_id->type = type;
254 pci_dev_id->domain = domain;
255 pci_dev_id->bus = bus;
256 pci_dev_id->devfn = PCI_DEVFN(slot, func);
258 - pr_debug("pciback: wants to seize %04x:%02x:%02x.%01x\n",
259 - domain, bus, slot, func);
260 + pr_debug("pciback: adding device ID type: %d for %04x:%02x:%02x.%01x\n",
261 + type, domain, bus, slot, func);
263 spin_lock_irqsave(&device_ids_lock, flags);
264 list_add_tail(&pci_dev_id->slot_list, &pcistub_device_ids);
269 -static int pcistub_device_id_remove(int domain, int bus, int slot, int func)
270 +static int pcistub_device_id_remove(int domain, int bus, int slot, int func, int type)
272 struct pcistub_device_id *pci_dev_id, *t;
273 int devfn = PCI_DEVFN(slot, func);
275 spin_lock_irqsave(&device_ids_lock, flags);
276 list_for_each_entry_safe(pci_dev_id, t, &pcistub_device_ids, slot_list) {
278 - if (pci_dev_id->domain == domain
279 + if (pci_dev_id->type == type && pci_dev_id->domain == domain
280 && pci_dev_id->bus == bus && pci_dev_id->devfn == devfn) {
281 /* Don't break; here because it's possible the same
282 * slot could be in the list more than once
283 @@ -939,6 +1038,32 @@
287 +static int pcistub_device_do_flr(int domain, int bus, int slot, int func)
290 + struct pcistub_device *psdev;
291 + struct pci_dev *dev;
293 + psdev = pcistub_device_find(domain, bus, slot, func);
294 + if (!psdev || !psdev->dev) {
300 + /* Do an FLR (or approximate) for the device on demand and
303 + if (!disable_all_flr) {
304 + pciback_flr_device(dev);
307 + dev_dbg(&dev->dev, "FLR disabled for all devices\n");
313 static ssize_t pcistub_slot_add(struct device_driver *drv, const char *buf,
320 - err = pcistub_device_id_add(domain, bus, slot, func);
321 + err = pcistub_device_id_add(domain, bus, slot, func, PCIBACK_ID_TYPE_HIDE);
329 - err = pcistub_device_id_remove(domain, bus, slot, func);
330 + err = pcistub_device_id_remove(domain, bus, slot, func, PCIBACK_ID_TYPE_HIDE);
334 @@ -987,6 +1112,10 @@
336 spin_lock_irqsave(&device_ids_lock, flags);
337 list_for_each_entry(pci_dev_id, &pcistub_device_ids, slot_list) {
338 + /* only want devices set for hide, not reset entries */
339 + if (pci_dev_id->type != PCIBACK_ID_TYPE_HIDE)
342 if (count >= PAGE_SIZE)
345 @@ -1068,7 +1197,7 @@
347 DRIVER_ATTR(quirks, S_IRUSR | S_IWUSR, pcistub_quirk_show, pcistub_quirk_add);
349 -static ssize_t permissive_add(struct device_driver *drv, const char *buf,
350 +static ssize_t pcistub_permissive_add(struct device_driver *drv, const char *buf,
353 int domain, bus, slot, func;
354 @@ -1109,7 +1238,7 @@
358 -static ssize_t permissive_show(struct device_driver *drv, char *buf)
359 +static ssize_t pcistub_permissive_show(struct device_driver *drv, char *buf)
361 struct pcistub_device *psdev;
362 struct pciback_dev_data *dev_data;
363 @@ -1132,7 +1261,68 @@
367 -DRIVER_ATTR(permissive, S_IRUSR | S_IWUSR, permissive_show, permissive_add);
368 +DRIVER_ATTR(permissive, S_IRUSR | S_IWUSR, pcistub_permissive_show, pcistub_permissive_add);
370 +static ssize_t pcistub_do_flr(struct device_driver *drv, const char *buf,
373 + int domain, bus, slot, func;
376 + err = str_to_slot(buf, &domain, &bus, &slot, &func);
380 + err = pcistub_device_do_flr(domain, bus, slot, func);
388 +DRIVER_ATTR(do_flr, S_IWUSR, NULL, pcistub_do_flr);
390 +static ssize_t pcistub_resets(struct device_driver *drv, const char *buf,
393 + int domain, bus, slot, func;
396 + /* string begins with reset type specifier sbr=|dr3=|noflr= */
397 + if (!strncmp(buf, "sbr=", 4)) {
398 + type = PCIBACK_ID_TYPE_SBR;
400 + } else if (!strncmp(buf, "d3r=", 4)) {
401 + type = PCIBACK_ID_TYPE_D3R;
403 + } else if (!strncmp(buf, "noflr=", 6)) {
404 + type = PCIBACK_ID_TYPE_NOFLR;
411 + /* check special wildcard noflr */
412 + if (type == PCIBACK_ID_TYPE_NOFLR && !strncmp(buf, "(*)", 3)) {
413 + disable_all_flr = 1;
417 + err = str_to_slot(buf, &domain, &bus, &slot, &func);
421 + err = pcistub_device_id_add(domain, bus, slot, func, type);
429 +DRIVER_ATTR(resets, S_IWUSR, NULL, pcistub_resets);
431 #ifdef CONFIG_PCI_MSI
433 @@ -1158,6 +1348,8 @@
434 driver_remove_file(&pciback_pci_driver.driver, &driver_attr_slots);
435 driver_remove_file(&pciback_pci_driver.driver, &driver_attr_quirks);
436 driver_remove_file(&pciback_pci_driver.driver, &driver_attr_permissive);
437 + driver_remove_file(&pciback_pci_driver.driver, &driver_attr_do_flr);
438 + driver_remove_file(&pciback_pci_driver.driver, &driver_attr_resets);
440 pci_unregister_driver(&pciback_pci_driver);
441 WARN_ON(unregister_msi_get_owner(pciback_get_owner));
442 @@ -1165,35 +1357,27 @@
444 static int __init pcistub_init(void)
448 - int domain, bus, slot, func;
451 - if (pci_devs_to_hide && *pci_devs_to_hide) {
454 + /* Parse device lists for hide, sbr, and d3r */
455 + err = pciback_parse_device_params(pci_devs_to_hide, PCIBACK_ID_TYPE_HIDE, pcistub_device_id_add);
459 - err = sscanf(pci_devs_to_hide + pos,
460 - " (%x:%x:%x.%x) %n",
461 - &domain, &bus, &slot, &func, &parsed);
464 - err = sscanf(pci_devs_to_hide + pos,
466 - &bus, &slot, &func, &parsed);
470 + err = pciback_parse_device_params(pci_devs_use_sbr, PCIBACK_ID_TYPE_SBR, pcistub_device_id_add);
474 - err = pcistub_device_id_add(domain, bus, slot, func);
477 + err = pciback_parse_device_params(pci_devs_use_d3r, PCIBACK_ID_TYPE_D3R, pcistub_device_id_add);
481 - /* if parsed<=0, we've reached the end of the string */
483 - } while (parsed > 0 && pci_devs_to_hide[pos]);
485 + if (pci_devs_no_flr && *pci_devs_no_flr && !strncmp(pci_devs_no_flr, "(*)", 3))
486 + disable_all_flr = 1; /* check special wildcard noflr */
488 + err = pciback_parse_device_params(pci_devs_no_flr, PCIBACK_ID_TYPE_NOFLR, pcistub_device_id_add);
492 /* If we're the first PCI Device Driver to register, we're the
493 * first one to get offered PCI devices as they become
494 @@ -1217,6 +1401,12 @@
496 err = driver_create_file(&pciback_pci_driver.driver,
497 &driver_attr_permissive);
499 + err = driver_create_file(&pciback_pci_driver.driver,
500 + &driver_attr_do_flr);
502 + err = driver_create_file(&pciback_pci_driver.driver,
503 + &driver_attr_resets);
506 err = register_msi_get_owner(pciback_get_owner);
507 @@ -1225,11 +1415,6 @@
513 - printk(KERN_ERR "pciback: Error parsing pci_devs_to_hide at \"%s\"\n",
514 - pci_devs_to_hide + pos);
519 diff --git a/drivers/xen/pciback/pciback.h b/drivers/xen/pciback/pciback.h
520 --- a/drivers/xen/pciback/pciback.h
521 +++ b/drivers/xen/pciback/pciback.h
523 #define _PCIB_op_pending (1)
524 #define PCIB_op_pending (1<<(_PCIB_op_pending))
526 +#define PCIBACK_TYPE_UNKNOWN 0
527 +#define PCIBACK_TYPE_PCIe_ENDPOINT 1
528 +#define PCIBACK_TYPE_PCIe_BRIDGE 2
529 +#define PCIBACK_TYPE_PCI_BRIDGE 3
530 +#define PCIBACK_TYPE_PCI 4
532 +#define DEV_CLASS_PCI_PCI_BRIDGE 0x0604
534 struct pciback_device {
538 struct list_head config_fields;
543 + int exp_flr_offset;
547 + u8 *cfg_space; /* saved config space for device */
550 /* Get/Put PCI Devices that are hidden from the PCI Backend Domain */
553 struct pci_dev *pcistub_get_pci_dev(struct pciback_device *pdev,
554 struct pci_dev *dev);
555 -void pcistub_put_pci_dev(struct pci_dev *dev);
556 +void pcistub_put_pci_dev(struct pci_dev *dev, int do_flr);
558 +/* Reference/unreference PCI Devices and stubs without changing the state */
559 +struct pci_dev *pcistub_ref_pci_dev(struct pci_dev *dev);
560 +void pcistub_unref_pci_dev(struct pci_dev *dev);
562 +/* Store/reload config space for devices */
563 +void pciback_store_config_space(struct pci_dev *dev);
564 +void pciback_reload_config_space(struct pci_dev *dev);
566 /* Ensure a device is turned off or reset */
567 void pciback_reset_device(struct pci_dev *pdev);
569 +/* Do a function level reset (or approximage functionality) for device */
570 +void pciback_flr_device(struct pci_dev *dev);
572 +/* Helper to classify the device type */
573 +void pciback_classify_device(struct pci_dev *dev);
575 /* Access a virtual configuration space for a PCI device */
576 int pciback_config_init(void);
578 irqreturn_t pciback_handle_event(int irq, void *dev_id);
579 void pciback_do_op(struct work_struct *work);
581 +/* Parse and load device specific module parameters */
582 +int pciback_parse_device_params(const char *device_args, int type,
583 + int (*add_func) (int domain, int bus, int slot, int func, int type));
585 int pciback_xenbus_register(void);
586 void pciback_xenbus_unregister(void);
588 diff --git a/drivers/xen/pciback/pciback_ops.c b/drivers/xen/pciback/pciback_ops.c
589 --- a/drivers/xen/pciback/pciback_ops.c
590 +++ b/drivers/xen/pciback/pciback_ops.c
592 #include <xen/evtchn.h>
595 +#define PCIBACK_VENDOR_INTEL 0x8086
596 +#define PCIBACK_CLASS_ID_USB 0x0c03
597 +#define PCIBACK_CLASS_ID_VGA 0x0300
598 +#define PCIBACK_USB_FLRCTRL 0x4
600 +#define PCIBACK_IGFX_CAP09_OFFSET 0xa4
601 +#define PCIBACK_IGFX_CAP13_OFFSET 0xa4
603 +#define PCIBACK_IGFX_MEDIARST 0x0d
604 +#define PCIBACK_IGFX_MEDIARST_OFFSET 0xc0
606 int verbose_request = 0;
607 module_param(verbose_request, int, 0644);
609 +struct pcistub_sbr_entry {
610 + struct list_head dev_list;
611 + struct pci_dev *dev;
614 +struct pcistub_sbr_list {
615 + struct list_head dev_list;
616 + struct pci_dev *bridge;
617 + struct pci_dev *dev;
622 +/* Used to store the config state so it can be restored after
625 +void pciback_store_config_space(struct pci_dev *dev)
627 + struct pciback_dev_data *dev_data = pci_get_drvdata(dev);
628 + u32 *ptr = (u32*)dev_data->cfg_space;
629 + int i, count = dev->cfg_size/sizeof(u32);
631 + for (i = 0; i < count; i += sizeof(u32), ptr++)
632 + pci_read_config_dword(dev, i, ptr);
635 +/* Used to reload the config state after resets.
637 +void pciback_reload_config_space(struct pci_dev *dev)
639 + struct pciback_dev_data *dev_data = pci_get_drvdata(dev);
640 + u32 *ptr = (u32*)dev_data->cfg_space;
641 + int i, val, count = dev->cfg_size/sizeof(u32);
643 + for (i = 0; i < count; i += sizeof(u32), ptr++) {
644 + pci_read_config_dword(dev, i, &val);
646 + pci_write_config_dword(dev, i, *ptr);
650 +static void pciback_walk_bus_cb(struct pci_dev *dev, void *userdata)
652 + struct pcistub_sbr_list *list = (struct pcistub_sbr_list*)userdata;
653 + struct pcistub_sbr_entry *entry;
654 + struct pci_dev *dev_tmp;
656 + if (list->err != 0)
659 + /* For PCIe endpoints we are only looking for co-assigned functions */
660 + if (!list->find_all &&
661 + (dev->bus->number != list->dev->bus->number ||
662 + PCI_SLOT(dev->devfn) != PCI_SLOT(list->dev->devfn)))
665 + dev_tmp = pcistub_ref_pci_dev(dev);
666 + if (dev_tmp == NULL) {
667 + /* not controlled by pciback, fail */
672 + entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
673 + if (entry == NULL) {
674 + pcistub_unref_pci_dev(dev_tmp);
675 + list->err = ENOMEM;
679 + entry->dev = dev_tmp;
680 + list_add_tail(&entry->dev_list, &list->dev_list);
683 +static void pciback_cleanup_sbr_list(struct pcistub_sbr_list *list)
685 + struct pcistub_sbr_entry *entry;
687 + list_for_each_entry(entry, &list->dev_list, dev_list) {
688 + pcistub_unref_pci_dev(entry->dev);
693 +/* Routine to find all devices and bridges that need to be reset
694 + * during a secondary bus reset. For PCIe this is simply all the
695 + * functions on the particular device. For PCI this is all devices
696 + * and bridges below the topmost PCI/PCI-X bridge. Note for PCI,
697 + * there is at least one something->PCI/PCI-X bridge to find since
698 + * the device is not on the host bus 0 and is on a PCI bus.
700 +static int pciback_get_sbr_list(struct pci_dev *dev,
701 + struct pcistub_sbr_list *list, int pcie_endpoint)
703 + struct pci_dev *bridge = dev->bus->self;
704 + struct pci_dev *last = NULL;
710 + INIT_LIST_HEAD(&list->dev_list);
712 + if (!pcie_endpoint) {
714 + /* Looking for the uppermost PCI/PCI-X bridge. If it is not PCIe then
715 + * this is a PCI/PCI-X bridge. If it is PCIe then except the PCIe to
716 + * PCI/PCI-X type 7, the rest of the bridge types are PCIe so the last
717 + * bridge encountered was the topmost PCI/PCI-X bridge.
719 + exp_pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
720 + if (exp_pos != 0) {
721 + pci_read_config_word(bridge, exp_pos + PCI_EXP_FLAGS, &exp_caps);
722 + if (((exp_caps & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_PCI_BRIDGE)
723 + break; /* don't want it in the list if it is a PCIe bridge */
726 + bridge = last->bus->self;
728 + list->bridge = last;
729 + list->find_all = 1; /* find all devices/bridges below the topmost */
733 + /* For PCIe, SBR logic is limited to PCIe endpoints behind a root/switch
736 + exp_pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
737 + if (likely(exp_pos != 0)) {
738 + pci_read_config_word(bridge, exp_pos + PCI_EXP_FLAGS, &exp_caps);
739 + exp_caps = ((exp_caps & PCI_EXP_FLAGS_TYPE) >> 4);
740 + if (exp_caps == PCI_EXP_TYPE_ROOT_PORT ||
741 + exp_caps == PCI_EXP_TYPE_UPSTREAM ||
742 + exp_caps == PCI_EXP_TYPE_DOWNSTREAM)
746 + list->bridge = last;
747 + list->find_all = 0; /* find just functions on this slot */
750 + /* Sanity check, there may not be any appropriate bridge to reset */
751 + if (!list->bridge) {
752 + dev_dbg(&dev->dev, "No appropriate bridge to reset\n");
756 + pci_walk_bus(list->bridge->subordinate, pciback_walk_bus_cb, list);
759 + pciback_cleanup_sbr_list(list);
766 /* Ensure a device is "turned off" and ready to be exported.
767 * (Also see pciback_config_reset to ensure virtual configuration space is
770 void pciback_reset_device(struct pci_dev *dev)
775 /* Disable devices (but not bridges) */
776 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
782 +/* Do a PCIe type function level reset for a single function on this
785 +static void pciback_do_pcie_flr(struct pci_dev *dev, int exp_pos)
789 + dev_dbg(&dev->dev, "doing PCIe FLR\n");
791 + pci_block_user_cfg_access(dev);
793 + /* Wait for Transaction Pending bit clean */
795 + pci_read_config_word(dev, exp_pos + PCI_EXP_DEVSTA, &status);
796 + if (status & PCI_EXP_DEVSTA_TRPND) {
797 + dev_dbg(&dev->dev, "Busy after 100ms while trying to reset; sleeping for 1 second\n");
799 + pci_read_config_word(dev, exp_pos + PCI_EXP_DEVSTA, &status);
800 + if (status & PCI_EXP_DEVSTA_TRPND)
801 + dev_warn(&dev->dev, "Still busy after 1s; proceeding with reset anyway\n");
804 + pci_write_config_word(dev, exp_pos + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
807 + pciback_reload_config_space(dev);
809 + pci_unblock_user_cfg_access(dev);
812 +/* Do a PCI type function level reset for a single function on this
813 + * device. This uses the Advanced Features Capability extensions to
816 +static void pciback_do_pci_flr(struct pci_dev *dev, int af_pos, int clear_cmd)
820 + dev_dbg(&dev->dev, "doing PCI FLR\n");
822 + pci_block_user_cfg_access(dev);
824 + /* Clear the command register to prevent new transactions */
826 + pci_write_config_word(dev, PCI_COMMAND, 0);
828 + /* Wait for Transaction Pending bit clean */
830 + pci_read_config_byte(dev, af_pos + PCI_AF_STA, &status);
831 + if (status & PCI_AF_STA_TP) {
832 + dev_dbg(&dev->dev, "Busy after 100ms while trying to reset; sleeping for 1 second\n");
834 + pci_read_config_byte(dev, af_pos + PCI_AF_STA, &status);
835 + if (status & PCI_AF_STA_TP)
836 + dev_warn(&dev->dev, "Still busy after 1s; proceeding with reset anyway\n");
839 + pci_write_config_byte(dev, af_pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
842 + pciback_reload_config_space(dev);
844 + pci_unblock_user_cfg_access(dev);
847 +/* Vendor specific resets. These can be set in the vendor specific
848 + * capabilities structures. Currently only the Intel USB and iGFX
849 + * reset is supported.
851 +static int pciback_do_vendor_specific_reset(struct pci_dev *dev)
853 + struct pci_dev *gmch;
856 + u16 device_id, cmd;
859 + dev_dbg(&dev->dev, "doing vendor specific resets\n");
861 + if (dev->vendor != PCIBACK_VENDOR_INTEL)
864 + if ((dev->class >> 8) == PCIBACK_CLASS_ID_VGA) {
865 + if (dev->bus->number != 0 || dev->devfn != PCI_DEVFN(2,0))
868 + /* Locate the GMCH (north bridge) and test for specific Intel devices */
869 + gmch = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
873 + device_id = gmch->device;
876 + if (device_id != PCI_DEVICE_ID_INTEL_GMCHGM45)
879 + /* Correct device and platform, assume vendor specific offset */
880 + pci_read_config_dword(dev, PCIBACK_IGFX_CAP09_OFFSET, ®32);
881 + if ((reg32 & 0x000000FF) != PCI_CAP_ID_VNDR ||
882 + ((reg32 >> 16) & 0x000000FF) != 0x06 ||
883 + ((reg32 >> 24) & 0x000000F0) != 0x20)
886 + vendor_pos = PCIBACK_IGFX_CAP09_OFFSET;
887 + } else if ((dev->class >> 8) == PCIBACK_CLASS_ID_USB) {
888 + vendor_pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
889 + if (vendor_pos == 0)
895 + if ((dev->class >> 8) == PCIBACK_CLASS_ID_VGA) {
896 + pci_write_config_byte(dev, PCIBACK_IGFX_MEDIARST_OFFSET, PCIBACK_IGFX_MEDIARST);
897 + for (i = 0; i <= 10; i++) {
899 + pci_read_config_byte(dev, PCIBACK_IGFX_MEDIARST_OFFSET, ®8);
900 + if ((reg8 & 0x01) == 0)
903 + dev_warn(&dev->dev, "media not reset after 1s; skipping FLR\n");
908 + /* This specific reset will hang if the command register does not have
909 + * memory space access enabled */
910 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
911 + pci_write_config_word(dev, PCI_COMMAND, (cmd | PCI_COMMAND_MEMORY));
912 + /* The rest is the same as a PCI AF FLR - use the same routine */
913 + pciback_do_pci_flr(dev, vendor_pos, 0);
914 + pci_write_config_word(dev, PCI_COMMAND, cmd);
916 + pci_block_user_cfg_access(dev);
918 + pci_write_config_byte(dev, vendor_pos + PCIBACK_USB_FLRCTRL, 1);
921 + pciback_reload_config_space(dev);
923 + pci_unblock_user_cfg_access(dev);
930 +/* Use a D0-D3-D0 device state transition to reset the device. This
931 + * is a good enough reset for some devices (like NICs).
933 +static int pciback_do_dstate_transition_reset(struct pci_dev *dev)
938 + pm_pos = pci_find_capability(dev, PCI_CAP_ID_PM);
942 + dev_dbg(&dev->dev, "doing Dstate transition reset\n");
944 + /* No_Soft_Reset - When set 1, this bit indicates that devices
945 + * transitioning from D3hot to D0 because of PowerState commands
946 + * do not perform an internal reset.
948 + pci_read_config_dword(dev, pm_pos + PCI_PM_CTRL, &pm_ctl);
949 + if (pm_ctl & PCI_PM_CTRL_NO_SOFT_RESET)
952 + pci_block_user_cfg_access(dev);
954 + pm_ctl &= ~PCI_PM_CTRL_STATE_MASK;
955 + pm_ctl |= PCI_PM_CTRL_D3HOT;
956 + pci_write_config_word(dev, pm_pos + PCI_PM_CTRL, pm_ctl);
959 + pm_ctl &= ~PCI_PM_CTRL_STATE_MASK;
960 + pm_ctl |= PCI_PM_CTRL_D0;
961 + pci_write_config_word(dev, pm_pos + PCI_PM_CTRL, pm_ctl);
964 + pciback_reload_config_space(dev);
966 + pci_unblock_user_cfg_access(dev);
971 +/* Do a secondary bus reset on a bridge. This is only done if all
972 + * co-assignment rules are satisfied and if it was explicitly
973 + * requested via pciback parameters.
975 +static int pciback_do_secondary_bus_reset(struct pci_dev *dev, u32 dev_type)
977 + struct pcistub_sbr_list sbr_list;
978 + struct pcistub_sbr_entry *entry;
982 + /* Call helper to get the device list needed for the device type. */
983 + err = pciback_get_sbr_list(dev, &sbr_list,
984 + (dev_type == PCIBACK_TYPE_PCIe_ENDPOINT ? 1 : 0));
986 + dev_warn(&dev->dev,
987 + "secondary bus reset failed for device - all functions need to be co-assigned - err: %d\n", err);
991 + pci_block_user_cfg_access(dev);
993 + /* Reset the secondary bus and restore the PCI space for all the devfn found above.
995 + pci_read_config_word(sbr_list.bridge, PCI_BRIDGE_CONTROL, &pci_bctl);
996 + pci_write_config_word(sbr_list.bridge, PCI_BRIDGE_CONTROL, pci_bctl | PCI_BRIDGE_CTL_BUS_RESET);
998 + pci_write_config_word(sbr_list.bridge, PCI_BRIDGE_CONTROL, pci_bctl);
1001 + list_for_each_entry(entry, &sbr_list.dev_list, dev_list) {
1002 + pciback_reload_config_space(entry->dev);
1005 + pci_unblock_user_cfg_access(dev);
1007 + pciback_cleanup_sbr_list(&sbr_list);
1012 +/* This function is used to do a function level reset on a singe
1013 + * device/function. FLRs must be done on devices before they are
1014 + * unassigned from one domain and passed through to another. The
1015 + * preferred method is to do an actual FLR on the device but the
1016 + * functionality may not be present or exposed. In the later case
1017 + * we attempt to locate the capability even though it is not
1018 + * chained into the capabilities list.
1020 + * In some cases, there is no way to perform the actual FLR so we
1021 + * fall back to some alternate methods (which are not as effective
1024 +void pciback_flr_device(struct pci_dev *dev)
1026 + struct pciback_dev_data *dev_data = pci_get_drvdata(dev);
1029 + if (dev_data->no_flr) {
1030 + dev_dbg(&dev->dev, "FLR disabled for device\n");
1033 + dev_dbg(&dev->dev, "FLR invoked for device\n");
1036 + /* First, always try to do an FLR */
1037 + if (dev_data->dev_type == PCIBACK_TYPE_PCIe_ENDPOINT &&
1038 + dev_data->exp_flr_offset != 0) {
1039 + pciback_do_pcie_flr(dev, dev_data->exp_flr_offset);
1042 + if (dev_data->dev_type == PCIBACK_TYPE_PCI &&
1043 + dev_data->af_flr_offset != 0) {
1044 + pciback_do_pci_flr(dev, dev_data->af_flr_offset, 1);
1048 + /* Next for integrated devices on the host bus 0, try some other methods */
1049 + if (dev->bus->number == 0) {
1050 + err = pciback_do_vendor_specific_reset(dev);
1051 + if (err && dev_data->use_d3r)
1052 + err = pciback_do_dstate_transition_reset(dev);
1054 + dev_warn(&dev->dev, "FLR functionality not supported; "
1055 + "attempts to use vendor FLR or D-states unsuccessful\n");
1059 + /* Else attempt a secondary bus reset if all conditions are met */
1060 + if (dev_data->use_sbr) {
1061 + err = pciback_do_secondary_bus_reset(dev, dev_data->dev_type);
1063 + dev_warn(&dev->dev, "FLR functionality not supported; "
1064 + "attempts to use secondary bus reset unsuccessful;\n");
1072 + dev_warn(&dev->dev, "FLR not performed for device\n");
1075 +/* Helper used to location the FLR capabilities for a PCIe device.
1076 + * When the capability cannot be found in the chain but is present,
1077 + * special logic is used to attempt to locate functionality.
1079 + * returns: the offset to the capability, zero if not found.
1081 +static int pciback_find_pcie_flr_caps(struct pci_dev *dev)
1086 + /* First look for the PCIe FLR capabilities using the capabilities list */
1087 + exp_pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1089 + pci_read_config_dword(dev, exp_pos + PCI_EXP_DEVCAP, &cap);
1090 + if (cap & PCI_EXP_DEVCAP_FLR) {
1098 +/* Helper used to location the AF FLR capabilities for a PCI device.
1099 + * When the capability cannot be found in the chain but is present,
1100 + * special logic is used to attempt to locate functionality.
1102 + * returns: the offset to the capability, zero if not found.
1104 +static int pciback_find_pci_flr_caps(struct pci_dev *dev)
1106 + struct pci_dev *gmch;
1109 + u8 cap = 0, reg8 = 0;
1111 + /* First look for the PCI AF capabilities for FLR using the capabilities list. This
1112 + * is only used on the devices on the root/host bus (integrated devices).
1114 + if (dev->bus->number != 0)
1117 + af_pos = pci_find_capability(dev, PCI_CAP_ID_AF);
1119 + pci_read_config_byte(dev, af_pos + PCI_AF_DEVCAP, &cap);
1120 + if (cap & PCI_AF_CAP_FLR) {
1125 + /* Next look for the unchained AF capabilities for FLR using specific
1126 + * logic. Currently only the graphics device on the Intel Q45 etc
1127 + * systems has special logic for locating the hidden FLR caps.
1130 + if (dev->bus->number != 0 || dev->devfn != PCI_DEVFN(2,0) ||
1131 + dev->vendor != PCIBACK_VENDOR_INTEL || (dev->class >> 8) != PCIBACK_CLASS_ID_VGA)
1134 + /* Locate the GMCH (north bridge) and test for specific Intel devices */
1135 + gmch = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
1139 + device_id = gmch->device;
1140 + pci_dev_put(gmch);
1142 + if (device_id != PCI_DEVICE_ID_INTEL_GMCHQ45 &&
1143 + device_id != PCI_DEVICE_ID_INTEL_GMCHG45 &&
1144 + device_id != PCI_DEVICE_ID_INTEL_GMCHG41)
1147 + /* Correct device and platform, assume AF offset */
1148 + af_pos = PCIBACK_IGFX_CAP13_OFFSET;
1149 + pci_read_config_byte(dev, af_pos + PCI_AF_LENFLD, ®8);
1150 + if (reg8 == PCI_AF_LENGTH) {
1151 + pci_read_config_byte(dev, af_pos + PCI_AF_DEVCAP, &cap);
1152 + if (cap & PCI_AF_CAP_FLR) {
1158 + /* Else not found */
1162 +/* Classify the device, specifically determine if it is PCIe/PCI
1163 + * and whether it is a PCIe endpoint, bridge, or other PCI device.
1165 +void pciback_classify_device(struct pci_dev *dev)
1167 + struct pciback_dev_data *dev_data;
1171 + dev_data = pci_get_drvdata(dev);
1172 + dev_data->dev_type = PCIBACK_TYPE_UNKNOWN;
1174 + exp_pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
1176 + if ((dev->class >> 8) != DEV_CLASS_PCI_PCI_BRIDGE) {
1177 + if (exp_pos != 0) {
1178 + dev_data->dev_type = PCIBACK_TYPE_PCIe_ENDPOINT;
1179 + dev_data->exp_flr_offset = pciback_find_pcie_flr_caps(dev);
1181 + dev_data->dev_type = PCIBACK_TYPE_PCI;
1182 + dev_data->af_flr_offset = pciback_find_pci_flr_caps(dev);
1184 + goto classify_done;
1187 + if (exp_pos == 0) {
1188 + dev_data->dev_type = PCIBACK_TYPE_PCI_BRIDGE;
1189 + goto classify_done;
1192 + pci_read_config_word(dev, exp_pos + PCI_EXP_FLAGS, &exp_caps);
1193 + dev_data->dev_type = (((exp_caps & PCI_EXP_FLAGS_TYPE) >> 4) == PCI_EXP_TYPE_PCI_BRIDGE) ? PCIBACK_TYPE_PCI_BRIDGE : PCIBACK_TYPE_PCIe_BRIDGE;
1200 extern wait_queue_head_t aer_wait_queue;
1201 extern struct workqueue_struct *pciback_wq;
1203 @@ -132,3 +719,51 @@
1208 +/* Helper routine used to parse command line parameters passed to the
1209 + * pciback module from the boot loader. These params all have the form
1210 + * of a list of one or more devices, e.g.:
1211 + * (XXXX:XX:XX.X)(XXXX:XX:XX.X)
1212 + * Which is: (domain/segment:bus:dev.func)
1214 +int pciback_parse_device_params(const char *device_args, int type,
1215 + int (*add_func) (int domain, int bus, int slot, int func, int type))
1219 + int domain, bus, slot, func;
1222 + if (device_args && *device_args) {
1226 + err = sscanf(device_args + pos,
1227 + " (%x:%x:%x.%x) %n",
1228 + &domain, &bus, &slot, &func, &parsed);
1231 + err = sscanf(device_args + pos,
1233 + &bus, &slot, &func, &parsed);
1238 + err = add_func(domain, bus, slot, func, type);
1242 + /* if parsed<=0, we've reached the end of the string */
1244 + } while (parsed > 0 && device_args[pos]);
1251 + printk(KERN_ERR "pciback: Error parsing device parameters \"%s\" at \"%s\"\n",
1252 + device_args, device_args + pos);
1255 diff --git a/drivers/xen/pciback/slot.c b/drivers/xen/pciback/slot.c
1256 --- a/drivers/xen/pciback/slot.c
1257 +++ b/drivers/xen/pciback/slot.c
1259 spin_unlock_irqrestore(&slot_dev->lock, flags);
1262 - pcistub_put_pci_dev(found_dev);
1263 + pcistub_put_pci_dev(found_dev, 0);
1266 int pciback_init_devices(struct pciback_device *pdev)
1268 for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
1269 dev = slot_dev->slots[bus][slot];
1271 - pcistub_put_pci_dev(dev);
1272 + pcistub_put_pci_dev(dev, 0);
1276 diff --git a/drivers/xen/pciback/vpci.c b/drivers/xen/pciback/vpci.c
1277 --- a/drivers/xen/pciback/vpci.c
1278 +++ b/drivers/xen/pciback/vpci.c
1280 spin_unlock_irqrestore(&vpci_dev->lock, flags);
1283 - pcistub_put_pci_dev(found_dev);
1284 + pcistub_put_pci_dev(found_dev, 0);
1287 int pciback_init_devices(struct pciback_device *pdev)
1289 list_for_each_entry_safe(e, tmp, &vpci_dev->dev_list[slot],
1292 - pcistub_put_pci_dev(e->dev);
1293 + pcistub_put_pci_dev(e->dev, 0);
1297 diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
1298 --- a/include/linux/pci_ids.h
1299 +++ b/include/linux/pci_ids.h
1300 @@ -2501,6 +2501,14 @@
1301 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
1302 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
1304 +#define PCI_DEVICE_ID_INTEL_GMCHQ45 0x2e10
1305 +#define PCI_DEVICE_ID_INTEL_GMCHG45 0x2e20
1306 +#define PCI_DEVICE_ID_INTEL_MCHP45 0x2e20
1307 +#define PCI_DEVICE_ID_INTEL_GMCHG41 0x2e30
1308 +#define PCI_DEVICE_ID_INTEL_GMCHGM45 0x2a40
1310 +#define PCI_DEVICE_ID_INTEL_GMCHG41 0x2e30
1312 #define PCI_VENDOR_ID_SCALEMP 0x8686
1313 #define PCI_DEVICE_ID_SCALEMP_VSMP_CTL 0x1010
1315 diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
1316 --- a/include/linux/pci_regs.h
1317 +++ b/include/linux/pci_regs.h
1319 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
1320 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
1321 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
1322 +#define PCI_CAP_ID_AF 0x13 /* Advanced Features Capability */
1323 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
1324 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
1325 #define PCI_CAP_SIZEOF 4
1326 @@ -239,6 +240,11 @@
1327 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
1328 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
1329 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
1330 +#define PCI_PM_CTRL_DATA_DSTATE_MASK 0x3 /* D0 - D3 */
1331 +#define PCI_PM_CTRL_D0 0x0
1332 +#define PCI_PM_CTRL_D1 0x1
1333 +#define PCI_PM_CTRL_D2 0x2
1334 +#define PCI_PM_CTRL_D3HOT 0x3
1335 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
1336 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
1337 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
1338 @@ -558,6 +564,17 @@
1339 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
1340 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
1342 +/* Advanced Features Capability */
1343 +#define PCI_AF_LENFLD 0x02 /* Device length offset */
1344 +#define PCI_AF_LENGTH 0x06
1345 +#define PCI_AF_DEVCAP 0x03 /* Device capabilities offset */
1346 +#define PCI_AF_CAP_TP 0x01
1347 +#define PCI_AF_CAP_FLR 0x02
1348 +#define PCI_AF_CTRL 0x04 /* Device CTRL offset */
1349 +#define PCI_AF_CTRL_FLR 0x01
1350 +#define PCI_AF_STA 0x05 /* Device STATUS offset */
1351 +#define PCI_AF_STA_TP 0x01
1353 /* Single Root I/O Virtualization */
1354 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
1355 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */