Coverage Report

Created: 2017-10-25 09:10

/root/src/xen/xen/arch/x86/genapic/delivery.c
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#include <xen/irq.h>
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#include <xen/sched.h>
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#include <asm/current.h>
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#include <asm/smp.h>
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#include <asm/hardirq.h>
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#include <mach_apic.h>
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const cpumask_t *target_cpus_all(void)
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{
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  return &cpu_online_map;
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}
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/*
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 * LOGICAL FLAT DELIVERY MODE (multicast via bitmask to <= 8 logical APIC IDs).
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 */
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void init_apic_ldr_flat(void)
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{
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  unsigned long val;
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  apic_write(APIC_DFR, APIC_DFR_FLAT);
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  val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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  val |= SET_xAPIC_LOGICAL_ID(1UL << smp_processor_id());
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  apic_write(APIC_LDR, val);
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}
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void __init clustered_apic_check_flat(void)
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{
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  printk("Enabling APIC mode:  Flat.  Using %d I/O APICs\n", nr_ioapics);
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}
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const cpumask_t *vector_allocation_cpumask_flat(int cpu)
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{
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  return &cpu_online_map;
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} 
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unsigned int cpu_mask_to_apicid_flat(const cpumask_t *cpumask)
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{
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  return cpumask_bits(cpumask)[0]&0xFF;
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}
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/*
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 * PHYSICAL DELIVERY MODE (unicast to physical APIC IDs).
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 */
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void init_apic_ldr_phys(void)
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{
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  unsigned long val;
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  apic_write(APIC_DFR, APIC_DFR_FLAT);
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  /* A dummy logical ID should be fine. We only deliver in phys mode. */
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  val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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  apic_write(APIC_LDR, val);
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}
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void __init clustered_apic_check_phys(void)
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{
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  printk("Enabling APIC mode:  Phys.  Using %d I/O APICs\n", nr_ioapics);
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1
}
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const cpumask_t *vector_allocation_cpumask_phys(int cpu)
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{
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  return cpumask_of(cpu);
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}
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unsigned int cpu_mask_to_apicid_phys(const cpumask_t *cpumask)
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{
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  /* As we are using single CPU as destination, pick only one CPU here */
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  return cpu_physical_id(cpumask_any(cpumask));
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}