/root/src/xen/xen/arch/x86/irq.c
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1 | | /****************************************************************************** |
2 | | * arch/x86/irq.c |
3 | | * |
4 | | * Portions of this file are: |
5 | | * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar |
6 | | */ |
7 | | |
8 | | #include <xen/init.h> |
9 | | #include <xen/delay.h> |
10 | | #include <xen/errno.h> |
11 | | #include <xen/event.h> |
12 | | #include <xen/irq.h> |
13 | | #include <xen/perfc.h> |
14 | | #include <xen/sched.h> |
15 | | #include <xen/keyhandler.h> |
16 | | #include <xen/compat.h> |
17 | | #include <xen/iocap.h> |
18 | | #include <xen/iommu.h> |
19 | | #include <xen/symbols.h> |
20 | | #include <xen/trace.h> |
21 | | #include <xen/softirq.h> |
22 | | #include <xsm/xsm.h> |
23 | | #include <asm/msi.h> |
24 | | #include <asm/current.h> |
25 | | #include <asm/flushtlb.h> |
26 | | #include <asm/mach-generic/mach_apic.h> |
27 | | #include <public/physdev.h> |
28 | | |
29 | | static int parse_irq_vector_map_param(const char *s); |
30 | | |
31 | | /* opt_noirqbalance: If true, software IRQ balancing/affinity is disabled. */ |
32 | | bool __read_mostly opt_noirqbalance; |
33 | | boolean_param("noirqbalance", opt_noirqbalance); |
34 | | |
35 | | unsigned int __read_mostly nr_irqs_gsi = 16; |
36 | | unsigned int __read_mostly nr_irqs; |
37 | | integer_param("nr_irqs", nr_irqs); |
38 | | |
39 | | /* This default may be changed by the AMD IOMMU code */ |
40 | | int __read_mostly opt_irq_vector_map = OPT_IRQ_VECTOR_MAP_DEFAULT; |
41 | | custom_param("irq_vector_map", parse_irq_vector_map_param); |
42 | | |
43 | | vmask_t global_used_vector_map; |
44 | | |
45 | | struct irq_desc __read_mostly *irq_desc = NULL; |
46 | | |
47 | | static DECLARE_BITMAP(used_vectors, NR_VECTORS); |
48 | | |
49 | | static DEFINE_SPINLOCK(vector_lock); |
50 | | |
51 | | DEFINE_PER_CPU(vector_irq_t, vector_irq); |
52 | | |
53 | | DEFINE_PER_CPU(struct cpu_user_regs *, __irq_regs); |
54 | | |
55 | | static LIST_HEAD(irq_ratelimit_list); |
56 | | static DEFINE_SPINLOCK(irq_ratelimit_lock); |
57 | | static struct timer irq_ratelimit_timer; |
58 | | |
59 | | /* irq_ratelimit: the max irq rate allowed in every 10ms, set 0 to disable */ |
60 | | static unsigned int __read_mostly irq_ratelimit_threshold = 10000; |
61 | | integer_param("irq_ratelimit", irq_ratelimit_threshold); |
62 | | |
63 | | static int __init parse_irq_vector_map_param(const char *s) |
64 | 0 | { |
65 | 0 | const char *ss; |
66 | 0 | int rc = 0; |
67 | 0 |
|
68 | 0 | do { |
69 | 0 | ss = strchr(s, ','); |
70 | 0 | if ( !ss ) |
71 | 0 | ss = strchr(s, '\0'); |
72 | 0 |
|
73 | 0 | if ( !strncmp(s, "none", ss - s)) |
74 | 0 | opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_NONE; |
75 | 0 | else if ( !strncmp(s, "global", ss - s)) |
76 | 0 | opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_GLOBAL; |
77 | 0 | else if ( !strncmp(s, "per-device", ss - s)) |
78 | 0 | opt_irq_vector_map=OPT_IRQ_VECTOR_MAP_PERDEV; |
79 | 0 | else |
80 | 0 | rc = -EINVAL; |
81 | 0 |
|
82 | 0 | s = ss + 1; |
83 | 0 | } while ( *ss ); |
84 | 0 |
|
85 | 0 | return rc; |
86 | 0 | } |
87 | | |
88 | | /* Must be called when irq disabled */ |
89 | | void lock_vector_lock(void) |
90 | 11 | { |
91 | 11 | /* Used to the online set of cpus does not change |
92 | 11 | * during assign_irq_vector. |
93 | 11 | */ |
94 | 11 | spin_lock(&vector_lock); |
95 | 11 | } |
96 | | |
97 | | void unlock_vector_lock(void) |
98 | 11 | { |
99 | 11 | spin_unlock(&vector_lock); |
100 | 11 | } |
101 | | |
102 | | static void trace_irq_mask(u32 event, int irq, int vector, cpumask_t *mask) |
103 | 62 | { |
104 | 62 | struct { |
105 | 62 | unsigned int irq:16, vec:16; |
106 | 62 | unsigned int mask[6]; |
107 | 62 | } d; |
108 | 62 | d.irq = irq; |
109 | 62 | d.vec = vector; |
110 | 62 | memset(d.mask, 0, sizeof(d.mask)); |
111 | 62 | memcpy(d.mask, mask, min(sizeof(d.mask), sizeof(cpumask_t))); |
112 | 62 | trace_var(event, 1, sizeof(d), &d); |
113 | 62 | } |
114 | | |
115 | | static int __init __bind_irq_vector(int irq, int vector, const cpumask_t *cpu_mask) |
116 | 1 | { |
117 | 1 | cpumask_t online_mask; |
118 | 1 | int cpu; |
119 | 1 | struct irq_desc *desc = irq_to_desc(irq); |
120 | 1 | |
121 | 1 | BUG_ON((unsigned)irq >= nr_irqs); |
122 | 1 | BUG_ON((unsigned)vector >= NR_VECTORS); |
123 | 1 | |
124 | 1 | cpumask_and(&online_mask, cpu_mask, &cpu_online_map); |
125 | 1 | if (cpumask_empty(&online_mask)) |
126 | 0 | return -EINVAL; |
127 | 1 | if ( (desc->arch.vector == vector) && |
128 | 0 | cpumask_equal(desc->arch.cpu_mask, &online_mask) ) |
129 | 0 | return 0; |
130 | 1 | if ( desc->arch.vector != IRQ_VECTOR_UNASSIGNED ) |
131 | 0 | return -EBUSY; |
132 | 1 | trace_irq_mask(TRC_HW_IRQ_BIND_VECTOR, irq, vector, &online_mask); |
133 | 1 | for_each_cpu(cpu, &online_mask) |
134 | 1 | per_cpu(vector_irq, cpu)[vector] = irq; |
135 | 1 | desc->arch.vector = vector; |
136 | 1 | cpumask_copy(desc->arch.cpu_mask, &online_mask); |
137 | 1 | if ( desc->arch.used_vectors ) |
138 | 0 | { |
139 | 0 | ASSERT(!test_bit(vector, desc->arch.used_vectors)); |
140 | 0 | set_bit(vector, desc->arch.used_vectors); |
141 | 0 | } |
142 | 1 | desc->arch.used = IRQ_USED; |
143 | 1 | return 0; |
144 | 1 | } |
145 | | |
146 | | int __init bind_irq_vector(int irq, int vector, const cpumask_t *cpu_mask) |
147 | 1 | { |
148 | 1 | unsigned long flags; |
149 | 1 | int ret; |
150 | 1 | |
151 | 1 | spin_lock_irqsave(&vector_lock, flags); |
152 | 1 | ret = __bind_irq_vector(irq, vector, cpu_mask); |
153 | 1 | spin_unlock_irqrestore(&vector_lock, flags); |
154 | 1 | return ret; |
155 | 1 | } |
156 | | |
157 | | /* |
158 | | * Dynamic irq allocate and deallocation for MSI |
159 | | */ |
160 | | int create_irq(nodeid_t node) |
161 | 43 | { |
162 | 43 | int irq, ret; |
163 | 43 | struct irq_desc *desc; |
164 | 43 | |
165 | 946 | for (irq = nr_irqs_gsi; irq < nr_irqs; irq++) |
166 | 946 | { |
167 | 946 | desc = irq_to_desc(irq); |
168 | 946 | if (cmpxchg(&desc->arch.used, IRQ_UNUSED, IRQ_RESERVED) == IRQ_UNUSED) |
169 | 43 | break; |
170 | 946 | } |
171 | 43 | |
172 | 43 | if (irq >= nr_irqs) |
173 | 0 | return -ENOSPC; |
174 | 43 | |
175 | 43 | ret = init_one_irq_desc(desc); |
176 | 43 | if (!ret) |
177 | 43 | { |
178 | 43 | cpumask_t *mask = NULL; |
179 | 43 | |
180 | 43 | if ( node != NUMA_NO_NODE ) |
181 | 0 | { |
182 | 0 | mask = &node_to_cpumask(node); |
183 | 0 | if (cpumask_empty(mask)) |
184 | 0 | mask = NULL; |
185 | 0 | } |
186 | 43 | ret = assign_irq_vector(irq, mask); |
187 | 43 | } |
188 | 43 | if (ret < 0) |
189 | 0 | { |
190 | 0 | desc->arch.used = IRQ_UNUSED; |
191 | 0 | irq = ret; |
192 | 0 | } |
193 | 43 | else if ( hardware_domain ) |
194 | 42 | { |
195 | 42 | ret = irq_permit_access(hardware_domain, irq); |
196 | 42 | if ( ret ) |
197 | 0 | printk(XENLOG_G_ERR |
198 | 0 | "Could not grant Dom0 access to IRQ%d (error %d)\n", |
199 | 0 | irq, ret); |
200 | 42 | } |
201 | 43 | |
202 | 43 | return irq; |
203 | 43 | } |
204 | | |
205 | | void destroy_irq(unsigned int irq) |
206 | 0 | { |
207 | 0 | struct irq_desc *desc = irq_to_desc(irq); |
208 | 0 | unsigned long flags; |
209 | 0 | struct irqaction *action; |
210 | 0 |
|
211 | 0 | BUG_ON(!MSI_IRQ(irq)); |
212 | 0 |
|
213 | 0 | if ( hardware_domain ) |
214 | 0 | { |
215 | 0 | int err = irq_deny_access(hardware_domain, irq); |
216 | 0 |
|
217 | 0 | if ( err ) |
218 | 0 | printk(XENLOG_G_ERR |
219 | 0 | "Could not revoke Dom0 access to IRQ%u (error %d)\n", |
220 | 0 | irq, err); |
221 | 0 | } |
222 | 0 |
|
223 | 0 | spin_lock_irqsave(&desc->lock, flags); |
224 | 0 | desc->status &= ~IRQ_GUEST; |
225 | 0 | desc->handler->shutdown(desc); |
226 | 0 | desc->status |= IRQ_DISABLED; |
227 | 0 | action = desc->action; |
228 | 0 | desc->action = NULL; |
229 | 0 | desc->msi_desc = NULL; |
230 | 0 | cpumask_setall(desc->affinity); |
231 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
232 | 0 |
|
233 | 0 | /* Wait to make sure it's not being used on another CPU */ |
234 | 0 | do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS ); |
235 | 0 |
|
236 | 0 | spin_lock_irqsave(&desc->lock, flags); |
237 | 0 | desc->handler = &no_irq_type; |
238 | 0 | clear_irq_vector(irq); |
239 | 0 | desc->arch.used_vectors = NULL; |
240 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
241 | 0 |
|
242 | 0 | xfree(action); |
243 | 0 | } |
244 | | |
245 | | static void __clear_irq_vector(int irq) |
246 | 1 | { |
247 | 1 | int cpu, vector, old_vector; |
248 | 1 | cpumask_t tmp_mask; |
249 | 1 | struct irq_desc *desc = irq_to_desc(irq); |
250 | 1 | |
251 | 1 | BUG_ON(!desc->arch.vector); |
252 | 1 | |
253 | 1 | /* Always clear desc->arch.vector */ |
254 | 1 | vector = desc->arch.vector; |
255 | 1 | cpumask_and(&tmp_mask, desc->arch.cpu_mask, &cpu_online_map); |
256 | 1 | |
257 | 1 | for_each_cpu(cpu, &tmp_mask) { |
258 | 1 | ASSERT( per_cpu(vector_irq, cpu)[vector] == irq ); |
259 | 1 | per_cpu(vector_irq, cpu)[vector] = ~irq; |
260 | 1 | } |
261 | 1 | |
262 | 1 | desc->arch.vector = IRQ_VECTOR_UNASSIGNED; |
263 | 1 | cpumask_clear(desc->arch.cpu_mask); |
264 | 1 | |
265 | 1 | if ( desc->arch.used_vectors ) |
266 | 0 | { |
267 | 0 | ASSERT(test_bit(vector, desc->arch.used_vectors)); |
268 | 0 | clear_bit(vector, desc->arch.used_vectors); |
269 | 0 | } |
270 | 1 | |
271 | 1 | desc->arch.used = IRQ_UNUSED; |
272 | 1 | |
273 | 1 | trace_irq_mask(TRC_HW_IRQ_CLEAR_VECTOR, irq, vector, &tmp_mask); |
274 | 1 | |
275 | 1 | if ( likely(!desc->arch.move_in_progress) ) |
276 | 1 | return; |
277 | 1 | |
278 | 1 | /* If we were in motion, also clear desc->arch.old_vector */ |
279 | 0 | old_vector = desc->arch.old_vector; |
280 | 0 | cpumask_and(&tmp_mask, desc->arch.old_cpu_mask, &cpu_online_map); |
281 | 0 |
|
282 | 0 | for_each_cpu(cpu, &tmp_mask) { |
283 | 0 | ASSERT( per_cpu(vector_irq, cpu)[old_vector] == irq ); |
284 | 0 | TRACE_3D(TRC_HW_IRQ_MOVE_FINISH, irq, old_vector, cpu); |
285 | 0 | per_cpu(vector_irq, cpu)[old_vector] = ~irq; |
286 | 0 | } |
287 | 0 |
|
288 | 0 | desc->arch.old_vector = IRQ_VECTOR_UNASSIGNED; |
289 | 0 | cpumask_clear(desc->arch.old_cpu_mask); |
290 | 0 |
|
291 | 0 | if ( desc->arch.used_vectors ) |
292 | 0 | { |
293 | 0 | ASSERT(test_bit(old_vector, desc->arch.used_vectors)); |
294 | 0 | clear_bit(old_vector, desc->arch.used_vectors); |
295 | 0 | } |
296 | 0 |
|
297 | 0 | desc->arch.move_in_progress = 0; |
298 | 0 | } |
299 | | |
300 | | void clear_irq_vector(int irq) |
301 | 1 | { |
302 | 1 | unsigned long flags; |
303 | 1 | |
304 | 1 | spin_lock_irqsave(&vector_lock, flags); |
305 | 1 | __clear_irq_vector(irq); |
306 | 1 | spin_unlock_irqrestore(&vector_lock, flags); |
307 | 1 | } |
308 | | |
309 | | int irq_to_vector(int irq) |
310 | 684 | { |
311 | 684 | int vector = -1; |
312 | 684 | |
313 | 684 | BUG_ON(irq >= nr_irqs || irq < 0); |
314 | 684 | |
315 | 684 | if (IO_APIC_IRQ(irq)) |
316 | 586 | { |
317 | 586 | vector = irq_to_desc(irq)->arch.vector; |
318 | 586 | if (vector >= FIRST_LEGACY_VECTOR && vector <= LAST_LEGACY_VECTOR) |
319 | 13 | vector = 0; |
320 | 586 | } |
321 | 98 | else if (MSI_IRQ(irq)) |
322 | 98 | vector = irq_to_desc(irq)->arch.vector; |
323 | 98 | else |
324 | 0 | vector = LEGACY_VECTOR(irq); |
325 | 684 | |
326 | 684 | return vector; |
327 | 684 | } |
328 | | |
329 | | int arch_init_one_irq_desc(struct irq_desc *desc) |
330 | 91 | { |
331 | 91 | if ( !zalloc_cpumask_var(&desc->arch.cpu_mask) ) |
332 | 0 | return -ENOMEM; |
333 | 91 | |
334 | 91 | if ( !alloc_cpumask_var(&desc->arch.old_cpu_mask) ) |
335 | 0 | { |
336 | 0 | free_cpumask_var(desc->arch.cpu_mask); |
337 | 0 | return -ENOMEM; |
338 | 0 | } |
339 | 91 | |
340 | 91 | if ( !alloc_cpumask_var(&desc->arch.pending_mask) ) |
341 | 0 | { |
342 | 0 | free_cpumask_var(desc->arch.old_cpu_mask); |
343 | 0 | free_cpumask_var(desc->arch.cpu_mask); |
344 | 0 | return -ENOMEM; |
345 | 0 | } |
346 | 91 | |
347 | 91 | desc->arch.vector = IRQ_VECTOR_UNASSIGNED; |
348 | 91 | desc->arch.old_vector = IRQ_VECTOR_UNASSIGNED; |
349 | 91 | |
350 | 91 | return 0; |
351 | 91 | } |
352 | | |
353 | | int __init init_irq_data(void) |
354 | 1 | { |
355 | 1 | struct irq_desc *desc; |
356 | 1 | int irq, vector; |
357 | 1 | |
358 | 257 | for ( vector = 0; vector < NR_VECTORS; ++vector ) |
359 | 256 | this_cpu(vector_irq)[vector] = INT_MIN; |
360 | 1 | |
361 | 1 | irq_desc = xzalloc_array(struct irq_desc, nr_irqs); |
362 | 1 | |
363 | 1 | if ( !irq_desc ) |
364 | 0 | return -ENOMEM; |
365 | 1 | |
366 | 49 | for ( irq = 0; irq < nr_irqs_gsi; irq++ ) |
367 | 48 | { |
368 | 48 | desc = irq_to_desc(irq); |
369 | 48 | desc->irq = irq; |
370 | 48 | init_one_irq_desc(desc); |
371 | 48 | } |
372 | 2.27k | for ( ; irq < nr_irqs; irq++ ) |
373 | 2.27k | irq_to_desc(irq)->irq = irq; |
374 | 1 | |
375 | 1 | #ifdef CONFIG_PV |
376 | 1 | /* Never allocate the hypercall vector or Linux/BSD fast-trap vector. */ |
377 | 1 | set_bit(LEGACY_SYSCALL_VECTOR, used_vectors); |
378 | 1 | set_bit(HYPERCALL_VECTOR, used_vectors); |
379 | 1 | #endif |
380 | 1 | |
381 | 1 | /* IRQ_MOVE_CLEANUP_VECTOR used for clean up vectors */ |
382 | 1 | set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors); |
383 | 1 | |
384 | 1 | return 0; |
385 | 1 | } |
386 | | |
387 | | static void __do_IRQ_guest(int vector); |
388 | | |
389 | | static void ack_none(struct irq_desc *desc) |
390 | 0 | { |
391 | 0 | ack_bad_irq(desc->irq); |
392 | 0 | } |
393 | | |
394 | | hw_irq_controller no_irq_type = { |
395 | | "none", |
396 | | irq_startup_none, |
397 | | irq_shutdown_none, |
398 | | irq_enable_none, |
399 | | irq_disable_none, |
400 | | ack_none, |
401 | | }; |
402 | | |
403 | | static vmask_t *irq_get_used_vector_mask(int irq) |
404 | 59 | { |
405 | 59 | vmask_t *ret = NULL; |
406 | 59 | |
407 | 59 | if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_GLOBAL ) |
408 | 0 | { |
409 | 0 | struct irq_desc *desc = irq_to_desc(irq); |
410 | 0 |
|
411 | 0 | ret = &global_used_vector_map; |
412 | 0 |
|
413 | 0 | if ( desc->arch.used_vectors ) |
414 | 0 | printk(XENLOG_INFO "Unassigned IRQ %d already has used_vectors\n", |
415 | 0 | irq); |
416 | 0 | else |
417 | 0 | { |
418 | 0 | int vector; |
419 | 0 | |
420 | 0 | vector = irq_to_vector(irq); |
421 | 0 | if ( vector > 0 ) |
422 | 0 | { |
423 | 0 | printk(XENLOG_INFO "IRQ %d already assigned vector %d\n", |
424 | 0 | irq, vector); |
425 | 0 | |
426 | 0 | ASSERT(!test_bit(vector, ret)); |
427 | 0 |
|
428 | 0 | set_bit(vector, ret); |
429 | 0 | } |
430 | 0 | } |
431 | 0 | } |
432 | 59 | else if ( IO_APIC_IRQ(irq) && |
433 | 16 | opt_irq_vector_map != OPT_IRQ_VECTOR_MAP_NONE ) |
434 | 16 | { |
435 | 16 | ret = io_apic_get_used_vector_map(irq); |
436 | 16 | } |
437 | 59 | |
438 | 59 | return ret; |
439 | 59 | } |
440 | | |
441 | | static int __assign_irq_vector( |
442 | | int irq, struct irq_desc *desc, const cpumask_t *mask) |
443 | 129 | { |
444 | 129 | /* |
445 | 129 | * NOTE! The local APIC isn't very good at handling |
446 | 129 | * multiple interrupts at the same interrupt level. |
447 | 129 | * As the interrupt level is determined by taking the |
448 | 129 | * vector number and shifting that right by 4, we |
449 | 129 | * want to spread these out a bit so that they don't |
450 | 129 | * all fall in the same interrupt level. |
451 | 129 | * |
452 | 129 | * Also, we've got to be careful not to trash gate |
453 | 129 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
454 | 129 | */ |
455 | 129 | static int current_vector = FIRST_DYNAMIC_VECTOR, current_offset = 0; |
456 | 129 | int cpu, err, old_vector; |
457 | 129 | cpumask_t tmp_mask; |
458 | 129 | vmask_t *irq_used_vectors = NULL; |
459 | 129 | |
460 | 129 | old_vector = irq_to_vector(irq); |
461 | 129 | if (old_vector > 0) { |
462 | 70 | cpumask_and(&tmp_mask, mask, &cpu_online_map); |
463 | 70 | if (cpumask_intersects(&tmp_mask, desc->arch.cpu_mask)) { |
464 | 69 | desc->arch.vector = old_vector; |
465 | 69 | return 0; |
466 | 69 | } |
467 | 70 | } |
468 | 129 | |
469 | 60 | if ( desc->arch.move_in_progress || desc->arch.move_cleanup_count ) |
470 | 0 | return -EAGAIN; |
471 | 60 | |
472 | 60 | err = -ENOSPC; |
473 | 60 | |
474 | 60 | /* This is the only place normal IRQs are ever marked |
475 | 60 | * as "in use". If they're not in use yet, check to see |
476 | 60 | * if we need to assign a global vector mask. */ |
477 | 60 | if ( desc->arch.used == IRQ_USED ) |
478 | 1 | { |
479 | 1 | irq_used_vectors = desc->arch.used_vectors; |
480 | 1 | } |
481 | 60 | else |
482 | 59 | irq_used_vectors = irq_get_used_vector_mask(irq); |
483 | 60 | |
484 | 60 | for_each_cpu(cpu, mask) { |
485 | 60 | int new_cpu; |
486 | 60 | int vector, offset; |
487 | 60 | |
488 | 60 | /* Only try and allocate irqs on cpus that are present. */ |
489 | 60 | if (!cpu_online(cpu)) |
490 | 0 | continue; |
491 | 60 | |
492 | 60 | cpumask_and(&tmp_mask, vector_allocation_cpumask(cpu), |
493 | 60 | &cpu_online_map); |
494 | 60 | |
495 | 60 | vector = current_vector; |
496 | 60 | offset = current_offset; |
497 | 62 | next: |
498 | 62 | vector += 8; |
499 | 62 | if (vector > LAST_DYNAMIC_VECTOR) { |
500 | 2 | /* If out of vectors on large boxen, must share them. */ |
501 | 2 | offset = (offset + 1) % 8; |
502 | 2 | vector = FIRST_DYNAMIC_VECTOR + offset; |
503 | 2 | } |
504 | 62 | if (unlikely(current_vector == vector)) |
505 | 0 | continue; |
506 | 62 | |
507 | 62 | if (test_bit(vector, used_vectors)) |
508 | 2 | goto next; |
509 | 62 | |
510 | 60 | if (irq_used_vectors |
511 | 17 | && test_bit(vector, irq_used_vectors) ) |
512 | 0 | goto next; |
513 | 60 | |
514 | 60 | for_each_cpu(new_cpu, &tmp_mask) |
515 | 566 | if (per_cpu(vector_irq, new_cpu)[vector] >= 0) |
516 | 0 | goto next; |
517 | 60 | /* Found one! */ |
518 | 60 | current_vector = vector; |
519 | 60 | current_offset = offset; |
520 | 60 | if (old_vector > 0) { |
521 | 1 | desc->arch.move_in_progress = 1; |
522 | 1 | cpumask_copy(desc->arch.old_cpu_mask, desc->arch.cpu_mask); |
523 | 1 | desc->arch.old_vector = desc->arch.vector; |
524 | 1 | } |
525 | 60 | trace_irq_mask(TRC_HW_IRQ_ASSIGN_VECTOR, irq, vector, &tmp_mask); |
526 | 60 | for_each_cpu(new_cpu, &tmp_mask) |
527 | 566 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
528 | 60 | desc->arch.vector = vector; |
529 | 60 | cpumask_copy(desc->arch.cpu_mask, &tmp_mask); |
530 | 60 | |
531 | 60 | desc->arch.used = IRQ_USED; |
532 | 60 | ASSERT((desc->arch.used_vectors == NULL) |
533 | 60 | || (desc->arch.used_vectors == irq_used_vectors)); |
534 | 60 | desc->arch.used_vectors = irq_used_vectors; |
535 | 60 | |
536 | 60 | if ( desc->arch.used_vectors ) |
537 | 17 | { |
538 | 17 | ASSERT(!test_bit(vector, desc->arch.used_vectors)); |
539 | 17 | |
540 | 17 | set_bit(vector, desc->arch.used_vectors); |
541 | 17 | } |
542 | 60 | |
543 | 60 | err = 0; |
544 | 60 | break; |
545 | 60 | } |
546 | 60 | return err; |
547 | 60 | } |
548 | | |
549 | | int assign_irq_vector(int irq, const cpumask_t *mask) |
550 | 64 | { |
551 | 64 | int ret; |
552 | 64 | unsigned long flags; |
553 | 64 | struct irq_desc *desc = irq_to_desc(irq); |
554 | 64 | |
555 | 64 | BUG_ON(irq >= nr_irqs || irq <0); |
556 | 64 | |
557 | 64 | spin_lock_irqsave(&vector_lock, flags); |
558 | 64 | ret = __assign_irq_vector(irq, desc, mask ?: TARGET_CPUS); |
559 | 64 | if (!ret) { |
560 | 64 | ret = desc->arch.vector; |
561 | 64 | cpumask_copy(desc->affinity, desc->arch.cpu_mask); |
562 | 64 | } |
563 | 64 | spin_unlock_irqrestore(&vector_lock, flags); |
564 | 64 | return ret; |
565 | 64 | } |
566 | | |
567 | | /* |
568 | | * Initialize vector_irq on a new cpu. This function must be called |
569 | | * with vector_lock held. |
570 | | */ |
571 | | void setup_vector_irq(unsigned int cpu) |
572 | 11 | { |
573 | 11 | unsigned int irq, vector; |
574 | 11 | |
575 | 11 | /* Clear vector_irq */ |
576 | 2.82k | for ( vector = 0; vector < NR_VECTORS; ++vector ) |
577 | 2.81k | per_cpu(vector_irq, cpu)[vector] = INT_MIN; |
578 | 11 | /* Mark the inuse vectors */ |
579 | 25.5k | for ( irq = 0; irq < nr_irqs; ++irq ) |
580 | 25.5k | { |
581 | 25.5k | struct irq_desc *desc = irq_to_desc(irq); |
582 | 25.5k | |
583 | 25.5k | if ( !irq_desc_initialized(desc) ) |
584 | 24.9k | continue; |
585 | 539 | vector = irq_to_vector(irq); |
586 | 539 | if ( vector >= FIRST_HIPRIORITY_VECTOR && |
587 | 374 | vector <= LAST_HIPRIORITY_VECTOR ) |
588 | 11 | cpumask_set_cpu(cpu, desc->arch.cpu_mask); |
589 | 528 | else if ( !cpumask_test_cpu(cpu, desc->arch.cpu_mask) ) |
590 | 528 | continue; |
591 | 11 | per_cpu(vector_irq, cpu)[vector] = irq; |
592 | 11 | } |
593 | 11 | } |
594 | | |
595 | | void move_masked_irq(struct irq_desc *desc) |
596 | 0 | { |
597 | 0 | cpumask_t *pending_mask = desc->arch.pending_mask; |
598 | 0 |
|
599 | 0 | if (likely(!(desc->status & IRQ_MOVE_PENDING))) |
600 | 0 | return; |
601 | 0 | |
602 | 0 | desc->status &= ~IRQ_MOVE_PENDING; |
603 | 0 |
|
604 | 0 | if (unlikely(cpumask_empty(pending_mask))) |
605 | 0 | return; |
606 | 0 |
|
607 | 0 | if (!desc->handler->set_affinity) |
608 | 0 | return; |
609 | 0 |
|
610 | 0 | /* |
611 | 0 | * If there was a valid mask to work with, please do the disable, |
612 | 0 | * re-program, enable sequence. This is *not* particularly important for |
613 | 0 | * level triggered but in a edge trigger case, we might be setting rte when |
614 | 0 | * an active trigger is comming in. This could cause some ioapics to |
615 | 0 | * mal-function. Being paranoid i guess! |
616 | 0 | * |
617 | 0 | * For correct operation this depends on the caller masking the irqs. |
618 | 0 | */ |
619 | 0 | if ( likely(cpumask_intersects(pending_mask, &cpu_online_map)) ) |
620 | 0 | desc->handler->set_affinity(desc, pending_mask); |
621 | 0 |
|
622 | 0 | cpumask_clear(pending_mask); |
623 | 0 | } |
624 | | |
625 | | void move_native_irq(struct irq_desc *desc) |
626 | 12.9k | { |
627 | 12.9k | if (likely(!(desc->status & IRQ_MOVE_PENDING))) |
628 | 12.9k | return; |
629 | 12.9k | |
630 | 0 | if (unlikely(desc->status & IRQ_DISABLED)) |
631 | 0 | return; |
632 | 0 |
|
633 | 0 | desc->handler->disable(desc); |
634 | 0 | move_masked_irq(desc); |
635 | 0 | desc->handler->enable(desc); |
636 | 0 | } |
637 | | |
638 | | void irq_move_cleanup_interrupt(struct cpu_user_regs *regs) |
639 | 1 | { |
640 | 1 | unsigned vector, me; |
641 | 1 | |
642 | 1 | ack_APIC_irq(); |
643 | 1 | |
644 | 1 | me = smp_processor_id(); |
645 | 1 | for ( vector = FIRST_DYNAMIC_VECTOR; |
646 | 218 | vector <= LAST_HIPRIORITY_VECTOR; vector++) |
647 | 217 | { |
648 | 217 | unsigned int irq; |
649 | 217 | unsigned int irr; |
650 | 217 | struct irq_desc *desc; |
651 | 217 | irq = __get_cpu_var(vector_irq)[vector]; |
652 | 217 | |
653 | 217 | if ((int)irq < 0) |
654 | 155 | continue; |
655 | 217 | |
656 | 62 | if ( vector >= FIRST_LEGACY_VECTOR && vector <= LAST_LEGACY_VECTOR ) |
657 | 0 | continue; |
658 | 62 | |
659 | 62 | desc = irq_to_desc(irq); |
660 | 62 | if (!desc) |
661 | 0 | continue; |
662 | 62 | |
663 | 62 | spin_lock(&desc->lock); |
664 | 62 | if (!desc->arch.move_cleanup_count) |
665 | 61 | goto unlock; |
666 | 62 | |
667 | 1 | if ( vector == desc->arch.vector && |
668 | 0 | cpumask_test_cpu(me, desc->arch.cpu_mask) ) |
669 | 0 | goto unlock; |
670 | 1 | |
671 | 1 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
672 | 1 | /* |
673 | 1 | * Check if the vector that needs to be cleanedup is |
674 | 1 | * registered at the cpu's IRR. If so, then this is not |
675 | 1 | * the best time to clean it up. Lets clean it up in the |
676 | 1 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
677 | 1 | * to myself. |
678 | 1 | */ |
679 | 1 | if (irr & (1 << (vector % 32))) { |
680 | 0 | send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
681 | 0 | TRACE_3D(TRC_HW_IRQ_MOVE_CLEANUP_DELAY, |
682 | 0 | irq, vector, smp_processor_id()); |
683 | 0 | goto unlock; |
684 | 0 | } |
685 | 1 | |
686 | 1 | TRACE_3D(TRC_HW_IRQ_MOVE_CLEANUP, |
687 | 1 | irq, vector, smp_processor_id()); |
688 | 1 | |
689 | 1 | __get_cpu_var(vector_irq)[vector] = ~irq; |
690 | 1 | desc->arch.move_cleanup_count--; |
691 | 1 | |
692 | 1 | if ( desc->arch.move_cleanup_count == 0 ) |
693 | 1 | { |
694 | 1 | desc->arch.old_vector = IRQ_VECTOR_UNASSIGNED; |
695 | 1 | cpumask_clear(desc->arch.old_cpu_mask); |
696 | 1 | |
697 | 1 | if ( desc->arch.used_vectors ) |
698 | 1 | { |
699 | 1 | ASSERT(test_bit(vector, desc->arch.used_vectors)); |
700 | 1 | clear_bit(vector, desc->arch.used_vectors); |
701 | 1 | } |
702 | 1 | } |
703 | 62 | unlock: |
704 | 62 | spin_unlock(&desc->lock); |
705 | 62 | } |
706 | 1 | } |
707 | | |
708 | | static void send_cleanup_vector(struct irq_desc *desc) |
709 | 1 | { |
710 | 1 | cpumask_t cleanup_mask; |
711 | 1 | |
712 | 1 | cpumask_and(&cleanup_mask, desc->arch.old_cpu_mask, &cpu_online_map); |
713 | 1 | desc->arch.move_cleanup_count = cpumask_weight(&cleanup_mask); |
714 | 1 | send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
715 | 1 | |
716 | 1 | desc->arch.move_in_progress = 0; |
717 | 1 | } |
718 | | |
719 | | void irq_complete_move(struct irq_desc *desc) |
720 | 13.2k | { |
721 | 13.2k | unsigned vector, me; |
722 | 13.2k | |
723 | 13.2k | if (likely(!desc->arch.move_in_progress)) |
724 | 13.2k | return; |
725 | 13.2k | |
726 | 1 | vector = (u8)get_irq_regs()->entry_vector; |
727 | 1 | me = smp_processor_id(); |
728 | 1 | |
729 | 1 | if ( vector == desc->arch.vector && |
730 | 1 | cpumask_test_cpu(me, desc->arch.cpu_mask) ) |
731 | 1 | send_cleanup_vector(desc); |
732 | 1 | } |
733 | | |
734 | | unsigned int set_desc_affinity(struct irq_desc *desc, const cpumask_t *mask) |
735 | 65 | { |
736 | 65 | unsigned int irq; |
737 | 65 | int ret; |
738 | 65 | unsigned long flags; |
739 | 65 | cpumask_t dest_mask; |
740 | 65 | |
741 | 65 | if (!cpumask_intersects(mask, &cpu_online_map)) |
742 | 0 | return BAD_APICID; |
743 | 65 | |
744 | 65 | irq = desc->irq; |
745 | 65 | |
746 | 65 | spin_lock_irqsave(&vector_lock, flags); |
747 | 65 | ret = __assign_irq_vector(irq, desc, mask); |
748 | 65 | spin_unlock_irqrestore(&vector_lock, flags); |
749 | 65 | |
750 | 65 | if (ret < 0) |
751 | 0 | return BAD_APICID; |
752 | 65 | |
753 | 65 | cpumask_copy(desc->affinity, mask); |
754 | 65 | cpumask_and(&dest_mask, mask, desc->arch.cpu_mask); |
755 | 65 | |
756 | 65 | return cpu_mask_to_apicid(&dest_mask); |
757 | 65 | } |
758 | | |
759 | | /* For re-setting irq interrupt affinity for specific irq */ |
760 | | void irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask) |
761 | 0 | { |
762 | 0 | if (!desc->handler->set_affinity) |
763 | 0 | return; |
764 | 0 | |
765 | 0 | ASSERT(spin_is_locked(&desc->lock)); |
766 | 0 | desc->status &= ~IRQ_MOVE_PENDING; |
767 | 0 | wmb(); |
768 | 0 | cpumask_copy(desc->arch.pending_mask, mask); |
769 | 0 | wmb(); |
770 | 0 | desc->status |= IRQ_MOVE_PENDING; |
771 | 0 | } |
772 | | |
773 | | void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) |
774 | 0 | { |
775 | 0 | unsigned long flags; |
776 | 0 | struct irq_desc *desc = domain_spin_lock_irq_desc(d, pirq, &flags); |
777 | 0 |
|
778 | 0 | if ( !desc ) |
779 | 0 | return; |
780 | 0 | irq_set_affinity(desc, mask); |
781 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
782 | 0 | } |
783 | | |
784 | | DEFINE_PER_CPU(unsigned int, irq_count); |
785 | | |
786 | | uint8_t alloc_hipriority_vector(void) |
787 | 4 | { |
788 | 4 | static uint8_t next = FIRST_HIPRIORITY_VECTOR; |
789 | 4 | BUG_ON(next < FIRST_HIPRIORITY_VECTOR); |
790 | 4 | BUG_ON(next > LAST_HIPRIORITY_VECTOR); |
791 | 4 | return next++; |
792 | 4 | } |
793 | | |
794 | | static void (*direct_apic_vector[NR_VECTORS])(struct cpu_user_regs *); |
795 | | void set_direct_apic_vector( |
796 | | uint8_t vector, void (*handler)(struct cpu_user_regs *)) |
797 | 11 | { |
798 | 11 | BUG_ON(direct_apic_vector[vector] != NULL); |
799 | 11 | direct_apic_vector[vector] = handler; |
800 | 11 | } |
801 | | |
802 | | void alloc_direct_apic_vector( |
803 | | uint8_t *vector, void (*handler)(struct cpu_user_regs *)) |
804 | 25 | { |
805 | 25 | static DEFINE_SPINLOCK(lock); |
806 | 25 | |
807 | 25 | spin_lock(&lock); |
808 | 25 | if (*vector == 0) { |
809 | 3 | *vector = alloc_hipriority_vector(); |
810 | 3 | set_direct_apic_vector(*vector, handler); |
811 | 3 | } |
812 | 25 | spin_unlock(&lock); |
813 | 25 | } |
814 | | |
815 | | void do_IRQ(struct cpu_user_regs *regs) |
816 | 2.13M | { |
817 | 2.13M | struct irqaction *action; |
818 | 2.13M | uint32_t tsc_in; |
819 | 2.13M | struct irq_desc *desc; |
820 | 2.13M | unsigned int vector = (u8)regs->entry_vector; |
821 | 2.13M | int irq = __get_cpu_var(vector_irq[vector]); |
822 | 2.13M | struct cpu_user_regs *old_regs = set_irq_regs(regs); |
823 | 2.13M | |
824 | 2.13M | perfc_incr(irqs); |
825 | 2.13M | this_cpu(irq_count)++; |
826 | 2.13M | irq_enter(); |
827 | 2.13M | |
828 | 2.13M | if (irq < 0) { |
829 | 2.02M | if (direct_apic_vector[vector] != NULL) { |
830 | 2.02M | (*direct_apic_vector[vector])(regs); |
831 | 18.4E | } else { |
832 | 18.4E | const char *kind = ", LAPIC"; |
833 | 18.4E | |
834 | 18.4E | if ( apic_isr_read(vector) ) |
835 | 0 | ack_APIC_irq(); |
836 | 18.4E | else |
837 | 18.4E | kind = ""; |
838 | 18.4E | if ( ! ( vector >= FIRST_LEGACY_VECTOR && |
839 | 0 | vector <= LAST_LEGACY_VECTOR && |
840 | 0 | bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR) ) ) |
841 | 0 | { |
842 | 0 | printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n", |
843 | 0 | smp_processor_id(), vector, irq, kind); |
844 | 0 | desc = irq_to_desc(~irq); |
845 | 0 | if ( ~irq < nr_irqs && irq_desc_initialized(desc) ) |
846 | 0 | { |
847 | 0 | spin_lock(&desc->lock); |
848 | 0 | printk("IRQ%d a=%04lx[%04lx,%04lx] v=%02x[%02x] t=%s s=%08x\n", |
849 | 0 | ~irq, *cpumask_bits(desc->affinity), |
850 | 0 | *cpumask_bits(desc->arch.cpu_mask), |
851 | 0 | *cpumask_bits(desc->arch.old_cpu_mask), |
852 | 0 | desc->arch.vector, desc->arch.old_vector, |
853 | 0 | desc->handler->typename, desc->status); |
854 | 0 | spin_unlock(&desc->lock); |
855 | 0 | } |
856 | 0 | } |
857 | 18.4E | TRACE_1D(TRC_HW_IRQ_UNMAPPED_VECTOR, vector); |
858 | 18.4E | } |
859 | 1.98M | goto out_no_unlock; |
860 | 1.98M | } |
861 | 2.13M | |
862 | 144k | desc = irq_to_desc(irq); |
863 | 144k | |
864 | 144k | spin_lock(&desc->lock); |
865 | 144k | desc->handler->ack(desc); |
866 | 144k | |
867 | 144k | if ( likely(desc->status & IRQ_GUEST) ) |
868 | 4.14k | { |
869 | 4.14k | if ( irq_ratelimit_timer.function && /* irq rate limiting enabled? */ |
870 | 4.14k | unlikely(desc->rl_cnt++ >= irq_ratelimit_threshold) ) |
871 | 0 | { |
872 | 0 | s_time_t now = NOW(); |
873 | 0 | if ( now < (desc->rl_quantum_start + MILLISECS(10)) ) |
874 | 0 | { |
875 | 0 | desc->handler->disable(desc); |
876 | 0 | /* |
877 | 0 | * If handler->disable doesn't actually mask the interrupt, a |
878 | 0 | * disabled irq still can fire. This check also avoids possible |
879 | 0 | * deadlocks if ratelimit_timer_fn runs at the same time. |
880 | 0 | */ |
881 | 0 | if ( likely(list_empty(&desc->rl_link)) ) |
882 | 0 | { |
883 | 0 | spin_lock(&irq_ratelimit_lock); |
884 | 0 | if ( list_empty(&irq_ratelimit_list) ) |
885 | 0 | set_timer(&irq_ratelimit_timer, now + MILLISECS(10)); |
886 | 0 | list_add(&desc->rl_link, &irq_ratelimit_list); |
887 | 0 | spin_unlock(&irq_ratelimit_lock); |
888 | 0 | } |
889 | 0 | goto out; |
890 | 0 | } |
891 | 0 | desc->rl_cnt = 0; |
892 | 0 | desc->rl_quantum_start = now; |
893 | 0 | } |
894 | 4.14k | |
895 | 4.14k | tsc_in = tb_init_done ? get_cycles() : 0; |
896 | 4.14k | __do_IRQ_guest(irq); |
897 | 4.14k | TRACE_3D(TRC_HW_IRQ_HANDLED, irq, tsc_in, get_cycles()); |
898 | 4.14k | goto out_no_end; |
899 | 4.14k | } |
900 | 144k | |
901 | 140k | desc->status &= ~IRQ_REPLAY; |
902 | 140k | desc->status |= IRQ_PENDING; |
903 | 140k | |
904 | 140k | /* |
905 | 140k | * Since we set PENDING, if another processor is handling a different |
906 | 140k | * instance of this same irq, the other processor will take care of it. |
907 | 140k | */ |
908 | 140k | if ( desc->status & (IRQ_DISABLED | IRQ_INPROGRESS) ) |
909 | 2 | goto out; |
910 | 140k | |
911 | 140k | desc->status |= IRQ_INPROGRESS; |
912 | 140k | |
913 | 140k | action = desc->action; |
914 | 149k | while ( desc->status & IRQ_PENDING ) |
915 | 9.07k | { |
916 | 9.07k | desc->status &= ~IRQ_PENDING; |
917 | 9.07k | spin_unlock_irq(&desc->lock); |
918 | 9.07k | tsc_in = tb_init_done ? get_cycles() : 0; |
919 | 9.07k | action->handler(irq, action->dev_id, regs); |
920 | 9.07k | TRACE_3D(TRC_HW_IRQ_HANDLED, irq, tsc_in, get_cycles()); |
921 | 9.07k | spin_lock_irq(&desc->lock); |
922 | 9.07k | } |
923 | 140k | |
924 | 140k | desc->status &= ~IRQ_INPROGRESS; |
925 | 140k | |
926 | 9.07k | out: |
927 | 9.07k | if ( desc->handler->end ) |
928 | 9 | desc->handler->end(desc, vector); |
929 | 13.2k | out_no_end: |
930 | 13.2k | spin_unlock(&desc->lock); |
931 | 2.22M | out_no_unlock: |
932 | 2.22M | irq_exit(); |
933 | 2.22M | set_irq_regs(old_regs); |
934 | 2.22M | } |
935 | | |
936 | | static void irq_ratelimit_timer_fn(void *data) |
937 | 0 | { |
938 | 0 | struct irq_desc *desc, *tmp; |
939 | 0 | unsigned long flags; |
940 | 0 |
|
941 | 0 | spin_lock_irqsave(&irq_ratelimit_lock, flags); |
942 | 0 |
|
943 | 0 | list_for_each_entry_safe ( desc, tmp, &irq_ratelimit_list, rl_link ) |
944 | 0 | { |
945 | 0 | spin_lock(&desc->lock); |
946 | 0 | desc->handler->enable(desc); |
947 | 0 | list_del(&desc->rl_link); |
948 | 0 | INIT_LIST_HEAD(&desc->rl_link); |
949 | 0 | spin_unlock(&desc->lock); |
950 | 0 | } |
951 | 0 |
|
952 | 0 | spin_unlock_irqrestore(&irq_ratelimit_lock, flags); |
953 | 0 | } |
954 | | |
955 | | static int __init irq_ratelimit_init(void) |
956 | 1 | { |
957 | 1 | if ( irq_ratelimit_threshold ) |
958 | 1 | init_timer(&irq_ratelimit_timer, irq_ratelimit_timer_fn, NULL, 0); |
959 | 1 | return 0; |
960 | 1 | } |
961 | | __initcall(irq_ratelimit_init); |
962 | | |
963 | | int __init request_irq(unsigned int irq, unsigned int irqflags, |
964 | | void (*handler)(int, void *, struct cpu_user_regs *), |
965 | | const char * devname, void *dev_id) |
966 | 1 | { |
967 | 1 | struct irqaction * action; |
968 | 1 | int retval; |
969 | 1 | |
970 | 1 | /* |
971 | 1 | * Sanity-check: shared interrupts must pass in a real dev-ID, |
972 | 1 | * otherwise we'll have trouble later trying to figure out |
973 | 1 | * which interrupt is which (messes up the interrupt freeing |
974 | 1 | * logic etc). |
975 | 1 | */ |
976 | 1 | if (irq >= nr_irqs) |
977 | 0 | return -EINVAL; |
978 | 1 | if (!handler) |
979 | 0 | return -EINVAL; |
980 | 1 | |
981 | 1 | action = xmalloc(struct irqaction); |
982 | 1 | if (!action) |
983 | 0 | return -ENOMEM; |
984 | 1 | |
985 | 1 | action->handler = handler; |
986 | 1 | action->name = devname; |
987 | 1 | action->dev_id = dev_id; |
988 | 1 | action->free_on_release = 1; |
989 | 1 | |
990 | 1 | retval = setup_irq(irq, irqflags, action); |
991 | 1 | if (retval) |
992 | 0 | xfree(action); |
993 | 1 | |
994 | 1 | return retval; |
995 | 1 | } |
996 | | |
997 | | void __init release_irq(unsigned int irq, const void *dev_id) |
998 | 0 | { |
999 | 0 | struct irq_desc *desc; |
1000 | 0 | unsigned long flags; |
1001 | 0 | struct irqaction *action; |
1002 | 0 |
|
1003 | 0 | desc = irq_to_desc(irq); |
1004 | 0 |
|
1005 | 0 | spin_lock_irqsave(&desc->lock,flags); |
1006 | 0 | action = desc->action; |
1007 | 0 | desc->action = NULL; |
1008 | 0 | desc->handler->shutdown(desc); |
1009 | 0 | desc->status |= IRQ_DISABLED; |
1010 | 0 | spin_unlock_irqrestore(&desc->lock,flags); |
1011 | 0 |
|
1012 | 0 | /* Wait to make sure it's not being used on another CPU */ |
1013 | 0 | do { smp_mb(); } while ( desc->status & IRQ_INPROGRESS ); |
1014 | 0 |
|
1015 | 0 | if (action && action->free_on_release) |
1016 | 0 | xfree(action); |
1017 | 0 | } |
1018 | | |
1019 | | int __init setup_irq(unsigned int irq, unsigned int irqflags, |
1020 | | struct irqaction *new) |
1021 | 4 | { |
1022 | 4 | struct irq_desc *desc; |
1023 | 4 | unsigned long flags; |
1024 | 4 | |
1025 | 4 | ASSERT(irqflags == 0); |
1026 | 4 | |
1027 | 4 | desc = irq_to_desc(irq); |
1028 | 4 | |
1029 | 4 | spin_lock_irqsave(&desc->lock,flags); |
1030 | 4 | |
1031 | 4 | if ( desc->action != NULL ) |
1032 | 0 | { |
1033 | 0 | spin_unlock_irqrestore(&desc->lock,flags); |
1034 | 0 | return -EBUSY; |
1035 | 0 | } |
1036 | 4 | |
1037 | 4 | desc->action = new; |
1038 | 4 | desc->status &= ~IRQ_DISABLED; |
1039 | 4 | desc->handler->startup(desc); |
1040 | 4 | |
1041 | 4 | spin_unlock_irqrestore(&desc->lock,flags); |
1042 | 4 | |
1043 | 4 | return 0; |
1044 | 4 | } |
1045 | | |
1046 | | |
1047 | | /* |
1048 | | * HANDLING OF GUEST-BOUND PHYSICAL IRQS |
1049 | | */ |
1050 | | |
1051 | 48 | #define IRQ_MAX_GUESTS 7 |
1052 | | typedef struct { |
1053 | | u8 nr_guests; |
1054 | | u8 in_flight; |
1055 | | u8 shareable; |
1056 | | u8 ack_type; |
1057 | 12.2k | #define ACKTYPE_NONE 0 /* No final acknowledgement is required */ |
1058 | 303 | #define ACKTYPE_UNMASK 1 /* Unmask PIC hardware (from any CPU) */ |
1059 | 7.69k | #define ACKTYPE_EOI 2 /* EOI on the CPU that was interrupted */ |
1060 | | cpumask_var_t cpu_eoi_map; /* CPUs that need to EOI this interrupt */ |
1061 | | struct timer eoi_timer; |
1062 | | struct domain *guest[IRQ_MAX_GUESTS]; |
1063 | | } irq_guest_action_t; |
1064 | | |
1065 | | /* |
1066 | | * Stack of interrupts awaiting EOI on each CPU. These must be popped in |
1067 | | * order, as only the current highest-priority pending irq can be EOIed. |
1068 | | */ |
1069 | | struct pending_eoi { |
1070 | | u32 ready:1; /* Ready for EOI now? */ |
1071 | | u32 irq:23; /* irq of the vector */ |
1072 | | u32 vector:8; /* vector awaiting EOI */ |
1073 | | }; |
1074 | | |
1075 | | static DEFINE_PER_CPU(struct pending_eoi, pending_eoi[NR_DYNAMIC_VECTORS]); |
1076 | 17.7k | #define pending_eoi_sp(p) ((p)[NR_DYNAMIC_VECTORS-1].vector) |
1077 | | |
1078 | | bool cpu_has_pending_apic_eoi(void) |
1079 | 0 | { |
1080 | 0 | return pending_eoi_sp(this_cpu(pending_eoi)) != 0; |
1081 | 0 | } |
1082 | | |
1083 | | static inline void set_pirq_eoi(struct domain *d, unsigned int irq) |
1084 | 10 | { |
1085 | 10 | if ( d->arch.pirq_eoi_map ) |
1086 | 0 | { |
1087 | 0 | ASSERT(irq < PAGE_SIZE * BITS_PER_BYTE); |
1088 | 0 | set_bit(irq, d->arch.pirq_eoi_map); |
1089 | 0 | } |
1090 | 10 | } |
1091 | | |
1092 | | static inline void clear_pirq_eoi(struct domain *d, unsigned int irq) |
1093 | 38 | { |
1094 | 38 | if ( d->arch.pirq_eoi_map ) |
1095 | 0 | { |
1096 | 0 | ASSERT(irq < PAGE_SIZE * BITS_PER_BYTE); |
1097 | 0 | clear_bit(irq, d->arch.pirq_eoi_map); |
1098 | 0 | } |
1099 | 38 | } |
1100 | | |
1101 | | static void set_eoi_ready(void *data); |
1102 | | |
1103 | | static void irq_guest_eoi_timer_fn(void *data) |
1104 | 3.84k | { |
1105 | 3.84k | struct irq_desc *desc = data; |
1106 | 3.84k | unsigned int irq = desc - irq_desc; |
1107 | 3.84k | irq_guest_action_t *action; |
1108 | 3.84k | cpumask_t cpu_eoi_map; |
1109 | 3.84k | unsigned long flags; |
1110 | 3.84k | |
1111 | 3.84k | spin_lock_irqsave(&desc->lock, flags); |
1112 | 3.84k | |
1113 | 3.84k | if ( !(desc->status & IRQ_GUEST) ) |
1114 | 0 | goto out; |
1115 | 3.84k | |
1116 | 3.84k | action = (irq_guest_action_t *)desc->action; |
1117 | 3.84k | |
1118 | 3.84k | if ( action->ack_type != ACKTYPE_NONE ) |
1119 | 3.84k | { |
1120 | 3.84k | unsigned int i; |
1121 | 7.69k | for ( i = 0; i < action->nr_guests; i++ ) |
1122 | 3.84k | { |
1123 | 3.84k | struct domain *d = action->guest[i]; |
1124 | 3.84k | unsigned int pirq = domain_irq_to_pirq(d, irq); |
1125 | 3.84k | if ( test_and_clear_bool(pirq_info(d, pirq)->masked) ) |
1126 | 3.84k | action->in_flight--; |
1127 | 3.84k | } |
1128 | 3.84k | } |
1129 | 3.84k | |
1130 | 3.84k | if ( action->in_flight != 0 ) |
1131 | 0 | goto out; |
1132 | 3.84k | |
1133 | 3.84k | switch ( action->ack_type ) |
1134 | 3.84k | { |
1135 | 299 | case ACKTYPE_UNMASK: |
1136 | 299 | if ( desc->handler->end ) |
1137 | 299 | desc->handler->end(desc, 0); |
1138 | 299 | break; |
1139 | 3.54k | case ACKTYPE_EOI: |
1140 | 3.54k | cpumask_copy(&cpu_eoi_map, action->cpu_eoi_map); |
1141 | 3.54k | spin_unlock_irq(&desc->lock); |
1142 | 3.54k | on_selected_cpus(&cpu_eoi_map, set_eoi_ready, desc, 0); |
1143 | 3.54k | spin_lock_irq(&desc->lock); |
1144 | 3.54k | break; |
1145 | 3.84k | } |
1146 | 3.84k | |
1147 | 3.84k | out: |
1148 | 3.84k | spin_unlock_irqrestore(&desc->lock, flags); |
1149 | 3.84k | } |
1150 | | |
1151 | | static void __do_IRQ_guest(int irq) |
1152 | 4.14k | { |
1153 | 4.14k | struct irq_desc *desc = irq_to_desc(irq); |
1154 | 4.14k | irq_guest_action_t *action = (irq_guest_action_t *)desc->action; |
1155 | 4.14k | struct domain *d; |
1156 | 4.14k | int i, sp; |
1157 | 4.14k | struct pending_eoi *peoi = this_cpu(pending_eoi); |
1158 | 4.14k | unsigned int vector = (u8)get_irq_regs()->entry_vector; |
1159 | 4.14k | |
1160 | 4.14k | if ( unlikely(action->nr_guests == 0) ) |
1161 | 0 | { |
1162 | 0 | /* An interrupt may slip through while freeing an ACKTYPE_EOI irq. */ |
1163 | 0 | ASSERT(action->ack_type == ACKTYPE_EOI); |
1164 | 0 | ASSERT(desc->status & IRQ_DISABLED); |
1165 | 0 | if ( desc->handler->end ) |
1166 | 0 | desc->handler->end(desc, vector); |
1167 | 0 | return; |
1168 | 0 | } |
1169 | 4.14k | |
1170 | 4.14k | if ( action->ack_type == ACKTYPE_EOI ) |
1171 | 3.54k | { |
1172 | 3.54k | sp = pending_eoi_sp(peoi); |
1173 | 3.54k | ASSERT((sp == 0) || (peoi[sp-1].vector < vector)); |
1174 | 3.54k | ASSERT(sp < (NR_DYNAMIC_VECTORS-1)); |
1175 | 3.54k | peoi[sp].irq = irq; |
1176 | 3.54k | peoi[sp].vector = vector; |
1177 | 3.54k | peoi[sp].ready = 0; |
1178 | 3.54k | pending_eoi_sp(peoi) = sp+1; |
1179 | 3.54k | cpumask_set_cpu(smp_processor_id(), action->cpu_eoi_map); |
1180 | 3.54k | } |
1181 | 4.14k | |
1182 | 8.29k | for ( i = 0; i < action->nr_guests; i++ ) |
1183 | 4.14k | { |
1184 | 4.14k | struct pirq *pirq; |
1185 | 4.14k | |
1186 | 4.14k | d = action->guest[i]; |
1187 | 4.14k | pirq = pirq_info(d, domain_irq_to_pirq(d, irq)); |
1188 | 4.14k | if ( (action->ack_type != ACKTYPE_NONE) && |
1189 | 3.84k | !test_and_set_bool(pirq->masked) ) |
1190 | 3.84k | action->in_flight++; |
1191 | 4.14k | if ( !is_hvm_domain(d) || !hvm_do_IRQ_dpci(d, pirq) ) |
1192 | 0 | send_guest_pirq(d, pirq); |
1193 | 4.14k | } |
1194 | 4.14k | |
1195 | 4.14k | if ( action->ack_type != ACKTYPE_NONE ) |
1196 | 3.84k | { |
1197 | 3.84k | stop_timer(&action->eoi_timer); |
1198 | 3.84k | migrate_timer(&action->eoi_timer, smp_processor_id()); |
1199 | 3.84k | set_timer(&action->eoi_timer, NOW() + MILLISECS(1)); |
1200 | 3.84k | } |
1201 | 4.14k | } |
1202 | | |
1203 | | /* |
1204 | | * Retrieve Xen irq-descriptor corresponding to a domain-specific irq. |
1205 | | * The descriptor is returned locked. This function is safe against changes |
1206 | | * to the per-domain irq-to-vector mapping. |
1207 | | */ |
1208 | | struct irq_desc *domain_spin_lock_irq_desc( |
1209 | | struct domain *d, int pirq, unsigned long *pflags) |
1210 | 36 | { |
1211 | 36 | const struct pirq *info = pirq_info(d, pirq); |
1212 | 36 | |
1213 | 36 | return info ? pirq_spin_lock_irq_desc(info, pflags) : NULL; |
1214 | 36 | } |
1215 | | |
1216 | | /* |
1217 | | * Same with struct pirq already looked up. |
1218 | | */ |
1219 | | struct irq_desc *pirq_spin_lock_irq_desc( |
1220 | | const struct pirq *pirq, unsigned long *pflags) |
1221 | 199 | { |
1222 | 199 | struct irq_desc *desc; |
1223 | 199 | unsigned long flags; |
1224 | 199 | |
1225 | 199 | for ( ; ; ) |
1226 | 199 | { |
1227 | 199 | int irq = pirq->arch.irq; |
1228 | 199 | |
1229 | 199 | if ( irq <= 0 ) |
1230 | 0 | return NULL; |
1231 | 199 | |
1232 | 199 | desc = irq_to_desc(irq); |
1233 | 199 | spin_lock_irqsave(&desc->lock, flags); |
1234 | 199 | if ( irq == pirq->arch.irq ) |
1235 | 199 | break; |
1236 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
1237 | 0 | } |
1238 | 199 | |
1239 | 199 | if ( pflags ) |
1240 | 36 | *pflags = flags; |
1241 | 199 | |
1242 | 199 | return desc; |
1243 | 199 | } |
1244 | | |
1245 | | static int prepare_domain_irq_pirq(struct domain *d, int irq, int pirq, |
1246 | | struct pirq **pinfo) |
1247 | 48 | { |
1248 | 48 | int err = radix_tree_insert(&d->arch.irq_pirq, irq, |
1249 | 48 | radix_tree_int_to_ptr(0)); |
1250 | 48 | struct pirq *info; |
1251 | 48 | |
1252 | 48 | if ( err && err != -EEXIST ) |
1253 | 0 | return err; |
1254 | 48 | info = pirq_get_info(d, pirq); |
1255 | 48 | if ( !info ) |
1256 | 0 | { |
1257 | 0 | if ( !err ) |
1258 | 0 | radix_tree_delete(&d->arch.irq_pirq, irq); |
1259 | 0 | return -ENOMEM; |
1260 | 0 | } |
1261 | 48 | *pinfo = info; |
1262 | 48 | |
1263 | 48 | return !!err; |
1264 | 48 | } |
1265 | | |
1266 | | static void set_domain_irq_pirq(struct domain *d, int irq, struct pirq *pirq) |
1267 | 48 | { |
1268 | 48 | radix_tree_replace_slot( |
1269 | 48 | radix_tree_lookup_slot(&d->arch.irq_pirq, irq), |
1270 | 48 | radix_tree_int_to_ptr(pirq->pirq)); |
1271 | 48 | pirq->arch.irq = irq; |
1272 | 48 | } |
1273 | | |
1274 | | static void clear_domain_irq_pirq(struct domain *d, int irq, struct pirq *pirq) |
1275 | 0 | { |
1276 | 0 | pirq->arch.irq = 0; |
1277 | 0 | radix_tree_replace_slot( |
1278 | 0 | radix_tree_lookup_slot(&d->arch.irq_pirq, irq), |
1279 | 0 | radix_tree_int_to_ptr(0)); |
1280 | 0 | } |
1281 | | |
1282 | | static void cleanup_domain_irq_pirq(struct domain *d, int irq, |
1283 | | struct pirq *pirq) |
1284 | 0 | { |
1285 | 0 | pirq_cleanup_check(pirq, d); |
1286 | 0 | radix_tree_delete(&d->arch.irq_pirq, irq); |
1287 | 0 | } |
1288 | | |
1289 | | int init_domain_irq_mapping(struct domain *d) |
1290 | 1 | { |
1291 | 1 | unsigned int i; |
1292 | 1 | int err = 0; |
1293 | 1 | |
1294 | 1 | radix_tree_init(&d->arch.irq_pirq); |
1295 | 1 | if ( is_hvm_domain(d) ) |
1296 | 1 | radix_tree_init(&d->arch.hvm_domain.emuirq_pirq); |
1297 | 1 | |
1298 | 16 | for ( i = 1; platform_legacy_irq(i); ++i ) |
1299 | 15 | { |
1300 | 15 | struct pirq *info; |
1301 | 15 | |
1302 | 15 | if ( IO_APIC_IRQ(i) ) |
1303 | 15 | continue; |
1304 | 0 | err = prepare_domain_irq_pirq(d, i, i, &info); |
1305 | 0 | if ( err ) |
1306 | 0 | { |
1307 | 0 | ASSERT(err < 0); |
1308 | 0 | break; |
1309 | 0 | } |
1310 | 0 | set_domain_irq_pirq(d, i, info); |
1311 | 0 | } |
1312 | 1 | |
1313 | 1 | if ( err ) |
1314 | 0 | cleanup_domain_irq_mapping(d); |
1315 | 1 | return err; |
1316 | 1 | } |
1317 | | |
1318 | | void cleanup_domain_irq_mapping(struct domain *d) |
1319 | 0 | { |
1320 | 0 | radix_tree_destroy(&d->arch.irq_pirq, NULL); |
1321 | 0 | if ( is_hvm_domain(d) ) |
1322 | 0 | radix_tree_destroy(&d->arch.hvm_domain.emuirq_pirq, NULL); |
1323 | 0 | } |
1324 | | |
1325 | | struct pirq *alloc_pirq_struct(struct domain *d) |
1326 | 48 | { |
1327 | 48 | size_t sz = is_hvm_domain(d) ? sizeof(struct pirq) : |
1328 | 0 | offsetof(struct pirq, arch.hvm); |
1329 | 48 | struct pirq *pirq = xzalloc_bytes(sz); |
1330 | 48 | |
1331 | 48 | if ( pirq ) |
1332 | 48 | { |
1333 | 48 | if ( is_hvm_domain(d) ) |
1334 | 48 | { |
1335 | 48 | pirq->arch.hvm.emuirq = IRQ_UNBOUND; |
1336 | 48 | pt_pirq_init(d, &pirq->arch.hvm.dpci); |
1337 | 48 | } |
1338 | 48 | } |
1339 | 48 | |
1340 | 48 | return pirq; |
1341 | 48 | } |
1342 | | |
1343 | | void (pirq_cleanup_check)(struct pirq *pirq, struct domain *d) |
1344 | 0 | { |
1345 | 0 | /* |
1346 | 0 | * Check whether all fields have their default values, and delete |
1347 | 0 | * the entry from the tree if so. |
1348 | 0 | * |
1349 | 0 | * NB: Common parts were already checked. |
1350 | 0 | */ |
1351 | 0 | if ( pirq->arch.irq ) |
1352 | 0 | return; |
1353 | 0 |
|
1354 | 0 | if ( is_hvm_domain(d) ) |
1355 | 0 | { |
1356 | 0 | if ( pirq->arch.hvm.emuirq != IRQ_UNBOUND ) |
1357 | 0 | return; |
1358 | 0 | if ( !pt_pirq_cleanup_check(&pirq->arch.hvm.dpci) ) |
1359 | 0 | return; |
1360 | 0 | } |
1361 | 0 |
|
1362 | 0 | if ( radix_tree_delete(&d->pirq_tree, pirq->pirq) != pirq ) |
1363 | 0 | BUG(); |
1364 | 0 | } |
1365 | | |
1366 | | /* Flush all ready EOIs from the top of this CPU's pending-EOI stack. */ |
1367 | | static void flush_ready_eoi(void) |
1368 | 3.54k | { |
1369 | 3.54k | struct pending_eoi *peoi = this_cpu(pending_eoi); |
1370 | 3.54k | struct irq_desc *desc; |
1371 | 3.54k | int irq, sp; |
1372 | 3.54k | |
1373 | 3.54k | ASSERT(!local_irq_is_enabled()); |
1374 | 3.54k | |
1375 | 3.54k | sp = pending_eoi_sp(peoi); |
1376 | 3.54k | |
1377 | 7.09k | while ( (--sp >= 0) && peoi[sp].ready ) |
1378 | 3.54k | { |
1379 | 3.54k | irq = peoi[sp].irq; |
1380 | 3.54k | ASSERT(irq > 0); |
1381 | 3.54k | desc = irq_to_desc(irq); |
1382 | 3.54k | spin_lock(&desc->lock); |
1383 | 3.54k | if ( desc->handler->end ) |
1384 | 3.54k | desc->handler->end(desc, peoi[sp].vector); |
1385 | 3.54k | spin_unlock(&desc->lock); |
1386 | 3.54k | } |
1387 | 3.54k | |
1388 | 3.54k | pending_eoi_sp(peoi) = sp+1; |
1389 | 3.54k | } |
1390 | | |
1391 | | static void __set_eoi_ready(struct irq_desc *desc) |
1392 | 3.54k | { |
1393 | 3.54k | irq_guest_action_t *action = (irq_guest_action_t *)desc->action; |
1394 | 3.54k | struct pending_eoi *peoi = this_cpu(pending_eoi); |
1395 | 3.54k | int irq, sp; |
1396 | 3.54k | |
1397 | 3.54k | irq = desc - irq_desc; |
1398 | 3.54k | |
1399 | 3.54k | if ( !(desc->status & IRQ_GUEST) || |
1400 | 3.54k | (action->in_flight != 0) || |
1401 | 3.54k | !cpumask_test_and_clear_cpu(smp_processor_id(), |
1402 | 3.54k | action->cpu_eoi_map) ) |
1403 | 0 | return; |
1404 | 3.54k | |
1405 | 3.54k | sp = pending_eoi_sp(peoi); |
1406 | 3.54k | |
1407 | 3.54k | do { |
1408 | 3.54k | ASSERT(sp > 0); |
1409 | 3.54k | } while ( peoi[--sp].irq != irq ); |
1410 | 3.54k | ASSERT(!peoi[sp].ready); |
1411 | 3.54k | peoi[sp].ready = 1; |
1412 | 3.54k | } |
1413 | | |
1414 | | /* Mark specified IRQ as ready-for-EOI (if it really is) and attempt to EOI. */ |
1415 | | static void set_eoi_ready(void *data) |
1416 | 3.54k | { |
1417 | 3.54k | struct irq_desc *desc = data; |
1418 | 3.54k | |
1419 | 3.54k | ASSERT(!local_irq_is_enabled()); |
1420 | 3.54k | |
1421 | 3.54k | spin_lock(&desc->lock); |
1422 | 3.54k | __set_eoi_ready(desc); |
1423 | 3.54k | spin_unlock(&desc->lock); |
1424 | 3.54k | |
1425 | 3.54k | flush_ready_eoi(); |
1426 | 3.54k | } |
1427 | | |
1428 | | void pirq_guest_eoi(struct pirq *pirq) |
1429 | 67 | { |
1430 | 67 | struct irq_desc *desc; |
1431 | 67 | |
1432 | 67 | ASSERT(local_irq_is_enabled()); |
1433 | 67 | desc = pirq_spin_lock_irq_desc(pirq, NULL); |
1434 | 67 | if ( desc ) |
1435 | 67 | desc_guest_eoi(desc, pirq); |
1436 | 67 | } |
1437 | | |
1438 | | void desc_guest_eoi(struct irq_desc *desc, struct pirq *pirq) |
1439 | 67 | { |
1440 | 67 | irq_guest_action_t *action; |
1441 | 67 | cpumask_t cpu_eoi_map; |
1442 | 67 | int irq; |
1443 | 67 | |
1444 | 67 | if ( !(desc->status & IRQ_GUEST) ) |
1445 | 0 | { |
1446 | 0 | spin_unlock_irq(&desc->lock); |
1447 | 0 | return; |
1448 | 0 | } |
1449 | 67 | |
1450 | 67 | action = (irq_guest_action_t *)desc->action; |
1451 | 67 | irq = desc - irq_desc; |
1452 | 67 | |
1453 | 67 | if ( unlikely(!test_and_clear_bool(pirq->masked)) || |
1454 | 0 | unlikely(--action->in_flight != 0) ) |
1455 | 67 | { |
1456 | 67 | spin_unlock_irq(&desc->lock); |
1457 | 67 | return; |
1458 | 67 | } |
1459 | 67 | |
1460 | 0 | if ( action->ack_type == ACKTYPE_UNMASK ) |
1461 | 0 | { |
1462 | 0 | ASSERT(cpumask_empty(action->cpu_eoi_map)); |
1463 | 0 | if ( desc->handler->end ) |
1464 | 0 | desc->handler->end(desc, 0); |
1465 | 0 | spin_unlock_irq(&desc->lock); |
1466 | 0 | return; |
1467 | 0 | } |
1468 | 0 |
|
1469 | 0 | ASSERT(action->ack_type == ACKTYPE_EOI); |
1470 | 0 | |
1471 | 0 | cpumask_copy(&cpu_eoi_map, action->cpu_eoi_map); |
1472 | 0 |
|
1473 | 0 | if ( __cpumask_test_and_clear_cpu(smp_processor_id(), &cpu_eoi_map) ) |
1474 | 0 | { |
1475 | 0 | __set_eoi_ready(desc); |
1476 | 0 | spin_unlock(&desc->lock); |
1477 | 0 | flush_ready_eoi(); |
1478 | 0 | local_irq_enable(); |
1479 | 0 | } |
1480 | 0 | else |
1481 | 0 | { |
1482 | 0 | spin_unlock_irq(&desc->lock); |
1483 | 0 | } |
1484 | 0 |
|
1485 | 0 | if ( !cpumask_empty(&cpu_eoi_map) ) |
1486 | 0 | on_selected_cpus(&cpu_eoi_map, set_eoi_ready, desc, 0); |
1487 | 0 | } |
1488 | | |
1489 | | int pirq_guest_unmask(struct domain *d) |
1490 | 0 | { |
1491 | 0 | unsigned int pirq = 0, n, i; |
1492 | 0 | struct pirq *pirqs[16]; |
1493 | 0 |
|
1494 | 0 | do { |
1495 | 0 | n = radix_tree_gang_lookup(&d->pirq_tree, (void **)pirqs, pirq, |
1496 | 0 | ARRAY_SIZE(pirqs)); |
1497 | 0 | for ( i = 0; i < n; ++i ) |
1498 | 0 | { |
1499 | 0 | pirq = pirqs[i]->pirq; |
1500 | 0 | if ( pirqs[i]->masked && |
1501 | 0 | !evtchn_port_is_masked(d, pirqs[i]->evtchn) ) |
1502 | 0 | pirq_guest_eoi(pirqs[i]); |
1503 | 0 | } |
1504 | 0 | } while ( ++pirq < d->nr_pirqs && n == ARRAY_SIZE(pirqs) ); |
1505 | 0 |
|
1506 | 0 | return 0; |
1507 | 0 | } |
1508 | | |
1509 | | static int pirq_acktype(struct domain *d, int pirq) |
1510 | 48 | { |
1511 | 48 | struct irq_desc *desc; |
1512 | 48 | int irq; |
1513 | 48 | |
1514 | 48 | irq = domain_pirq_to_irq(d, pirq); |
1515 | 48 | if ( irq <= 0 ) |
1516 | 0 | return ACKTYPE_NONE; |
1517 | 48 | |
1518 | 48 | desc = irq_to_desc(irq); |
1519 | 48 | |
1520 | 48 | if ( desc->handler == &no_irq_type ) |
1521 | 0 | return ACKTYPE_NONE; |
1522 | 48 | |
1523 | 48 | /* |
1524 | 48 | * Edge-triggered IO-APIC and LAPIC interrupts need no final |
1525 | 48 | * acknowledgement: we ACK early during interrupt processing. |
1526 | 48 | */ |
1527 | 48 | if ( !strcmp(desc->handler->typename, "IO-APIC-edge") || |
1528 | 46 | !strcmp(desc->handler->typename, "local-APIC-edge") ) |
1529 | 2 | return ACKTYPE_NONE; |
1530 | 48 | |
1531 | 48 | /* |
1532 | 48 | * MSIs are treated as edge-triggered interrupts, except |
1533 | 48 | * when there is no proper way to mask them. |
1534 | 48 | */ |
1535 | 46 | if ( desc->msi_desc ) |
1536 | 42 | return msi_maskable_irq(desc->msi_desc) ? ACKTYPE_NONE : ACKTYPE_EOI; |
1537 | 46 | |
1538 | 46 | /* |
1539 | 46 | * Level-triggered IO-APIC interrupts need to be acknowledged on the CPU |
1540 | 46 | * on which they were received. This is because we tickle the LAPIC to EOI. |
1541 | 46 | */ |
1542 | 4 | if ( !strcmp(desc->handler->typename, "IO-APIC-level") ) |
1543 | 4 | return desc->handler->ack == irq_complete_move ? |
1544 | 4 | ACKTYPE_EOI : ACKTYPE_UNMASK; |
1545 | 4 | |
1546 | 4 | /* Legacy PIC interrupts can be acknowledged from any CPU. */ |
1547 | 0 | if ( !strcmp(desc->handler->typename, "XT-PIC") ) |
1548 | 0 | return ACKTYPE_UNMASK; |
1549 | 0 |
|
1550 | 0 | printk("Unknown PIC type '%s' for IRQ %d\n", desc->handler->typename, irq); |
1551 | 0 | BUG(); |
1552 | 0 |
|
1553 | 0 | return 0; |
1554 | 0 | } |
1555 | | |
1556 | | int pirq_shared(struct domain *d, int pirq) |
1557 | 0 | { |
1558 | 0 | struct irq_desc *desc; |
1559 | 0 | irq_guest_action_t *action; |
1560 | 0 | unsigned long flags; |
1561 | 0 | int shared; |
1562 | 0 |
|
1563 | 0 | desc = domain_spin_lock_irq_desc(d, pirq, &flags); |
1564 | 0 | if ( desc == NULL ) |
1565 | 0 | return 0; |
1566 | 0 |
|
1567 | 0 | action = (irq_guest_action_t *)desc->action; |
1568 | 0 | shared = ((desc->status & IRQ_GUEST) && (action->nr_guests > 1)); |
1569 | 0 |
|
1570 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
1571 | 0 |
|
1572 | 0 | return shared; |
1573 | 0 | } |
1574 | | |
1575 | | int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) |
1576 | 48 | { |
1577 | 48 | unsigned int irq; |
1578 | 48 | struct irq_desc *desc; |
1579 | 48 | irq_guest_action_t *action, *newaction = NULL; |
1580 | 48 | int rc = 0; |
1581 | 48 | |
1582 | 48 | WARN_ON(!spin_is_locked(&v->domain->event_lock)); |
1583 | 48 | BUG_ON(!local_irq_is_enabled()); |
1584 | 48 | |
1585 | 96 | retry: |
1586 | 96 | desc = pirq_spin_lock_irq_desc(pirq, NULL); |
1587 | 96 | if ( desc == NULL ) |
1588 | 0 | { |
1589 | 0 | rc = -EINVAL; |
1590 | 0 | goto out; |
1591 | 0 | } |
1592 | 96 | |
1593 | 96 | action = (irq_guest_action_t *)desc->action; |
1594 | 96 | irq = desc - irq_desc; |
1595 | 96 | |
1596 | 96 | if ( !(desc->status & IRQ_GUEST) ) |
1597 | 96 | { |
1598 | 96 | if ( desc->action != NULL ) |
1599 | 0 | { |
1600 | 0 | printk(XENLOG_G_INFO |
1601 | 0 | "Cannot bind IRQ%d to dom%d. In use by '%s'.\n", |
1602 | 0 | pirq->pirq, v->domain->domain_id, desc->action->name); |
1603 | 0 | rc = -EBUSY; |
1604 | 0 | goto unlock_out; |
1605 | 0 | } |
1606 | 96 | |
1607 | 96 | if ( newaction == NULL ) |
1608 | 48 | { |
1609 | 48 | spin_unlock_irq(&desc->lock); |
1610 | 48 | if ( (newaction = xmalloc(irq_guest_action_t)) != NULL && |
1611 | 48 | zalloc_cpumask_var(&newaction->cpu_eoi_map) ) |
1612 | 48 | goto retry; |
1613 | 0 | xfree(newaction); |
1614 | 0 | printk(XENLOG_G_INFO |
1615 | 0 | "Cannot bind IRQ%d to dom%d. Out of memory.\n", |
1616 | 0 | pirq->pirq, v->domain->domain_id); |
1617 | 0 | return -ENOMEM; |
1618 | 48 | } |
1619 | 96 | |
1620 | 48 | action = newaction; |
1621 | 48 | desc->action = (struct irqaction *)action; |
1622 | 48 | newaction = NULL; |
1623 | 48 | |
1624 | 48 | action->nr_guests = 0; |
1625 | 48 | action->in_flight = 0; |
1626 | 48 | action->shareable = will_share; |
1627 | 48 | action->ack_type = pirq_acktype(v->domain, pirq->pirq); |
1628 | 48 | init_timer(&action->eoi_timer, irq_guest_eoi_timer_fn, desc, 0); |
1629 | 48 | |
1630 | 48 | desc->status |= IRQ_GUEST; |
1631 | 48 | |
1632 | 48 | /* Attempt to bind the interrupt target to the correct CPU. */ |
1633 | 48 | if ( !opt_noirqbalance && (desc->handler->set_affinity != NULL) ) |
1634 | 48 | desc->handler->set_affinity(desc, cpumask_of(v->processor)); |
1635 | 48 | |
1636 | 48 | desc->status &= ~IRQ_DISABLED; |
1637 | 48 | desc->handler->startup(desc); |
1638 | 48 | } |
1639 | 0 | else if ( !will_share || !action->shareable ) |
1640 | 0 | { |
1641 | 0 | printk(XENLOG_G_INFO "Cannot bind IRQ%d to dom%d. %s.\n", |
1642 | 0 | pirq->pirq, v->domain->domain_id, |
1643 | 0 | will_share ? "Others do not share" |
1644 | 0 | : "Will not share with others"); |
1645 | 0 | rc = -EBUSY; |
1646 | 0 | goto unlock_out; |
1647 | 0 | } |
1648 | 0 | else if ( action->nr_guests == 0 ) |
1649 | 0 | { |
1650 | 0 | /* |
1651 | 0 | * Indicates that an ACKTYPE_EOI interrupt is being released. |
1652 | 0 | * Wait for that to happen before continuing. |
1653 | 0 | */ |
1654 | 0 | ASSERT(action->ack_type == ACKTYPE_EOI); |
1655 | 0 | ASSERT(desc->status & IRQ_DISABLED); |
1656 | 0 | spin_unlock_irq(&desc->lock); |
1657 | 0 | cpu_relax(); |
1658 | 0 | goto retry; |
1659 | 0 | } |
1660 | 96 | |
1661 | 48 | if ( action->nr_guests == IRQ_MAX_GUESTS ) |
1662 | 0 | { |
1663 | 0 | printk(XENLOG_G_INFO "Cannot bind IRQ%d to dom%d. " |
1664 | 0 | "Already at max share.\n", |
1665 | 0 | pirq->pirq, v->domain->domain_id); |
1666 | 0 | rc = -EBUSY; |
1667 | 0 | goto unlock_out; |
1668 | 0 | } |
1669 | 48 | |
1670 | 48 | action->guest[action->nr_guests++] = v->domain; |
1671 | 48 | |
1672 | 48 | if ( action->ack_type != ACKTYPE_NONE ) |
1673 | 10 | set_pirq_eoi(v->domain, pirq->pirq); |
1674 | 48 | else |
1675 | 38 | clear_pirq_eoi(v->domain, pirq->pirq); |
1676 | 48 | |
1677 | 48 | unlock_out: |
1678 | 48 | spin_unlock_irq(&desc->lock); |
1679 | 48 | out: |
1680 | 48 | if ( newaction != NULL ) |
1681 | 0 | { |
1682 | 0 | free_cpumask_var(newaction->cpu_eoi_map); |
1683 | 0 | xfree(newaction); |
1684 | 0 | } |
1685 | 48 | return rc; |
1686 | 48 | } |
1687 | | |
1688 | | static irq_guest_action_t *__pirq_guest_unbind( |
1689 | | struct domain *d, struct pirq *pirq, struct irq_desc *desc) |
1690 | 0 | { |
1691 | 0 | unsigned int irq; |
1692 | 0 | irq_guest_action_t *action; |
1693 | 0 | cpumask_t cpu_eoi_map; |
1694 | 0 | int i; |
1695 | 0 |
|
1696 | 0 | action = (irq_guest_action_t *)desc->action; |
1697 | 0 | irq = desc - irq_desc; |
1698 | 0 |
|
1699 | 0 | if ( unlikely(action == NULL) ) |
1700 | 0 | { |
1701 | 0 | dprintk(XENLOG_G_WARNING, "dom%d: pirq %d: desc->action is NULL!\n", |
1702 | 0 | d->domain_id, pirq->pirq); |
1703 | 0 | return NULL; |
1704 | 0 | } |
1705 | 0 |
|
1706 | 0 | BUG_ON(!(desc->status & IRQ_GUEST)); |
1707 | 0 |
|
1708 | 0 | for ( i = 0; (i < action->nr_guests) && (action->guest[i] != d); i++ ) |
1709 | 0 | continue; |
1710 | 0 | BUG_ON(i == action->nr_guests); |
1711 | 0 | memmove(&action->guest[i], &action->guest[i+1], |
1712 | 0 | (action->nr_guests-i-1) * sizeof(action->guest[0])); |
1713 | 0 | action->nr_guests--; |
1714 | 0 |
|
1715 | 0 | switch ( action->ack_type ) |
1716 | 0 | { |
1717 | 0 | case ACKTYPE_UNMASK: |
1718 | 0 | if ( test_and_clear_bool(pirq->masked) && |
1719 | 0 | (--action->in_flight == 0) && |
1720 | 0 | desc->handler->end ) |
1721 | 0 | desc->handler->end(desc, 0); |
1722 | 0 | break; |
1723 | 0 | case ACKTYPE_EOI: |
1724 | 0 | /* NB. If #guests == 0 then we clear the eoi_map later on. */ |
1725 | 0 | if ( test_and_clear_bool(pirq->masked) && |
1726 | 0 | (--action->in_flight == 0) && |
1727 | 0 | (action->nr_guests != 0) ) |
1728 | 0 | { |
1729 | 0 | cpumask_copy(&cpu_eoi_map, action->cpu_eoi_map); |
1730 | 0 | spin_unlock_irq(&desc->lock); |
1731 | 0 | on_selected_cpus(&cpu_eoi_map, set_eoi_ready, desc, 0); |
1732 | 0 | spin_lock_irq(&desc->lock); |
1733 | 0 | } |
1734 | 0 | break; |
1735 | 0 | } |
1736 | 0 |
|
1737 | 0 | /* |
1738 | 0 | * The guest cannot re-bind to this IRQ until this function returns. So, |
1739 | 0 | * when we have flushed this IRQ from ->masked, it should remain flushed. |
1740 | 0 | */ |
1741 | 0 | BUG_ON(pirq->masked); |
1742 | 0 |
|
1743 | 0 | if ( action->nr_guests != 0 ) |
1744 | 0 | return NULL; |
1745 | 0 |
|
1746 | 0 | BUG_ON(action->in_flight != 0); |
1747 | 0 |
|
1748 | 0 | /* Disabling IRQ before releasing the desc_lock avoids an IRQ storm. */ |
1749 | 0 | desc->handler->disable(desc); |
1750 | 0 | desc->status |= IRQ_DISABLED; |
1751 | 0 |
|
1752 | 0 | /* |
1753 | 0 | * Mark any remaining pending EOIs as ready to flush. |
1754 | 0 | * NOTE: We will need to make this a stronger barrier if in future we allow |
1755 | 0 | * an interrupt vectors to be re-bound to a different PIC. In that case we |
1756 | 0 | * would need to flush all ready EOIs before returning as otherwise the |
1757 | 0 | * desc->handler could change and we would call the wrong 'end' hook. |
1758 | 0 | */ |
1759 | 0 | cpumask_copy(&cpu_eoi_map, action->cpu_eoi_map); |
1760 | 0 | if ( !cpumask_empty(&cpu_eoi_map) ) |
1761 | 0 | { |
1762 | 0 | BUG_ON(action->ack_type != ACKTYPE_EOI); |
1763 | 0 | spin_unlock_irq(&desc->lock); |
1764 | 0 | on_selected_cpus(&cpu_eoi_map, set_eoi_ready, desc, 1); |
1765 | 0 | spin_lock_irq(&desc->lock); |
1766 | 0 | } |
1767 | 0 |
|
1768 | 0 | BUG_ON(!cpumask_empty(action->cpu_eoi_map)); |
1769 | 0 |
|
1770 | 0 | desc->action = NULL; |
1771 | 0 | desc->status &= ~(IRQ_GUEST|IRQ_INPROGRESS); |
1772 | 0 | desc->handler->shutdown(desc); |
1773 | 0 |
|
1774 | 0 | /* Caller frees the old guest descriptor block. */ |
1775 | 0 | return action; |
1776 | 0 | } |
1777 | | |
1778 | | void pirq_guest_unbind(struct domain *d, struct pirq *pirq) |
1779 | 0 | { |
1780 | 0 | irq_guest_action_t *oldaction = NULL; |
1781 | 0 | struct irq_desc *desc; |
1782 | 0 | int irq = 0; |
1783 | 0 |
|
1784 | 0 | WARN_ON(!spin_is_locked(&d->event_lock)); |
1785 | 0 |
|
1786 | 0 | BUG_ON(!local_irq_is_enabled()); |
1787 | 0 | desc = pirq_spin_lock_irq_desc(pirq, NULL); |
1788 | 0 |
|
1789 | 0 | if ( desc == NULL ) |
1790 | 0 | { |
1791 | 0 | irq = -pirq->arch.irq; |
1792 | 0 | BUG_ON(irq <= 0); |
1793 | 0 | desc = irq_to_desc(irq); |
1794 | 0 | spin_lock_irq(&desc->lock); |
1795 | 0 | clear_domain_irq_pirq(d, irq, pirq); |
1796 | 0 | } |
1797 | 0 | else |
1798 | 0 | { |
1799 | 0 | oldaction = __pirq_guest_unbind(d, pirq, desc); |
1800 | 0 | } |
1801 | 0 |
|
1802 | 0 | spin_unlock_irq(&desc->lock); |
1803 | 0 |
|
1804 | 0 | if ( oldaction != NULL ) |
1805 | 0 | { |
1806 | 0 | kill_timer(&oldaction->eoi_timer); |
1807 | 0 | free_cpumask_var(oldaction->cpu_eoi_map); |
1808 | 0 | xfree(oldaction); |
1809 | 0 | } |
1810 | 0 | else if ( irq > 0 ) |
1811 | 0 | cleanup_domain_irq_pirq(d, irq, pirq); |
1812 | 0 | } |
1813 | | |
1814 | | static bool pirq_guest_force_unbind(struct domain *d, struct pirq *pirq) |
1815 | 0 | { |
1816 | 0 | struct irq_desc *desc; |
1817 | 0 | irq_guest_action_t *action, *oldaction = NULL; |
1818 | 0 | unsigned int i; |
1819 | 0 | bool bound = false; |
1820 | 0 |
|
1821 | 0 | WARN_ON(!spin_is_locked(&d->event_lock)); |
1822 | 0 |
|
1823 | 0 | BUG_ON(!local_irq_is_enabled()); |
1824 | 0 | desc = pirq_spin_lock_irq_desc(pirq, NULL); |
1825 | 0 | BUG_ON(desc == NULL); |
1826 | 0 |
|
1827 | 0 | if ( !(desc->status & IRQ_GUEST) ) |
1828 | 0 | goto out; |
1829 | 0 |
|
1830 | 0 | action = (irq_guest_action_t *)desc->action; |
1831 | 0 | if ( unlikely(action == NULL) ) |
1832 | 0 | { |
1833 | 0 | dprintk(XENLOG_G_WARNING, "dom%d: pirq %d: desc->action is NULL!\n", |
1834 | 0 | d->domain_id, pirq->pirq); |
1835 | 0 | goto out; |
1836 | 0 | } |
1837 | 0 |
|
1838 | 0 | for ( i = 0; (i < action->nr_guests) && (action->guest[i] != d); i++ ) |
1839 | 0 | continue; |
1840 | 0 | if ( i == action->nr_guests ) |
1841 | 0 | goto out; |
1842 | 0 |
|
1843 | 0 | bound = true; |
1844 | 0 | oldaction = __pirq_guest_unbind(d, pirq, desc); |
1845 | 0 |
|
1846 | 0 | out: |
1847 | 0 | spin_unlock_irq(&desc->lock); |
1848 | 0 |
|
1849 | 0 | if ( oldaction != NULL ) |
1850 | 0 | { |
1851 | 0 | kill_timer(&oldaction->eoi_timer); |
1852 | 0 | free_cpumask_var(oldaction->cpu_eoi_map); |
1853 | 0 | xfree(oldaction); |
1854 | 0 | } |
1855 | 0 |
|
1856 | 0 | return bound; |
1857 | 0 | } |
1858 | | |
1859 | | static inline bool is_free_pirq(const struct domain *d, |
1860 | | const struct pirq *pirq) |
1861 | 903 | { |
1862 | 861 | return !pirq || (!pirq->arch.irq && (!is_hvm_domain(d) || |
1863 | 0 | pirq->arch.hvm.emuirq == IRQ_UNBOUND)); |
1864 | 903 | } |
1865 | | |
1866 | | int get_free_pirq(struct domain *d, int type) |
1867 | 36 | { |
1868 | 36 | int i; |
1869 | 36 | |
1870 | 36 | ASSERT(spin_is_locked(&d->event_lock)); |
1871 | 36 | |
1872 | 36 | if ( type == MAP_PIRQ_TYPE_GSI ) |
1873 | 0 | { |
1874 | 0 | for ( i = 16; i < nr_irqs_gsi; i++ ) |
1875 | 0 | if ( is_free_pirq(d, pirq_info(d, i)) ) |
1876 | 0 | { |
1877 | 0 | pirq_get_info(d, i); |
1878 | 0 | return i; |
1879 | 0 | } |
1880 | 0 | } |
1881 | 846 | for ( i = d->nr_pirqs - 1; i >= nr_irqs_gsi; i-- ) |
1882 | 846 | if ( is_free_pirq(d, pirq_info(d, i)) ) |
1883 | 36 | { |
1884 | 36 | pirq_get_info(d, i); |
1885 | 36 | return i; |
1886 | 36 | } |
1887 | 36 | |
1888 | 0 | return -ENOSPC; |
1889 | 36 | } |
1890 | | |
1891 | | int get_free_pirqs(struct domain *d, unsigned int nr) |
1892 | 6 | { |
1893 | 6 | unsigned int i, found = 0; |
1894 | 6 | |
1895 | 6 | ASSERT(spin_is_locked(&d->event_lock)); |
1896 | 6 | |
1897 | 57 | for ( i = d->nr_pirqs - 1; i >= nr_irqs_gsi; --i ) |
1898 | 57 | if ( is_free_pirq(d, pirq_info(d, i)) ) |
1899 | 6 | { |
1900 | 6 | pirq_get_info(d, i); |
1901 | 6 | if ( ++found == nr ) |
1902 | 6 | return i; |
1903 | 6 | } |
1904 | 57 | else |
1905 | 51 | found = 0; |
1906 | 6 | |
1907 | 0 | return -ENOSPC; |
1908 | 6 | } |
1909 | | |
1910 | 6 | #define MAX_MSI_IRQS 32 /* limited by MSI capability struct properties */ |
1911 | | |
1912 | | int map_domain_pirq( |
1913 | | struct domain *d, int pirq, int irq, int type, void *data) |
1914 | 48 | { |
1915 | 48 | int ret = 0; |
1916 | 48 | int old_irq, old_pirq; |
1917 | 48 | struct pirq *info; |
1918 | 48 | struct irq_desc *desc; |
1919 | 48 | unsigned long flags; |
1920 | 48 | DECLARE_BITMAP(prepared, MAX_MSI_IRQS) = {}; |
1921 | 48 | |
1922 | 48 | ASSERT(spin_is_locked(&d->event_lock)); |
1923 | 48 | |
1924 | 48 | if ( !irq_access_permitted(current->domain, irq)) |
1925 | 0 | return -EPERM; |
1926 | 48 | |
1927 | 48 | if ( pirq < 0 || pirq >= d->nr_pirqs || irq <= 0 || irq >= nr_irqs ) |
1928 | 0 | { |
1929 | 0 | dprintk(XENLOG_G_ERR, "dom%d: invalid pirq %d or irq %d\n", |
1930 | 0 | d->domain_id, pirq, irq); |
1931 | 0 | return -EINVAL; |
1932 | 0 | } |
1933 | 48 | |
1934 | 48 | old_irq = domain_pirq_to_irq(d, pirq); |
1935 | 48 | old_pirq = domain_irq_to_pirq(d, irq); |
1936 | 48 | |
1937 | 48 | if ( (old_irq > 0 && (old_irq != irq) ) || |
1938 | 48 | (old_pirq && (old_pirq != pirq)) ) |
1939 | 0 | { |
1940 | 0 | dprintk(XENLOG_G_WARNING, |
1941 | 0 | "dom%d: pirq %d or irq %d already mapped (%d,%d)\n", |
1942 | 0 | d->domain_id, pirq, irq, old_pirq, old_irq); |
1943 | 0 | return 0; |
1944 | 0 | } |
1945 | 48 | |
1946 | 48 | ret = xsm_map_domain_irq(XSM_HOOK, d, irq, data); |
1947 | 48 | if ( ret ) |
1948 | 0 | { |
1949 | 0 | dprintk(XENLOG_G_ERR, "dom%d: could not permit access to irq %d mapping to pirq %d\n", |
1950 | 0 | d->domain_id, irq, pirq); |
1951 | 0 | return ret; |
1952 | 0 | } |
1953 | 48 | |
1954 | 48 | ret = irq_permit_access(d, irq); |
1955 | 48 | if ( ret ) |
1956 | 0 | { |
1957 | 0 | printk(XENLOG_G_ERR |
1958 | 0 | "dom%d: could not permit access to IRQ%d (pirq %d)\n", |
1959 | 0 | d->domain_id, irq, pirq); |
1960 | 0 | return ret; |
1961 | 0 | } |
1962 | 48 | |
1963 | 48 | ret = prepare_domain_irq_pirq(d, irq, pirq, &info); |
1964 | 48 | if ( ret < 0 ) |
1965 | 0 | goto revoke; |
1966 | 48 | if ( !ret ) |
1967 | 48 | __set_bit(0, prepared); |
1968 | 48 | |
1969 | 48 | desc = irq_to_desc(irq); |
1970 | 48 | |
1971 | 48 | if ( type == MAP_PIRQ_TYPE_MSI || type == MAP_PIRQ_TYPE_MULTI_MSI ) |
1972 | 42 | { |
1973 | 42 | struct msi_info *msi = (struct msi_info *)data; |
1974 | 42 | struct msi_desc *msi_desc; |
1975 | 42 | struct pci_dev *pdev; |
1976 | 42 | unsigned int nr = 0; |
1977 | 42 | |
1978 | 42 | ASSERT(pcidevs_locked()); |
1979 | 42 | |
1980 | 42 | ret = -ENODEV; |
1981 | 42 | if ( !cpu_has_apic ) |
1982 | 0 | goto done; |
1983 | 42 | |
1984 | 42 | pdev = pci_get_pdev_by_domain(d, msi->seg, msi->bus, msi->devfn); |
1985 | 42 | if ( !pdev ) |
1986 | 0 | goto done; |
1987 | 42 | |
1988 | 42 | ret = pci_enable_msi(msi, &msi_desc); |
1989 | 42 | if ( ret ) |
1990 | 0 | { |
1991 | 0 | if ( ret > 0 ) |
1992 | 0 | { |
1993 | 0 | msi->entry_nr = ret; |
1994 | 0 | ret = -ENFILE; |
1995 | 0 | } |
1996 | 0 | goto done; |
1997 | 0 | } |
1998 | 42 | |
1999 | 42 | spin_lock_irqsave(&desc->lock, flags); |
2000 | 42 | |
2001 | 42 | if ( desc->handler != &no_irq_type ) |
2002 | 0 | { |
2003 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2004 | 0 | dprintk(XENLOG_G_ERR, "dom%d: irq %d in use\n", |
2005 | 0 | d->domain_id, irq); |
2006 | 0 | pci_disable_msi(msi_desc); |
2007 | 0 | msi_desc->irq = -1; |
2008 | 0 | msi_free_irq(msi_desc); |
2009 | 0 | ret = -EBUSY; |
2010 | 0 | goto done; |
2011 | 0 | } |
2012 | 42 | |
2013 | 42 | while ( !(ret = setup_msi_irq(desc, msi_desc + nr)) ) |
2014 | 42 | { |
2015 | 42 | if ( opt_irq_vector_map == OPT_IRQ_VECTOR_MAP_PERDEV && |
2016 | 0 | !desc->arch.used_vectors ) |
2017 | 0 | { |
2018 | 0 | desc->arch.used_vectors = &pdev->arch.used_vectors; |
2019 | 0 | if ( desc->arch.vector != IRQ_VECTOR_UNASSIGNED ) |
2020 | 0 | { |
2021 | 0 | int vector = desc->arch.vector; |
2022 | 0 |
|
2023 | 0 | ASSERT(!test_bit(vector, desc->arch.used_vectors)); |
2024 | 0 | set_bit(vector, desc->arch.used_vectors); |
2025 | 0 | } |
2026 | 0 | } |
2027 | 42 | if ( type == MAP_PIRQ_TYPE_MSI || |
2028 | 6 | msi_desc->msi_attrib.type != PCI_CAP_ID_MSI || |
2029 | 6 | ++nr == msi->entry_nr ) |
2030 | 42 | break; |
2031 | 42 | |
2032 | 0 | set_domain_irq_pirq(d, irq, info); |
2033 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2034 | 0 |
|
2035 | 0 | info = NULL; |
2036 | 0 | irq = create_irq(NUMA_NO_NODE); |
2037 | 0 | ret = irq >= 0 ? prepare_domain_irq_pirq(d, irq, pirq + nr, &info) |
2038 | 0 | : irq; |
2039 | 0 | if ( ret < 0 ) |
2040 | 0 | break; |
2041 | 0 | if ( !ret ) |
2042 | 0 | __set_bit(nr, prepared); |
2043 | 0 | msi_desc[nr].irq = irq; |
2044 | 0 |
|
2045 | 0 | if ( irq_permit_access(d, irq) != 0 ) |
2046 | 0 | printk(XENLOG_G_WARNING |
2047 | 0 | "dom%d: could not permit access to IRQ%d (pirq %d)\n", |
2048 | 0 | d->domain_id, irq, pirq); |
2049 | 0 |
|
2050 | 0 | desc = irq_to_desc(irq); |
2051 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2052 | 0 |
|
2053 | 0 | if ( desc->handler != &no_irq_type ) |
2054 | 0 | { |
2055 | 0 | dprintk(XENLOG_G_ERR, "dom%d: irq %d (pirq %u) in use (%s)\n", |
2056 | 0 | d->domain_id, irq, pirq + nr, desc->handler->typename); |
2057 | 0 | ret = -EBUSY; |
2058 | 0 | break; |
2059 | 0 | } |
2060 | 0 | } |
2061 | 42 | |
2062 | 42 | if ( ret ) |
2063 | 0 | { |
2064 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2065 | 0 | pci_disable_msi(msi_desc); |
2066 | 0 | if ( nr ) |
2067 | 0 | { |
2068 | 0 | ASSERT(msi_desc->irq >= 0); |
2069 | 0 | desc = irq_to_desc(msi_desc->irq); |
2070 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2071 | 0 | desc->handler = &no_irq_type; |
2072 | 0 | desc->msi_desc = NULL; |
2073 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2074 | 0 | } |
2075 | 0 | while ( nr ) |
2076 | 0 | { |
2077 | 0 | if ( irq >= 0 && irq_deny_access(d, irq) ) |
2078 | 0 | printk(XENLOG_G_ERR |
2079 | 0 | "dom%d: could not revoke access to IRQ%d (pirq %d)\n", |
2080 | 0 | d->domain_id, irq, pirq); |
2081 | 0 | if ( info && test_bit(nr, prepared) ) |
2082 | 0 | cleanup_domain_irq_pirq(d, irq, info); |
2083 | 0 | info = pirq_info(d, pirq + --nr); |
2084 | 0 | irq = info->arch.irq; |
2085 | 0 | } |
2086 | 0 | msi_desc->irq = -1; |
2087 | 0 | msi_free_irq(msi_desc); |
2088 | 0 | goto done; |
2089 | 0 | } |
2090 | 42 | |
2091 | 42 | set_domain_irq_pirq(d, irq, info); |
2092 | 42 | spin_unlock_irqrestore(&desc->lock, flags); |
2093 | 42 | } |
2094 | 48 | else |
2095 | 6 | { |
2096 | 6 | spin_lock_irqsave(&desc->lock, flags); |
2097 | 6 | set_domain_irq_pirq(d, irq, info); |
2098 | 6 | spin_unlock_irqrestore(&desc->lock, flags); |
2099 | 6 | ret = 0; |
2100 | 6 | } |
2101 | 48 | |
2102 | 48 | done: |
2103 | 48 | if ( ret ) |
2104 | 0 | { |
2105 | 0 | if ( test_bit(0, prepared) ) |
2106 | 0 | cleanup_domain_irq_pirq(d, irq, info); |
2107 | 0 | revoke: |
2108 | 0 | if ( irq_deny_access(d, irq) ) |
2109 | 0 | printk(XENLOG_G_ERR |
2110 | 0 | "dom%d: could not revoke access to IRQ%d (pirq %d)\n", |
2111 | 0 | d->domain_id, irq, pirq); |
2112 | 0 | } |
2113 | 48 | return ret; |
2114 | 48 | } |
2115 | | |
2116 | | /* The pirq should have been unbound before this call. */ |
2117 | | int unmap_domain_pirq(struct domain *d, int pirq) |
2118 | 0 | { |
2119 | 0 | unsigned long flags; |
2120 | 0 | struct irq_desc *desc; |
2121 | 0 | int irq, ret = 0, rc; |
2122 | 0 | unsigned int i, nr = 1; |
2123 | 0 | bool forced_unbind; |
2124 | 0 | struct pirq *info; |
2125 | 0 | struct msi_desc *msi_desc = NULL; |
2126 | 0 |
|
2127 | 0 | if ( (pirq < 0) || (pirq >= d->nr_pirqs) ) |
2128 | 0 | return -EINVAL; |
2129 | 0 |
|
2130 | 0 | ASSERT(pcidevs_locked()); |
2131 | 0 | ASSERT(spin_is_locked(&d->event_lock)); |
2132 | 0 |
|
2133 | 0 | info = pirq_info(d, pirq); |
2134 | 0 | if ( !info || (irq = info->arch.irq) <= 0 ) |
2135 | 0 | { |
2136 | 0 | dprintk(XENLOG_G_ERR, "dom%d: pirq %d not mapped\n", |
2137 | 0 | d->domain_id, pirq); |
2138 | 0 | ret = -EINVAL; |
2139 | 0 | goto done; |
2140 | 0 | } |
2141 | 0 |
|
2142 | 0 | desc = irq_to_desc(irq); |
2143 | 0 | msi_desc = desc->msi_desc; |
2144 | 0 | if ( msi_desc && msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) |
2145 | 0 | { |
2146 | 0 | if ( msi_desc->msi_attrib.entry_nr ) |
2147 | 0 | { |
2148 | 0 | printk(XENLOG_G_ERR |
2149 | 0 | "dom%d: trying to unmap secondary MSI pirq %d\n", |
2150 | 0 | d->domain_id, pirq); |
2151 | 0 | ret = -EBUSY; |
2152 | 0 | goto done; |
2153 | 0 | } |
2154 | 0 | nr = msi_desc->msi.nvec; |
2155 | 0 | } |
2156 | 0 |
|
2157 | 0 | ret = xsm_unmap_domain_irq(XSM_HOOK, d, irq, |
2158 | 0 | msi_desc ? msi_desc->dev : NULL); |
2159 | 0 | if ( ret ) |
2160 | 0 | goto done; |
2161 | 0 |
|
2162 | 0 | forced_unbind = pirq_guest_force_unbind(d, info); |
2163 | 0 | if ( forced_unbind ) |
2164 | 0 | dprintk(XENLOG_G_WARNING, "dom%d: forcing unbind of pirq %d\n", |
2165 | 0 | d->domain_id, pirq); |
2166 | 0 |
|
2167 | 0 | if ( msi_desc != NULL ) |
2168 | 0 | pci_disable_msi(msi_desc); |
2169 | 0 |
|
2170 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2171 | 0 |
|
2172 | 0 | for ( i = 0; ; ) |
2173 | 0 | { |
2174 | 0 | BUG_ON(irq != domain_pirq_to_irq(d, pirq + i)); |
2175 | 0 |
|
2176 | 0 | if ( !forced_unbind ) |
2177 | 0 | clear_domain_irq_pirq(d, irq, info); |
2178 | 0 | else |
2179 | 0 | { |
2180 | 0 | info->arch.irq = -irq; |
2181 | 0 | radix_tree_replace_slot( |
2182 | 0 | radix_tree_lookup_slot(&d->arch.irq_pirq, irq), |
2183 | 0 | radix_tree_int_to_ptr(-pirq)); |
2184 | 0 | } |
2185 | 0 |
|
2186 | 0 | if ( msi_desc ) |
2187 | 0 | { |
2188 | 0 | desc->handler = &no_irq_type; |
2189 | 0 | desc->msi_desc = NULL; |
2190 | 0 | } |
2191 | 0 |
|
2192 | 0 | if ( ++i == nr ) |
2193 | 0 | break; |
2194 | 0 |
|
2195 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2196 | 0 |
|
2197 | 0 | if ( !forced_unbind ) |
2198 | 0 | cleanup_domain_irq_pirq(d, irq, info); |
2199 | 0 |
|
2200 | 0 | rc = irq_deny_access(d, irq); |
2201 | 0 | if ( rc ) |
2202 | 0 | { |
2203 | 0 | printk(XENLOG_G_ERR |
2204 | 0 | "dom%d: could not deny access to IRQ%d (pirq %d)\n", |
2205 | 0 | d->domain_id, irq, pirq + i); |
2206 | 0 | ret = rc; |
2207 | 0 | } |
2208 | 0 |
|
2209 | 0 | do { |
2210 | 0 | info = pirq_info(d, pirq + i); |
2211 | 0 | if ( info && (irq = info->arch.irq) > 0 ) |
2212 | 0 | break; |
2213 | 0 | printk(XENLOG_G_ERR "dom%d: MSI pirq %d not mapped\n", |
2214 | 0 | d->domain_id, pirq + i); |
2215 | 0 | } while ( ++i < nr ); |
2216 | 0 |
|
2217 | 0 | if ( i == nr ) |
2218 | 0 | { |
2219 | 0 | desc = NULL; |
2220 | 0 | break; |
2221 | 0 | } |
2222 | 0 |
|
2223 | 0 | desc = irq_to_desc(irq); |
2224 | 0 | BUG_ON(desc->msi_desc != msi_desc + i); |
2225 | 0 |
|
2226 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2227 | 0 | } |
2228 | 0 |
|
2229 | 0 | if ( desc ) |
2230 | 0 | { |
2231 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2232 | 0 |
|
2233 | 0 | if ( !forced_unbind ) |
2234 | 0 | cleanup_domain_irq_pirq(d, irq, info); |
2235 | 0 |
|
2236 | 0 | rc = irq_deny_access(d, irq); |
2237 | 0 | if ( rc ) |
2238 | 0 | { |
2239 | 0 | printk(XENLOG_G_ERR |
2240 | 0 | "dom%d: could not deny access to IRQ%d (pirq %d)\n", |
2241 | 0 | d->domain_id, irq, pirq + nr - 1); |
2242 | 0 | ret = rc; |
2243 | 0 | } |
2244 | 0 | } |
2245 | 0 |
|
2246 | 0 | if (msi_desc) |
2247 | 0 | msi_free_irq(msi_desc); |
2248 | 0 |
|
2249 | 0 | done: |
2250 | 0 | return ret; |
2251 | 0 | } |
2252 | | |
2253 | | void free_domain_pirqs(struct domain *d) |
2254 | 0 | { |
2255 | 0 | int i; |
2256 | 0 |
|
2257 | 0 | pcidevs_lock(); |
2258 | 0 | spin_lock(&d->event_lock); |
2259 | 0 |
|
2260 | 0 | for ( i = 0; i < d->nr_pirqs; i++ ) |
2261 | 0 | if ( domain_pirq_to_irq(d, i) > 0 ) |
2262 | 0 | unmap_domain_pirq(d, i); |
2263 | 0 |
|
2264 | 0 | spin_unlock(&d->event_lock); |
2265 | 0 | pcidevs_unlock(); |
2266 | 0 | } |
2267 | | |
2268 | | static void dump_irqs(unsigned char key) |
2269 | 0 | { |
2270 | 0 | int i, irq, pirq; |
2271 | 0 | struct irq_desc *desc; |
2272 | 0 | irq_guest_action_t *action; |
2273 | 0 | struct domain *d; |
2274 | 0 | const struct pirq *info; |
2275 | 0 | unsigned long flags; |
2276 | 0 | char *ssid; |
2277 | 0 |
|
2278 | 0 | printk("IRQ information:\n"); |
2279 | 0 |
|
2280 | 0 | for ( irq = 0; irq < nr_irqs; irq++ ) |
2281 | 0 | { |
2282 | 0 | if ( !(irq & 0x1f) ) |
2283 | 0 | process_pending_softirqs(); |
2284 | 0 |
|
2285 | 0 | desc = irq_to_desc(irq); |
2286 | 0 |
|
2287 | 0 | if ( !irq_desc_initialized(desc) || desc->handler == &no_irq_type ) |
2288 | 0 | continue; |
2289 | 0 |
|
2290 | 0 | ssid = in_irq() ? NULL : xsm_show_irq_sid(irq); |
2291 | 0 |
|
2292 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2293 | 0 |
|
2294 | 0 | cpumask_scnprintf(keyhandler_scratch, sizeof(keyhandler_scratch), |
2295 | 0 | desc->affinity); |
2296 | 0 | printk(" IRQ:%4d affinity:%s vec:%02x type=%-15s" |
2297 | 0 | " status=%08x ", |
2298 | 0 | irq, keyhandler_scratch, desc->arch.vector, |
2299 | 0 | desc->handler->typename, desc->status); |
2300 | 0 |
|
2301 | 0 | if ( ssid ) |
2302 | 0 | printk("Z=%-25s ", ssid); |
2303 | 0 |
|
2304 | 0 | if ( desc->status & IRQ_GUEST ) |
2305 | 0 | { |
2306 | 0 | action = (irq_guest_action_t *)desc->action; |
2307 | 0 |
|
2308 | 0 | printk("in-flight=%d domain-list=", action->in_flight); |
2309 | 0 |
|
2310 | 0 | for ( i = 0; i < action->nr_guests; i++ ) |
2311 | 0 | { |
2312 | 0 | d = action->guest[i]; |
2313 | 0 | pirq = domain_irq_to_pirq(d, irq); |
2314 | 0 | info = pirq_info(d, pirq); |
2315 | 0 | printk("%u:%3d(%c%c%c)", |
2316 | 0 | d->domain_id, pirq, |
2317 | 0 | evtchn_port_is_pending(d, info->evtchn) ? 'P' : '-', |
2318 | 0 | evtchn_port_is_masked(d, info->evtchn) ? 'M' : '-', |
2319 | 0 | (info->masked ? 'M' : '-')); |
2320 | 0 | if ( i != action->nr_guests ) |
2321 | 0 | printk(","); |
2322 | 0 | } |
2323 | 0 |
|
2324 | 0 | printk("\n"); |
2325 | 0 | } |
2326 | 0 | else if ( desc->action ) |
2327 | 0 | printk("%ps()\n", desc->action->handler); |
2328 | 0 | else |
2329 | 0 | printk("mapped, unbound\n"); |
2330 | 0 |
|
2331 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2332 | 0 |
|
2333 | 0 | xfree(ssid); |
2334 | 0 | } |
2335 | 0 |
|
2336 | 0 | process_pending_softirqs(); |
2337 | 0 | printk("Direct vector information:\n"); |
2338 | 0 | for ( i = FIRST_DYNAMIC_VECTOR; i < NR_VECTORS; ++i ) |
2339 | 0 | if ( direct_apic_vector[i] ) |
2340 | 0 | printk(" %#02x -> %ps()\n", i, direct_apic_vector[i]); |
2341 | 0 |
|
2342 | 0 | dump_ioapic_irq_info(); |
2343 | 0 | } |
2344 | | |
2345 | | static int __init setup_dump_irqs(void) |
2346 | 1 | { |
2347 | 1 | register_keyhandler('i', dump_irqs, "dump interrupt bindings", 1); |
2348 | 1 | return 0; |
2349 | 1 | } |
2350 | | __initcall(setup_dump_irqs); |
2351 | | |
2352 | | /* Reset irq affinities to match the given CPU mask. */ |
2353 | | void fixup_irqs(const cpumask_t *mask, bool verbose) |
2354 | 0 | { |
2355 | 0 | unsigned int irq; |
2356 | 0 | static int warned; |
2357 | 0 | struct irq_desc *desc; |
2358 | 0 |
|
2359 | 0 | for ( irq = 0; irq < nr_irqs; irq++ ) |
2360 | 0 | { |
2361 | 0 | bool break_affinity = false, set_affinity = true; |
2362 | 0 | unsigned int vector; |
2363 | 0 | cpumask_t affinity; |
2364 | 0 |
|
2365 | 0 | if ( irq == 2 ) |
2366 | 0 | continue; |
2367 | 0 |
|
2368 | 0 | desc = irq_to_desc(irq); |
2369 | 0 | if ( !irq_desc_initialized(desc) ) |
2370 | 0 | continue; |
2371 | 0 |
|
2372 | 0 | spin_lock(&desc->lock); |
2373 | 0 |
|
2374 | 0 | vector = irq_to_vector(irq); |
2375 | 0 | if ( vector >= FIRST_HIPRIORITY_VECTOR && |
2376 | 0 | vector <= LAST_HIPRIORITY_VECTOR ) |
2377 | 0 | cpumask_and(desc->arch.cpu_mask, desc->arch.cpu_mask, mask); |
2378 | 0 |
|
2379 | 0 | cpumask_copy(&affinity, desc->affinity); |
2380 | 0 | if ( !desc->action || cpumask_subset(&affinity, mask) ) |
2381 | 0 | { |
2382 | 0 | spin_unlock(&desc->lock); |
2383 | 0 | continue; |
2384 | 0 | } |
2385 | 0 |
|
2386 | 0 | cpumask_and(&affinity, &affinity, mask); |
2387 | 0 | if ( cpumask_empty(&affinity) ) |
2388 | 0 | { |
2389 | 0 | break_affinity = true; |
2390 | 0 | cpumask_copy(&affinity, mask); |
2391 | 0 | } |
2392 | 0 |
|
2393 | 0 | if ( desc->handler->disable ) |
2394 | 0 | desc->handler->disable(desc); |
2395 | 0 |
|
2396 | 0 | if ( desc->handler->set_affinity ) |
2397 | 0 | desc->handler->set_affinity(desc, &affinity); |
2398 | 0 | else if ( !(warned++) ) |
2399 | 0 | set_affinity = false; |
2400 | 0 |
|
2401 | 0 | if ( desc->handler->enable ) |
2402 | 0 | desc->handler->enable(desc); |
2403 | 0 |
|
2404 | 0 | spin_unlock(&desc->lock); |
2405 | 0 |
|
2406 | 0 | if ( !verbose ) |
2407 | 0 | continue; |
2408 | 0 |
|
2409 | 0 | if ( break_affinity && set_affinity ) |
2410 | 0 | printk("Broke affinity for irq %i\n", irq); |
2411 | 0 | else if ( !set_affinity ) |
2412 | 0 | printk("Cannot set affinity for irq %i\n", irq); |
2413 | 0 | } |
2414 | 0 |
|
2415 | 0 | /* That doesn't seem sufficient. Give it 1ms. */ |
2416 | 0 | local_irq_enable(); |
2417 | 0 | mdelay(1); |
2418 | 0 | local_irq_disable(); |
2419 | 0 | } |
2420 | | |
2421 | | void fixup_eoi(void) |
2422 | 0 | { |
2423 | 0 | unsigned int irq, sp; |
2424 | 0 | struct irq_desc *desc; |
2425 | 0 | irq_guest_action_t *action; |
2426 | 0 | struct pending_eoi *peoi; |
2427 | 0 |
|
2428 | 0 | /* Clean up cpu_eoi_map of every interrupt to exclude this CPU. */ |
2429 | 0 | for ( irq = 0; irq < nr_irqs; irq++ ) |
2430 | 0 | { |
2431 | 0 | desc = irq_to_desc(irq); |
2432 | 0 | if ( !(desc->status & IRQ_GUEST) ) |
2433 | 0 | continue; |
2434 | 0 | action = (irq_guest_action_t *)desc->action; |
2435 | 0 | cpumask_clear_cpu(smp_processor_id(), action->cpu_eoi_map); |
2436 | 0 | } |
2437 | 0 |
|
2438 | 0 | /* Flush the interrupt EOI stack. */ |
2439 | 0 | peoi = this_cpu(pending_eoi); |
2440 | 0 | for ( sp = 0; sp < pending_eoi_sp(peoi); sp++ ) |
2441 | 0 | peoi[sp].ready = 1; |
2442 | 0 | flush_ready_eoi(); |
2443 | 0 | } |
2444 | | |
2445 | | int map_domain_emuirq_pirq(struct domain *d, int pirq, int emuirq) |
2446 | 0 | { |
2447 | 0 | int old_emuirq = IRQ_UNBOUND, old_pirq = IRQ_UNBOUND; |
2448 | 0 | struct pirq *info; |
2449 | 0 |
|
2450 | 0 | ASSERT(spin_is_locked(&d->event_lock)); |
2451 | 0 |
|
2452 | 0 | if ( !is_hvm_domain(d) ) |
2453 | 0 | return -EINVAL; |
2454 | 0 |
|
2455 | 0 | if ( pirq < 0 || pirq >= d->nr_pirqs || |
2456 | 0 | emuirq == IRQ_UNBOUND || emuirq >= (int) nr_irqs ) |
2457 | 0 | { |
2458 | 0 | dprintk(XENLOG_G_ERR, "dom%d: invalid pirq %d or emuirq %d\n", |
2459 | 0 | d->domain_id, pirq, emuirq); |
2460 | 0 | return -EINVAL; |
2461 | 0 | } |
2462 | 0 |
|
2463 | 0 | old_emuirq = domain_pirq_to_emuirq(d, pirq); |
2464 | 0 | if ( emuirq != IRQ_PT ) |
2465 | 0 | old_pirq = domain_emuirq_to_pirq(d, emuirq); |
2466 | 0 |
|
2467 | 0 | if ( (old_emuirq != IRQ_UNBOUND && (old_emuirq != emuirq) ) || |
2468 | 0 | (old_pirq != IRQ_UNBOUND && (old_pirq != pirq)) ) |
2469 | 0 | { |
2470 | 0 | dprintk(XENLOG_G_WARNING, "dom%d: pirq %d or emuirq %d already mapped\n", |
2471 | 0 | d->domain_id, pirq, emuirq); |
2472 | 0 | return 0; |
2473 | 0 | } |
2474 | 0 |
|
2475 | 0 | info = pirq_get_info(d, pirq); |
2476 | 0 | if ( !info ) |
2477 | 0 | return -ENOMEM; |
2478 | 0 |
|
2479 | 0 | /* do not store emuirq mappings for pt devices */ |
2480 | 0 | if ( emuirq != IRQ_PT ) |
2481 | 0 | { |
2482 | 0 | int err = radix_tree_insert(&d->arch.hvm_domain.emuirq_pirq, emuirq, |
2483 | 0 | radix_tree_int_to_ptr(pirq)); |
2484 | 0 |
|
2485 | 0 | switch ( err ) |
2486 | 0 | { |
2487 | 0 | case 0: |
2488 | 0 | break; |
2489 | 0 | case -EEXIST: |
2490 | 0 | radix_tree_replace_slot( |
2491 | 0 | radix_tree_lookup_slot( |
2492 | 0 | &d->arch.hvm_domain.emuirq_pirq, emuirq), |
2493 | 0 | radix_tree_int_to_ptr(pirq)); |
2494 | 0 | break; |
2495 | 0 | default: |
2496 | 0 | pirq_cleanup_check(info, d); |
2497 | 0 | return err; |
2498 | 0 | } |
2499 | 0 | } |
2500 | 0 | info->arch.hvm.emuirq = emuirq; |
2501 | 0 |
|
2502 | 0 | return 0; |
2503 | 0 | } |
2504 | | |
2505 | | int unmap_domain_pirq_emuirq(struct domain *d, int pirq) |
2506 | 0 | { |
2507 | 0 | int emuirq, ret = 0; |
2508 | 0 | struct pirq *info; |
2509 | 0 |
|
2510 | 0 | if ( !is_hvm_domain(d) ) |
2511 | 0 | return -EINVAL; |
2512 | 0 |
|
2513 | 0 | if ( (pirq < 0) || (pirq >= d->nr_pirqs) ) |
2514 | 0 | return -EINVAL; |
2515 | 0 |
|
2516 | 0 | ASSERT(spin_is_locked(&d->event_lock)); |
2517 | 0 |
|
2518 | 0 | emuirq = domain_pirq_to_emuirq(d, pirq); |
2519 | 0 | if ( emuirq == IRQ_UNBOUND ) |
2520 | 0 | { |
2521 | 0 | dprintk(XENLOG_G_ERR, "dom%d: pirq %d not mapped\n", |
2522 | 0 | d->domain_id, pirq); |
2523 | 0 | ret = -EINVAL; |
2524 | 0 | goto done; |
2525 | 0 | } |
2526 | 0 |
|
2527 | 0 | info = pirq_info(d, pirq); |
2528 | 0 | if ( info ) |
2529 | 0 | { |
2530 | 0 | info->arch.hvm.emuirq = IRQ_UNBOUND; |
2531 | 0 | pirq_cleanup_check(info, d); |
2532 | 0 | } |
2533 | 0 | if ( emuirq != IRQ_PT ) |
2534 | 0 | radix_tree_delete(&d->arch.hvm_domain.emuirq_pirq, emuirq); |
2535 | 0 |
|
2536 | 0 | done: |
2537 | 0 | return ret; |
2538 | 0 | } |
2539 | | |
2540 | | void arch_evtchn_bind_pirq(struct domain *d, int pirq) |
2541 | 0 | { |
2542 | 0 | int irq = domain_pirq_to_irq(d, pirq); |
2543 | 0 | struct irq_desc *desc; |
2544 | 0 | unsigned long flags; |
2545 | 0 |
|
2546 | 0 | if ( irq <= 0 ) |
2547 | 0 | return; |
2548 | 0 |
|
2549 | 0 | if ( is_hvm_domain(d) ) |
2550 | 0 | map_domain_emuirq_pirq(d, pirq, IRQ_PT); |
2551 | 0 |
|
2552 | 0 | desc = irq_to_desc(irq); |
2553 | 0 | spin_lock_irqsave(&desc->lock, flags); |
2554 | 0 | if ( desc->msi_desc ) |
2555 | 0 | guest_mask_msi_irq(desc, 0); |
2556 | 0 | spin_unlock_irqrestore(&desc->lock, flags); |
2557 | 0 | } |
2558 | | |
2559 | | bool hvm_domain_use_pirq(const struct domain *d, const struct pirq *pirq) |
2560 | 4.44k | { |
2561 | 4.44k | return is_hvm_domain(d) && pirq && pirq->arch.hvm.emuirq != IRQ_UNBOUND; |
2562 | 4.44k | } |
2563 | | |
2564 | | static int allocate_pirq(struct domain *d, int index, int pirq, int irq, |
2565 | | int type, int *nr) |
2566 | 48 | { |
2567 | 48 | int current_pirq; |
2568 | 48 | |
2569 | 48 | ASSERT(spin_is_locked(&d->event_lock)); |
2570 | 48 | current_pirq = domain_irq_to_pirq(d, irq); |
2571 | 48 | if ( pirq < 0 ) |
2572 | 42 | { |
2573 | 42 | if ( current_pirq ) |
2574 | 0 | { |
2575 | 0 | dprintk(XENLOG_G_ERR, "dom%d: %d:%d already mapped to %d\n", |
2576 | 0 | d->domain_id, index, pirq, current_pirq); |
2577 | 0 | if ( current_pirq < 0 ) |
2578 | 0 | return -EBUSY; |
2579 | 0 | } |
2580 | 42 | else if ( type == MAP_PIRQ_TYPE_MULTI_MSI ) |
2581 | 6 | { |
2582 | 6 | if ( *nr <= 0 || *nr > MAX_MSI_IRQS ) |
2583 | 0 | return -EDOM; |
2584 | 6 | if ( *nr != 1 && !iommu_intremap ) |
2585 | 0 | return -EOPNOTSUPP; |
2586 | 6 | |
2587 | 6 | while ( *nr & (*nr - 1) ) |
2588 | 0 | *nr += *nr & -*nr; |
2589 | 6 | pirq = get_free_pirqs(d, *nr); |
2590 | 6 | if ( pirq < 0 ) |
2591 | 0 | { |
2592 | 0 | while ( (*nr >>= 1) > 1 ) |
2593 | 0 | if ( get_free_pirqs(d, *nr) > 0 ) |
2594 | 0 | break; |
2595 | 0 | dprintk(XENLOG_G_ERR, "dom%d: no block of %d free pirqs\n", |
2596 | 0 | d->domain_id, *nr << 1); |
2597 | 0 | } |
2598 | 6 | } |
2599 | 42 | else |
2600 | 36 | { |
2601 | 36 | pirq = get_free_pirq(d, type); |
2602 | 36 | if ( pirq < 0 ) |
2603 | 0 | dprintk(XENLOG_G_ERR, "dom%d: no free pirq\n", d->domain_id); |
2604 | 36 | } |
2605 | 42 | } |
2606 | 6 | else if ( current_pirq && pirq != current_pirq ) |
2607 | 0 | { |
2608 | 0 | dprintk(XENLOG_G_ERR, "dom%d: irq %d already mapped to pirq %d\n", |
2609 | 0 | d->domain_id, irq, current_pirq); |
2610 | 0 | return -EEXIST; |
2611 | 0 | } |
2612 | 48 | |
2613 | 48 | return pirq; |
2614 | 48 | } |
2615 | | |
2616 | | int allocate_and_map_gsi_pirq(struct domain *d, int index, int *pirq_p) |
2617 | 6 | { |
2618 | 6 | int irq, pirq, ret; |
2619 | 6 | |
2620 | 6 | if ( index < 0 || index >= nr_irqs_gsi ) |
2621 | 0 | { |
2622 | 0 | dprintk(XENLOG_G_ERR, "dom%d: map invalid irq %d\n", d->domain_id, |
2623 | 0 | index); |
2624 | 0 | return -EINVAL; |
2625 | 0 | } |
2626 | 6 | |
2627 | 6 | irq = domain_pirq_to_irq(current->domain, index); |
2628 | 6 | if ( irq <= 0 ) |
2629 | 6 | { |
2630 | 6 | if ( is_hardware_domain(current->domain) ) |
2631 | 6 | irq = index; |
2632 | 6 | else |
2633 | 0 | { |
2634 | 0 | dprintk(XENLOG_G_ERR, "dom%d: map pirq with incorrect irq!\n", |
2635 | 0 | d->domain_id); |
2636 | 0 | return -EINVAL; |
2637 | 0 | } |
2638 | 6 | } |
2639 | 6 | |
2640 | 6 | /* Verify or get pirq. */ |
2641 | 6 | spin_lock(&d->event_lock); |
2642 | 6 | pirq = allocate_pirq(d, index, *pirq_p, irq, MAP_PIRQ_TYPE_GSI, NULL); |
2643 | 6 | if ( pirq < 0 ) |
2644 | 0 | { |
2645 | 0 | ret = pirq; |
2646 | 0 | goto done; |
2647 | 0 | } |
2648 | 6 | |
2649 | 6 | ret = map_domain_pirq(d, pirq, irq, MAP_PIRQ_TYPE_GSI, NULL); |
2650 | 6 | if ( !ret ) |
2651 | 6 | *pirq_p = pirq; |
2652 | 6 | |
2653 | 6 | done: |
2654 | 6 | spin_unlock(&d->event_lock); |
2655 | 6 | |
2656 | 6 | return ret; |
2657 | 6 | } |
2658 | | |
2659 | | int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p, |
2660 | | int type, struct msi_info *msi) |
2661 | 42 | { |
2662 | 42 | int irq, pirq, ret; |
2663 | 42 | |
2664 | 42 | switch ( type ) |
2665 | 42 | { |
2666 | 36 | case MAP_PIRQ_TYPE_MSI: |
2667 | 36 | if ( !msi->table_base ) |
2668 | 0 | msi->entry_nr = 1; |
2669 | 36 | irq = index; |
2670 | 36 | if ( irq == -1 ) |
2671 | 36 | { |
2672 | 42 | case MAP_PIRQ_TYPE_MULTI_MSI: |
2673 | 42 | irq = create_irq(NUMA_NO_NODE); |
2674 | 42 | } |
2675 | 36 | |
2676 | 42 | if ( irq < nr_irqs_gsi || irq >= nr_irqs ) |
2677 | 0 | { |
2678 | 0 | dprintk(XENLOG_G_ERR, "dom%d: can't create irq for msi!\n", |
2679 | 0 | d->domain_id); |
2680 | 0 | return -EINVAL; |
2681 | 0 | } |
2682 | 42 | |
2683 | 42 | msi->irq = irq; |
2684 | 42 | break; |
2685 | 42 | |
2686 | 0 | default: |
2687 | 0 | dprintk(XENLOG_G_ERR, "dom%d: wrong pirq type %x\n", |
2688 | 0 | d->domain_id, type); |
2689 | 0 | ASSERT_UNREACHABLE(); |
2690 | 0 | return -EINVAL; |
2691 | 42 | } |
2692 | 42 | |
2693 | 42 | msi->irq = irq; |
2694 | 42 | |
2695 | 42 | pcidevs_lock(); |
2696 | 42 | /* Verify or get pirq. */ |
2697 | 42 | spin_lock(&d->event_lock); |
2698 | 42 | pirq = allocate_pirq(d, index, *pirq_p, irq, type, &msi->entry_nr); |
2699 | 42 | if ( pirq < 0 ) |
2700 | 0 | { |
2701 | 0 | ret = pirq; |
2702 | 0 | goto done; |
2703 | 0 | } |
2704 | 42 | |
2705 | 42 | ret = map_domain_pirq(d, pirq, irq, type, msi); |
2706 | 42 | if ( !ret ) |
2707 | 42 | *pirq_p = pirq; |
2708 | 42 | |
2709 | 42 | done: |
2710 | 42 | spin_unlock(&d->event_lock); |
2711 | 42 | pcidevs_unlock(); |
2712 | 42 | if ( ret ) |
2713 | 0 | { |
2714 | 0 | switch ( type ) |
2715 | 0 | { |
2716 | 0 | case MAP_PIRQ_TYPE_MSI: |
2717 | 0 | if ( index == -1 ) |
2718 | 0 | case MAP_PIRQ_TYPE_MULTI_MSI: |
2719 | 0 | destroy_irq(irq); |
2720 | 0 | break; |
2721 | 0 | } |
2722 | 0 | } |
2723 | 42 | |
2724 | 42 | return ret; |
2725 | 42 | } |