/root/src/xen/xen/arch/x86/x86_64/mmconfig-shared.c

Source (jump to first uncovered line)
/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 *
 * Author: Allen Kay <allen.m.kay@intel.com> -  adapted to xen from Linux
 */

#include <xen/init.h>
#include <xen/mm.h>
#include <xen/acpi.h>
#include <xen/xmalloc.h>
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/pci_ids.h>
#include <asm/e820.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
#include <public/physdev.h>

#include "mmconfig.h"

unsigned int pci_probe = PCI_PROBE_CONF1 | PCI_PROBE_MMCONF;

static int __init parse_mmcfg(const char *s)
{
    const char *ss;
    int rc = 0;

    do {
        ss = strchr(s, ',');
        if ( !ss )
            ss = strchr(s, '\0');

        switch ( parse_bool(s, ss) )
        {
        case 0:
            pci_probe &= ~PCI_PROBE_MMCONF;
            break;
        case 1:
            break;
        default:
            if ( !strncmp(s, "amd_fam10", ss - s) ||
                 !strncmp(s, "amd-fam10", ss - s) )
                pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
            else
                rc = -EINVAL;
            break;
        }

        s = ss + 1;
    } while ( *ss );

    return rc;
}
custom_param("mmcfg", parse_mmcfg);

static const char __init *pci_mmcfg_e7520(void)
{
    u32 win;
    win = pci_conf_read16(0, 0, 0, 0, 0xce);

    win = win & 0xf000;
    if(win == 0x0000 || win == 0xf000)
        pci_mmcfg_config_num = 0;
    else {
        pci_mmcfg_config_num = 1;
        pci_mmcfg_config = xzalloc(struct acpi_mcfg_allocation);
        if (!pci_mmcfg_config)
            return NULL;
        pci_mmcfg_config[0].address = win << 16;
        pci_mmcfg_config[0].pci_segment = 0;
        pci_mmcfg_config[0].start_bus_number = 0;
        pci_mmcfg_config[0].end_bus_number = 255;
    }

    return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
    u32 pciexbar, mask = 0, len = 0;

    pci_mmcfg_config_num = 1;

    pciexbar = pci_conf_read32(0, 0, 0, 0, 0x48);

    /* Enable bit */
    if (!(pciexbar & 1))
        pci_mmcfg_config_num = 0;

    /* Size bits */
    switch ((pciexbar >> 1) & 3) {
    case 0:
        mask = 0xf0000000U;
        len  = 0x10000000U;
        break;
    case 1:
        mask = 0xf8000000U;
        len  = 0x08000000U;
        break;
    case 2:
        mask = 0xfc000000U;
        len  = 0x04000000U;
        break;
    default:
        pci_mmcfg_config_num = 0;
    }

    /* Errata #2, things break when not aligned on a 256Mb boundary */
    /* Can only happen in 64M/128M mode */

    if ((pciexbar & mask) & 0x0fffffffU)
        pci_mmcfg_config_num = 0;

    /* Don't hit the APIC registers and their friends */
    if ((pciexbar & mask) >= 0xf0000000U)
        pci_mmcfg_config_num = 0;

    if (pci_mmcfg_config_num) {
        pci_mmcfg_config = xzalloc(struct acpi_mcfg_allocation);
        if (!pci_mmcfg_config)
            return NULL;
        pci_mmcfg_config[0].address = pciexbar & mask;
        pci_mmcfg_config[0].pci_segment = 0;
        pci_mmcfg_config[0].start_bus_number = 0;
        pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
    }

    return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
    uint32_t address;
    uint64_t base, msr_content;
    int i;
    unsigned segnbits = 0, busnbits;

    if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
        return NULL;

    address = MSR_FAM10H_MMIO_CONF_BASE;
    if (rdmsr_safe(address, msr_content))
        return NULL;

    /* mmconfig is not enable */
    if (!(msr_content & FAM10H_MMIO_CONF_ENABLE))
        return NULL;

    base = msr_content &
        (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

    busnbits = (msr_content >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
                FAM10H_MMIO_CONF_BUSRANGE_MASK;

    /*
     * only handle bus 0 ?
     * need to skip it
     */
    if (!busnbits)
        return NULL;

    if (busnbits > 8) {
        segnbits = busnbits - 8;
        busnbits = 8;
    }

    pci_mmcfg_config_num = (1 << segnbits);
    pci_mmcfg_config = xmalloc_array(struct acpi_mcfg_allocation,
                                     pci_mmcfg_config_num);
    if (!pci_mmcfg_config)
        return NULL;

    for (i = 0; i < (1 << segnbits); i++) {
        pci_mmcfg_config[i].address = base + ((unsigned long)i << 28);
        pci_mmcfg_config[i].pci_segment = i;
        pci_mmcfg_config[i].start_bus_number = 0;
        pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
        pci_add_segment(i);
    }

    return "AMD Family 10h NB";
}

static const char __init *pci_mmcfg_nvidia_mcp55(void)
{
    static bool_t __initdata mcp55_checked;
    int bus, i;

    static const u32 extcfg_regnum      = 0x90;
    static const u32 extcfg_enable_mask = 1u << 31;
    static const u32 extcfg_start_mask  = 0xffu << 16;
    static const int extcfg_start_shift = 16;
    static const u32 extcfg_size_mask   = 3u << 28;
    static const int extcfg_size_shift  = 28;
    static const int extcfg_sizebus[]   = {0xff, 0x7f, 0x3f, 0x1f};
    static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
    static const int extcfg_base_lshift = 25;

    /* check if amd fam10h already took over */
    if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
        return NULL;

    mcp55_checked = 1;
    for (i = bus = 0; bus < 256; bus++) {
        u32 l, extcfg;
        u16 vendor, device;

        l = pci_conf_read32(0, bus, 0, 0, 0);
        vendor = l & 0xffff;
        device = (l >> 16) & 0xffff;

        if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
            continue;

        extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum);

        if (extcfg & extcfg_enable_mask)
            i++;
    }

    if (!i)
        return NULL;

    pci_mmcfg_config_num = i;
    pci_mmcfg_config = xmalloc_array(struct acpi_mcfg_allocation,
                                     pci_mmcfg_config_num);

    for (i = bus = 0; bus < 256; bus++) {
        u64 base;
        u32 l, extcfg;
        u16 vendor, device;
        int size_index;

        l = pci_conf_read32(0, bus, 0, 0, 0);
        vendor = l & 0xffff;
        device = (l >> 16) & 0xffff;

        if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
            continue;

        extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum);

        if (!(extcfg & extcfg_enable_mask))
            continue;

        if (i >= pci_mmcfg_config_num)
            break;

        size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
        base = extcfg & extcfg_base_mask[size_index];
        /* base could be > 4G */
        pci_mmcfg_config[i].address = base << extcfg_base_lshift;
        pci_mmcfg_config[i].pci_segment = 0;
        pci_mmcfg_config[i].start_bus_number =
            (extcfg & extcfg_start_mask) >> extcfg_start_shift;
        pci_mmcfg_config[i].end_bus_number =
            pci_mmcfg_config[i].start_bus_number + extcfg_sizebus[size_index];
        i++;
    }

    if (bus == 256)
        return "nVidia MCP55";

    pci_mmcfg_config_num = 0;
    xfree(pci_mmcfg_config);
    pci_mmcfg_config = NULL;

    return NULL;
}

struct pci_mmcfg_hostbridge_probe {
    u32 bus;
    u32 devfn;
    u32 vendor;
    u32 device;
    const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
    { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
      PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
    { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
      PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
    { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
      0x1200, pci_mmcfg_amd_fam10h },
    { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
      0x1200, pci_mmcfg_amd_fam10h },
    { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
      0x0369, pci_mmcfg_nvidia_mcp55 },
};

static int __init pci_mmcfg_check_hostbridge(void)
{
    u32 l;
    u32 bus, devfn;
    u16 vendor, device;
    int i;
    const char *name;

    pci_mmcfg_config_num = 0;
    pci_mmcfg_config = NULL;
    name = NULL;

    for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
        bus =  pci_mmcfg_probes[i].bus;
        devfn = pci_mmcfg_probes[i].devfn;
        l = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0);
        vendor = l & 0xffff;
        device = (l >> 16) & 0xffff;

        if (pci_mmcfg_probes[i].vendor == vendor &&
            pci_mmcfg_probes[i].device == device)
            name = pci_mmcfg_probes[i].probe();
    }

    if (name) {
        printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
            name, pci_mmcfg_config_num ? "with" : "without");
    }

    return name != NULL;
}

static int __init is_mmconf_reserved(
    u64 addr, u64 size, int i,
    typeof(pci_mmcfg_config[0]) *cfg)
{
    u64 old_size = size;
    int valid = 0;

    while (!e820_all_mapped(addr, addr + size - 1, E820_RESERVED)) {
        size >>= 1;
        if (size < (16UL<<20))
            break;
    }

    if (size >= (16UL<<20) || size == old_size) {
        printk(KERN_NOTICE "PCI: MCFG area at %lx reserved in E820\n", addr);
        valid = 1;

        if (old_size != size) {
            /* update end_bus_number */
            cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
            printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
                   "segment %hu buses %u - %u\n",
                   i, (unsigned long)cfg->address, cfg->pci_segment,
                   (unsigned int)cfg->start_bus_number,
                   (unsigned int)cfg->end_bus_number);
        }
    }

    return valid;
}

static bool_t __init pci_mmcfg_reject_broken(void)
{
    typeof(pci_mmcfg_config[0]) *cfg;
    int i;
    bool_t valid = 1;

    if ((pci_mmcfg_config_num == 0) ||
        (pci_mmcfg_config == NULL) ||
        (pci_mmcfg_config[0].address == 0))
        return 0;

    cfg = &pci_mmcfg_config[0];

    for (i = 0; i < pci_mmcfg_config_num; i++) {
        u64 addr, size;

        cfg = &pci_mmcfg_config[i];
        addr = cfg->start_bus_number;
        addr <<= 20;
        addr += cfg->address;
        size = cfg->end_bus_number + 1 - cfg->start_bus_number;
        size <<= 20;
        printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
               "segment %04x buses %02x - %02x\n",
               i, (unsigned long)cfg->address, cfg->pci_segment,
               (unsigned int)cfg->start_bus_number,
               (unsigned int)cfg->end_bus_number);

        if (!is_mmconf_reserved(addr, size, i, cfg) ||
            pci_mmcfg_arch_enable(i)) {
            pci_mmcfg_arch_disable(i);
            valid = 0;
        }
    }

    return valid;
}

void __init acpi_mmcfg_init(void)
{
    bool_t valid = 1;

    /* MMCONFIG disabled */
    if ((pci_probe & PCI_PROBE_MMCONF) == 0)
        return;

    /* MMCONFIG already enabled */
    if (!(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
        return;

    if (pci_mmcfg_check_hostbridge()) {
        unsigned int i;

        pci_mmcfg_arch_init();
        for (i = 0; i < pci_mmcfg_config_num; ++i)
            if (pci_mmcfg_arch_enable(i))
                valid = 0;
    } else {
        acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
        pci_mmcfg_arch_init();
        valid = pci_mmcfg_reject_broken();
    }

    if ((pci_mmcfg_config_num == 0) ||
        (pci_mmcfg_config == NULL) ||
        (pci_mmcfg_config[0].address == 0))
        return;

    if (valid)
        pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
}

int pci_mmcfg_reserved(uint64_t address, unsigned int segment,
                       unsigned int start_bus, unsigned int end_bus,
                       unsigned int flags)
{
    unsigned int i;

    if (flags & ~XEN_PCI_MMCFG_RESERVED)
        return -EINVAL;

    for (i = 0; i < pci_mmcfg_config_num; ++i) {
        const typeof(pci_mmcfg_config[0]) *cfg = &pci_mmcfg_config[i];

        if (cfg->pci_segment == segment &&
            cfg->start_bus_number == start_bus &&
            cfg->end_bus_number == end_bus) {
            if (cfg->address != address) {
                printk(KERN_WARNING
                       "Base address presented for segment %04x bus %02x-%02x"
                       " (%08" PRIx64 ") does not match previously obtained"
                       " one (%08" PRIx64 ")\n",
                       segment, start_bus, end_bus, address, cfg->address);
                return -EIO;
            }
            if (flags & XEN_PCI_MMCFG_RESERVED)
                return pci_mmcfg_arch_enable(i);
            pci_mmcfg_arch_disable(i);
            return 0;
        }
    }

    return -ENODEV;
}

Coverage Report

Created: 2017-10-25 09:10

Line	Count	Source (jump to first uncovered line)
1		/*
2		* mmconfig-shared.c - Low-level direct PCI config space access via
3		* MMCONFIG - common code between i386 and x86-64.
4		*
5		* This code does:
6		* - known chipset handling
7		* - ACPI decoding and validation
8		*
9		* Per-architecture code takes care of the mappings and accesses
10		* themselves.
11		*
12		* Author: Allen Kay <allen.m.kay@intel.com> - adapted to xen from Linux
13		*/
14
15		#include <xen/init.h>
16		#include <xen/mm.h>
17		#include <xen/acpi.h>
18		#include <xen/xmalloc.h>
19		#include <xen/pci.h>
20		#include <xen/pci_regs.h>
21		#include <xen/pci_ids.h>
22		#include <asm/e820.h>
23		#include <asm/msr.h>
24		#include <asm/msr-index.h>
25		#include <public/physdev.h>
26
27		#include "mmconfig.h"
28
29		unsigned int pci_probe = PCI_PROBE_CONF1 \| PCI_PROBE_MMCONF;
30
31		static int __init parse_mmcfg(const char *s)
32	0	{
33	0	const char *ss;
34	0	int rc = 0;
35	0
36	0	do {
37	0	ss = strchr(s, ',');
38	0	if ( !ss )
39	0	ss = strchr(s, '\0');
40	0
41	0	switch ( parse_bool(s, ss) )
42	0	{
43	0	case 0:
44	0	pci_probe &= ~PCI_PROBE_MMCONF;
45	0	break;
46	0	case 1:
47	0	break;
48	0	default:
49	0	if ( !strncmp(s, "amd_fam10", ss - s) \|\|
50	0	!strncmp(s, "amd-fam10", ss - s) )
51	0	pci_probe \|= PCI_CHECK_ENABLE_AMD_MMCONF;
52	0	else
53	0	rc = -EINVAL;
54	0	break;
55	0	}
56	0
57	0	s = ss + 1;
58	0	} while ( *ss );
59	0
60	0	return rc;
61	0	}
62		custom_param("mmcfg", parse_mmcfg);
63
64		static const char __init *pci_mmcfg_e7520(void)
65	0	{
66	0	u32 win;
67	0	win = pci_conf_read16(0, 0, 0, 0, 0xce);
68	0
69	0	win = win & 0xf000;
70	0	if(win == 0x0000 \|\| win == 0xf000)
71	0	pci_mmcfg_config_num = 0;
72	0	else {
73	0	pci_mmcfg_config_num = 1;
74	0	pci_mmcfg_config = xzalloc(struct acpi_mcfg_allocation);
75	0	if (!pci_mmcfg_config)
76	0	return NULL;
77	0	pci_mmcfg_config[0].address = win << 16;
78	0	pci_mmcfg_config[0].pci_segment = 0;
79	0	pci_mmcfg_config[0].start_bus_number = 0;
80	0	pci_mmcfg_config[0].end_bus_number = 255;
81	0	}
82	0
83	0	return "Intel Corporation E7520 Memory Controller Hub";
84	0	}
85
86		static const char __init *pci_mmcfg_intel_945(void)
87	0	{
88	0	u32 pciexbar, mask = 0, len = 0;
89	0
90	0	pci_mmcfg_config_num = 1;
91	0
92	0	pciexbar = pci_conf_read32(0, 0, 0, 0, 0x48);
93	0
94	0	/* Enable bit */
95	0	if (!(pciexbar & 1))
96	0	pci_mmcfg_config_num = 0;
97	0
98	0	/* Size bits */
99	0	switch ((pciexbar >> 1) & 3) {
100	0	case 0:
101	0	mask = 0xf0000000U;
102	0	len = 0x10000000U;
103	0	break;
104	0	case 1:
105	0	mask = 0xf8000000U;
106	0	len = 0x08000000U;
107	0	break;
108	0	case 2:
109	0	mask = 0xfc000000U;
110	0	len = 0x04000000U;
111	0	break;
112	0	default:
113	0	pci_mmcfg_config_num = 0;
114	0	}
115	0
116	0	/* Errata #2, things break when not aligned on a 256Mb boundary */
117	0	/* Can only happen in 64M/128M mode */
118	0
119	0	if ((pciexbar & mask) & 0x0fffffffU)
120	0	pci_mmcfg_config_num = 0;
121	0
122	0	/* Don't hit the APIC registers and their friends */
123	0	if ((pciexbar & mask) >= 0xf0000000U)
124	0	pci_mmcfg_config_num = 0;
125	0
126	0	if (pci_mmcfg_config_num) {
127	0	pci_mmcfg_config = xzalloc(struct acpi_mcfg_allocation);
128	0	if (!pci_mmcfg_config)
129	0	return NULL;
130	0	pci_mmcfg_config[0].address = pciexbar & mask;
131	0	pci_mmcfg_config[0].pci_segment = 0;
132	0	pci_mmcfg_config[0].start_bus_number = 0;
133	0	pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
134	0	}
135	0
136	0	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
137	0	}
138
139		static const char __init *pci_mmcfg_amd_fam10h(void)
140	0	{
141	0	uint32_t address;
142	0	uint64_t base, msr_content;
143	0	int i;
144	0	unsigned segnbits = 0, busnbits;
145	0
146	0	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
147	0	return NULL;
148	0
149	0	address = MSR_FAM10H_MMIO_CONF_BASE;
150	0	if (rdmsr_safe(address, msr_content))
151	0	return NULL;
152	0
153	0	/* mmconfig is not enable */
154	0	if (!(msr_content & FAM10H_MMIO_CONF_ENABLE))
155	0	return NULL;
156	0
157	0	base = msr_content &
158	0	(FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
159	0
160	0	busnbits = (msr_content >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
161	0	FAM10H_MMIO_CONF_BUSRANGE_MASK;
162	0
163	0	/*
164	0	* only handle bus 0 ?
165	0	* need to skip it
166	0	*/
167	0	if (!busnbits)
168	0	return NULL;
169	0
170	0	if (busnbits > 8) {
171	0	segnbits = busnbits - 8;
172	0	busnbits = 8;
173	0	}
174	0
175	0	pci_mmcfg_config_num = (1 << segnbits);
176	0	pci_mmcfg_config = xmalloc_array(struct acpi_mcfg_allocation,
177	0	pci_mmcfg_config_num);
178	0	if (!pci_mmcfg_config)
179	0	return NULL;
180	0
181	0	for (i = 0; i < (1 << segnbits); i++) {
182	0	pci_mmcfg_config[i].address = base + ((unsigned long)i << 28);
183	0	pci_mmcfg_config[i].pci_segment = i;
184	0	pci_mmcfg_config[i].start_bus_number = 0;
185	0	pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
186	0	pci_add_segment(i);
187	0	}
188	0
189	0	return "AMD Family 10h NB";
190	0	}
191
192		static const char __init *pci_mmcfg_nvidia_mcp55(void)
193	0	{
194	0	static bool_t __initdata mcp55_checked;
195	0	int bus, i;
196	0
197	0	static const u32 extcfg_regnum = 0x90;
198	0	static const u32 extcfg_enable_mask = 1u << 31;
199	0	static const u32 extcfg_start_mask = 0xffu << 16;
200	0	static const int extcfg_start_shift = 16;
201	0	static const u32 extcfg_size_mask = 3u << 28;
202	0	static const int extcfg_size_shift = 28;
203	0	static const int extcfg_sizebus[] = {0xff, 0x7f, 0x3f, 0x1f};
204	0	static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
205	0	static const int extcfg_base_lshift = 25;
206	0
207	0	/* check if amd fam10h already took over */
208	0	if (!acpi_disabled \|\| pci_mmcfg_config_num \|\| mcp55_checked)
209	0	return NULL;
210	0
211	0	mcp55_checked = 1;
212	0	for (i = bus = 0; bus < 256; bus++) {
213	0	u32 l, extcfg;
214	0	u16 vendor, device;
215	0
216	0	l = pci_conf_read32(0, bus, 0, 0, 0);
217	0	vendor = l & 0xffff;
218	0	device = (l >> 16) & 0xffff;
219	0
220	0	if (PCI_VENDOR_ID_NVIDIA != vendor \|\| 0x0369 != device)
221	0	continue;
222	0
223	0	extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum);
224	0
225	0	if (extcfg & extcfg_enable_mask)
226	0	i++;
227	0	}
228	0
229	0	if (!i)
230	0	return NULL;
231	0
232	0	pci_mmcfg_config_num = i;
233	0	pci_mmcfg_config = xmalloc_array(struct acpi_mcfg_allocation,
234	0	pci_mmcfg_config_num);
235	0
236	0	for (i = bus = 0; bus < 256; bus++) {
237	0	u64 base;
238	0	u32 l, extcfg;
239	0	u16 vendor, device;
240	0	int size_index;
241	0
242	0	l = pci_conf_read32(0, bus, 0, 0, 0);
243	0	vendor = l & 0xffff;
244	0	device = (l >> 16) & 0xffff;
245	0
246	0	if (PCI_VENDOR_ID_NVIDIA != vendor \|\| 0x0369 != device)
247	0	continue;
248	0
249	0	extcfg = pci_conf_read32(0, bus, 0, 0, extcfg_regnum);
250	0
251	0	if (!(extcfg & extcfg_enable_mask))
252	0	continue;
253	0
254	0	if (i >= pci_mmcfg_config_num)
255	0	break;
256	0
257	0	size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
258	0	base = extcfg & extcfg_base_mask[size_index];
259	0	/* base could be > 4G */
260	0	pci_mmcfg_config[i].address = base << extcfg_base_lshift;
261	0	pci_mmcfg_config[i].pci_segment = 0;
262	0	pci_mmcfg_config[i].start_bus_number =
263	0	(extcfg & extcfg_start_mask) >> extcfg_start_shift;
264	0	pci_mmcfg_config[i].end_bus_number =
265	0	pci_mmcfg_config[i].start_bus_number + extcfg_sizebus[size_index];
266	0	i++;
267	0	}
268	0
269	0	if (bus == 256)
270	0	return "nVidia MCP55";
271	0
272	0	pci_mmcfg_config_num = 0;
273	0	xfree(pci_mmcfg_config);
274	0	pci_mmcfg_config = NULL;
275	0
276	0	return NULL;
277	0	}
278
279		struct pci_mmcfg_hostbridge_probe {
280		u32 bus;
281		u32 devfn;
282		u32 vendor;
283		u32 device;
284		const char (probe)(void);
285		};
286
287		static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
288		{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
289		PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
290		{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
291		PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
292		{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
293		0x1200, pci_mmcfg_amd_fam10h },
294		{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
295		0x1200, pci_mmcfg_amd_fam10h },
296		{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
297		0x0369, pci_mmcfg_nvidia_mcp55 },
298		};
299
300		static int __init pci_mmcfg_check_hostbridge(void)
301	1	{
302	1	u32 l;
303	1	u32 bus, devfn;
304	1	u16 vendor, device;
305	1	int i;
306	1	const char *name;
307	1
308	1	pci_mmcfg_config_num = 0;
309	1	pci_mmcfg_config = NULL;
310	1	name = NULL;
311	1
312	6	for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
313	5	bus = pci_mmcfg_probes[i].bus;
314	5	devfn = pci_mmcfg_probes[i].devfn;
315	5	l = pci_conf_read32(0, bus, PCI_SLOT(devfn), PCI_FUNC(devfn), 0);
316	5	vendor = l & 0xffff;
317	5	device = (l >> 16) & 0xffff;
318	5
319	5	if (pci_mmcfg_probes[i].vendor == vendor &&
320	2	pci_mmcfg_probes[i].device == device)
321	0	name = pci_mmcfg_probes[i].probe();
322	5	}
323	1
324	1	if (name) {
325	0	printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
326	0	name, pci_mmcfg_config_num ? "with" : "without");
327	0	}
328	1
329	1	return name != NULL;
330	1	}
331
332		static int __init is_mmconf_reserved(
333		u64 addr, u64 size, int i,
334		typeof(pci_mmcfg_config[0]) *cfg)
335	1	{
336	1	u64 old_size = size;
337	1	int valid = 0;
338	1
339	1	while (!e820_all_mapped(addr, addr + size - 1, E820_RESERVED)) {
340	0	size >>= 1;
341	0	if (size < (16UL<<20))
342	0	break;
343	0	}
344	1
345	1	if (size >= (16UL<<20) \|\| size == old_size) {
346	1	printk(KERN_NOTICE "PCI: MCFG area at %lx reserved in E820\n", addr);
347	1	valid = 1;
348	1
349	1	if (old_size != size) {
350	0	/* update end_bus_number */
351	0	cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
352	0	printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
353	0	"segment %hu buses %u - %u\n",
354	0	i, (unsigned long)cfg->address, cfg->pci_segment,
355	0	(unsigned int)cfg->start_bus_number,
356	0	(unsigned int)cfg->end_bus_number);
357	0	}
358	1	}
359	1
360	1	return valid;
361	1	}
362
363		static bool_t __init pci_mmcfg_reject_broken(void)
364	1	{
365	1	typeof(pci_mmcfg_config[0]) *cfg;
366	1	int i;
367	1	bool_t valid = 1;
368	1
369	1	if ((pci_mmcfg_config_num == 0) \|\|
370	1	(pci_mmcfg_config == NULL) \|\|
371	1	(pci_mmcfg_config[0].address == 0))
372	0	return 0;
373	1
374	1	cfg = &pci_mmcfg_config[0];
375	1
376	2	for (i = 0; i < pci_mmcfg_config_num; i++) {
377	1	u64 addr, size;
378	1
379	1	cfg = &pci_mmcfg_config[i];
380	1	addr = cfg->start_bus_number;
381	1	addr <<= 20;
382	1	addr += cfg->address;
383	1	size = cfg->end_bus_number + 1 - cfg->start_bus_number;
384	1	size <<= 20;
385	1	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
386	1	"segment %04x buses %02x - %02x\n",
387	1	i, (unsigned long)cfg->address, cfg->pci_segment,
388	1	(unsigned int)cfg->start_bus_number,
389	1	(unsigned int)cfg->end_bus_number);
390	1
391	1	if (!is_mmconf_reserved(addr, size, i, cfg) \|\|
392	1	pci_mmcfg_arch_enable(i)) {
393	0	pci_mmcfg_arch_disable(i);
394	0	valid = 0;
395	0	}
396	1	}
397	1
398	1	return valid;
399	1	}
400
401		void __init acpi_mmcfg_init(void)
402	1	{
403	1	bool_t valid = 1;
404	1
405	1	/* MMCONFIG disabled */
406	1	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
407	0	return;
408	1
409	1	/* MMCONFIG already enabled */
410	1	if (!(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
411	0	return;
412	1
413	1	if (pci_mmcfg_check_hostbridge()) {
414	0	unsigned int i;
415	0
416	0	pci_mmcfg_arch_init();
417	0	for (i = 0; i < pci_mmcfg_config_num; ++i)
418	0	if (pci_mmcfg_arch_enable(i))
419	0	valid = 0;
420	1	} else {
421	1	acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
422	1	pci_mmcfg_arch_init();
423	1	valid = pci_mmcfg_reject_broken();
424	1	}
425	1
426	1	if ((pci_mmcfg_config_num == 0) \|\|
427	1	(pci_mmcfg_config == NULL) \|\|
428	1	(pci_mmcfg_config[0].address == 0))
429	0	return;
430	1
431	1	if (valid)
432	1	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
433	1	}
434
435		int pci_mmcfg_reserved(uint64_t address, unsigned int segment,
436		unsigned int start_bus, unsigned int end_bus,
437		unsigned int flags)
438	0	{
439	0	unsigned int i;
440	0
441	0	if (flags & ~XEN_PCI_MMCFG_RESERVED)
442	0	return -EINVAL;
443	0
444	0	for (i = 0; i < pci_mmcfg_config_num; ++i) {
445	0	const typeof(pci_mmcfg_config[0]) *cfg = &pci_mmcfg_config[i];
446	0
447	0	if (cfg->pci_segment == segment &&
448	0	cfg->start_bus_number == start_bus &&
449	0	cfg->end_bus_number == end_bus) {
450	0	if (cfg->address != address) {
451	0	printk(KERN_WARNING
452	0	"Base address presented for segment %04x bus %02x-%02x"
453	0	" (%08" PRIx64 ") does not match previously obtained"
454	0	" one (%08" PRIx64 ")\n",
455	0	segment, start_bus, end_bus, address, cfg->address);
456	0	return -EIO;
457	0	}
458	0	if (flags & XEN_PCI_MMCFG_RESERVED)
459	0	return pci_mmcfg_arch_enable(i);
460	0	pci_mmcfg_arch_disable(i);
461	0	return 0;
462	0	}
463	0	}
464	0
465	0	return -ENODEV;
466	0	}