/root/src/xen/xen/drivers/char/ns16550.c
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1 | | /****************************************************************************** |
2 | | * ns16550.c |
3 | | * |
4 | | * Driver for 16550-series UARTs. This driver is to be kept within Xen as |
5 | | * it permits debugging of seriously-toasted machines (e.g., in situations |
6 | | * where a device driver within a guest OS would be inaccessible). |
7 | | * |
8 | | * Copyright (c) 2003-2005, K A Fraser |
9 | | */ |
10 | | |
11 | | #include <xen/console.h> |
12 | | #include <xen/init.h> |
13 | | #include <xen/irq.h> |
14 | | #include <xen/sched.h> |
15 | | #include <xen/timer.h> |
16 | | #include <xen/serial.h> |
17 | | #include <xen/iocap.h> |
18 | | #ifdef CONFIG_HAS_PCI |
19 | | #include <xen/pci.h> |
20 | | #include <xen/pci_regs.h> |
21 | | #include <xen/pci_ids.h> |
22 | | #endif |
23 | | #include <xen/8250-uart.h> |
24 | | #include <xen/vmap.h> |
25 | | #include <asm/io.h> |
26 | | #ifdef CONFIG_HAS_DEVICE_TREE |
27 | | #include <asm/device.h> |
28 | | #endif |
29 | | #ifdef CONFIG_X86 |
30 | | #include <asm/fixmap.h> |
31 | | #endif |
32 | | |
33 | | /* |
34 | | * Configure serial port with a string: |
35 | | * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]]. |
36 | | * The tail of the string can be omitted if platform defaults are sufficient. |
37 | | * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto' |
38 | | * can be specified in place of a numeric baud rate. Polled mode is specified |
39 | | * by requesting irq 0. |
40 | | */ |
41 | | static char __initdata opt_com1[128] = ""; |
42 | | static char __initdata opt_com2[128] = ""; |
43 | | string_param("com1", opt_com1); |
44 | | string_param("com2", opt_com2); |
45 | | |
46 | | enum serial_param_type { |
47 | | baud, |
48 | | clock_hz, |
49 | | data_bits, |
50 | | io_base, |
51 | | irq, |
52 | | parity, |
53 | | reg_shift, |
54 | | reg_width, |
55 | | stop_bits, |
56 | | #ifdef CONFIG_HAS_PCI |
57 | | bridge_bdf, |
58 | | device, |
59 | | port_bdf, |
60 | | #endif |
61 | | /* List all parameters before this line. */ |
62 | | num_serial_params |
63 | | }; |
64 | | |
65 | | static struct ns16550 { |
66 | | int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq; |
67 | | u64 io_base; /* I/O port or memory-mapped I/O address. */ |
68 | | u64 io_size; |
69 | | int reg_shift; /* Bits to shift register offset by */ |
70 | | int reg_width; /* Size of access to use, the registers |
71 | | * themselves are still bytes */ |
72 | | char __iomem *remapped_io_base; /* Remapped virtual address of MMIO. */ |
73 | | /* UART with IRQ line: interrupt-driven I/O. */ |
74 | | struct irqaction irqaction; |
75 | | u8 lsr_mask; |
76 | | #ifdef CONFIG_ARM |
77 | | struct vuart_info vuart; |
78 | | #endif |
79 | | /* UART with no IRQ line: periodically-polled I/O. */ |
80 | | struct timer timer; |
81 | | struct timer resume_timer; |
82 | | unsigned int timeout_ms; |
83 | | bool_t intr_works; |
84 | | bool_t dw_usr_bsy; |
85 | | #ifdef CONFIG_HAS_PCI |
86 | | /* PCI card parameters. */ |
87 | | bool_t pb_bdf_enable; /* if =1, pb-bdf effective, port behind bridge */ |
88 | | bool_t ps_bdf_enable; /* if =1, ps_bdf effective, port on pci card */ |
89 | | unsigned int pb_bdf[3]; /* pci bridge BDF */ |
90 | | unsigned int ps_bdf[3]; /* pci serial port BDF */ |
91 | | u32 bar; |
92 | | u32 bar64; |
93 | | u16 cr; |
94 | | u8 bar_idx; |
95 | | const struct ns16550_config_param *param; /* Points into .init.*! */ |
96 | | #endif |
97 | | } ns16550_com[2] = { { 0 } }; |
98 | | |
99 | | struct serial_param_var { |
100 | | char name[12]; |
101 | | enum serial_param_type type; |
102 | | }; |
103 | | |
104 | | /* |
105 | | * Enum struct keeping a table of all accepted parameter names for parsing |
106 | | * com_console_options for serial port com1 and com2. |
107 | | */ |
108 | | static const struct serial_param_var __initconst sp_vars[] = { |
109 | | {"baud", baud}, |
110 | | {"clock-hz", clock_hz}, |
111 | | {"data-bits", data_bits}, |
112 | | {"io-base", io_base}, |
113 | | {"irq", irq}, |
114 | | {"parity", parity}, |
115 | | {"reg-shift", reg_shift}, |
116 | | {"reg-width", reg_width}, |
117 | | {"stop-bits", stop_bits}, |
118 | | #ifdef CONFIG_HAS_PCI |
119 | | {"bridge", bridge_bdf}, |
120 | | {"dev", device}, |
121 | | {"port", port_bdf}, |
122 | | #endif |
123 | | }; |
124 | | |
125 | | #ifdef CONFIG_HAS_PCI |
126 | | struct ns16550_config { |
127 | | u16 vendor_id; |
128 | | u16 dev_id; |
129 | | enum { |
130 | | param_default, /* Must not be referenced by any table entry. */ |
131 | | param_trumanage, |
132 | | param_oxford, |
133 | | param_oxford_2port, |
134 | | param_pericom_1port, |
135 | | param_pericom_2port, |
136 | | param_pericom_4port, |
137 | | param_pericom_8port, |
138 | | } param; |
139 | | }; |
140 | | |
141 | | /* Defining uart config options for MMIO devices */ |
142 | | struct ns16550_config_param { |
143 | | unsigned int reg_shift; |
144 | | unsigned int reg_width; |
145 | | unsigned int fifo_size; |
146 | | u8 lsr_mask; |
147 | | bool_t mmio; |
148 | | bool_t bar0; |
149 | | unsigned int max_ports; |
150 | | unsigned int base_baud; |
151 | | unsigned int uart_offset; |
152 | | unsigned int first_offset; |
153 | | }; |
154 | | |
155 | | /* |
156 | | * Create lookup tables for specific devices. It is assumed that if |
157 | | * the device found is MMIO, then you have indexed it here. Else, the |
158 | | * driver does nothing for MMIO based devices. |
159 | | */ |
160 | | static const struct ns16550_config_param __initconst uart_param[] = { |
161 | | [param_default] = { |
162 | | .reg_width = 1, |
163 | | .lsr_mask = UART_LSR_THRE, |
164 | | .max_ports = 1, |
165 | | }, |
166 | | [param_trumanage] = { |
167 | | .reg_shift = 2, |
168 | | .reg_width = 1, |
169 | | .fifo_size = 16, |
170 | | .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT), |
171 | | .mmio = 1, |
172 | | .max_ports = 1, |
173 | | }, |
174 | | [param_oxford] = { |
175 | | .base_baud = 4000000, |
176 | | .uart_offset = 0x200, |
177 | | .first_offset = 0x1000, |
178 | | .reg_width = 1, |
179 | | .fifo_size = 16, |
180 | | .lsr_mask = UART_LSR_THRE, |
181 | | .mmio = 1, |
182 | | .max_ports = 1, /* It can do more, but we would need more custom code.*/ |
183 | | }, |
184 | | [param_oxford_2port] = { |
185 | | .base_baud = 4000000, |
186 | | .uart_offset = 0x200, |
187 | | .first_offset = 0x1000, |
188 | | .reg_width = 1, |
189 | | .fifo_size = 16, |
190 | | .lsr_mask = UART_LSR_THRE, |
191 | | .mmio = 1, |
192 | | .max_ports = 2, |
193 | | }, |
194 | | [param_pericom_1port] = { |
195 | | .base_baud = 921600, |
196 | | .uart_offset = 8, |
197 | | .reg_width = 1, |
198 | | .fifo_size = 16, |
199 | | .lsr_mask = UART_LSR_THRE, |
200 | | .bar0 = 1, |
201 | | .max_ports = 1, |
202 | | }, |
203 | | [param_pericom_2port] = { |
204 | | .base_baud = 921600, |
205 | | .uart_offset = 8, |
206 | | .reg_width = 1, |
207 | | .fifo_size = 16, |
208 | | .lsr_mask = UART_LSR_THRE, |
209 | | .bar0 = 1, |
210 | | .max_ports = 2, |
211 | | }, |
212 | | /* |
213 | | * Of the two following ones, we can't really use all of their ports, |
214 | | * unless ns16550_com[] would get grown. |
215 | | */ |
216 | | [param_pericom_4port] = { |
217 | | .base_baud = 921600, |
218 | | .uart_offset = 8, |
219 | | .reg_width = 1, |
220 | | .fifo_size = 16, |
221 | | .lsr_mask = UART_LSR_THRE, |
222 | | .bar0 = 1, |
223 | | .max_ports = 4, |
224 | | }, |
225 | | [param_pericom_8port] = { |
226 | | .base_baud = 921600, |
227 | | .uart_offset = 8, |
228 | | .reg_width = 1, |
229 | | .fifo_size = 16, |
230 | | .lsr_mask = UART_LSR_THRE, |
231 | | .bar0 = 1, |
232 | | .max_ports = 8, |
233 | | } |
234 | | }; |
235 | | static const struct ns16550_config __initconst uart_config[] = |
236 | | { |
237 | | /* Broadcom TruManage device */ |
238 | | { |
239 | | .vendor_id = PCI_VENDOR_ID_BROADCOM, |
240 | | .dev_id = 0x160a, |
241 | | .param = param_trumanage, |
242 | | }, |
243 | | /* OXPCIe952 1 Native UART */ |
244 | | { |
245 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
246 | | .dev_id = 0xc11b, |
247 | | .param = param_oxford, |
248 | | }, |
249 | | /* OXPCIe952 1 Native UART */ |
250 | | { |
251 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
252 | | .dev_id = 0xc11f, |
253 | | .param = param_oxford, |
254 | | }, |
255 | | /* OXPCIe952 1 Native UART */ |
256 | | { |
257 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
258 | | .dev_id = 0xc138, |
259 | | .param = param_oxford, |
260 | | }, |
261 | | /* OXPCIe952 2 Native UART */ |
262 | | { |
263 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
264 | | .dev_id = 0xc158, |
265 | | .param = param_oxford_2port, |
266 | | }, |
267 | | /* OXPCIe952 1 Native UART */ |
268 | | { |
269 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
270 | | .dev_id = 0xc13d, |
271 | | .param = param_oxford, |
272 | | }, |
273 | | /* OXPCIe952 2 Native UART */ |
274 | | { |
275 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
276 | | .dev_id = 0xc15d, |
277 | | .param = param_oxford_2port, |
278 | | }, |
279 | | /* OXPCIe952 1 Native UART */ |
280 | | { |
281 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
282 | | .dev_id = 0xc40b, |
283 | | .param = param_oxford, |
284 | | }, |
285 | | /* OXPCIe200 1 Native UART */ |
286 | | { |
287 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
288 | | .dev_id = 0xc40f, |
289 | | .param = param_oxford, |
290 | | }, |
291 | | /* OXPCIe200 1 Native UART */ |
292 | | { |
293 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
294 | | .dev_id = 0xc41b, |
295 | | .param = param_oxford, |
296 | | }, |
297 | | /* OXPCIe200 1 Native UART */ |
298 | | { |
299 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
300 | | .dev_id = 0xc41f, |
301 | | .param = param_oxford, |
302 | | }, |
303 | | /* OXPCIe200 1 Native UART */ |
304 | | { |
305 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
306 | | .dev_id = 0xc42b, |
307 | | .param = param_oxford, |
308 | | }, |
309 | | /* OXPCIe200 1 Native UART */ |
310 | | { |
311 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
312 | | .dev_id = 0xc42f, |
313 | | .param = param_oxford, |
314 | | }, |
315 | | /* OXPCIe200 1 Native UART */ |
316 | | { |
317 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
318 | | .dev_id = 0xc43b, |
319 | | .param = param_oxford, |
320 | | }, |
321 | | /* OXPCIe200 1 Native UART */ |
322 | | { |
323 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
324 | | .dev_id = 0xc43f, |
325 | | .param = param_oxford, |
326 | | }, |
327 | | /* OXPCIe200 1 Native UART */ |
328 | | { |
329 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
330 | | .dev_id = 0xc44b, |
331 | | .param = param_oxford, |
332 | | }, |
333 | | /* OXPCIe200 1 Native UART */ |
334 | | { |
335 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
336 | | .dev_id = 0xc44f, |
337 | | .param = param_oxford, |
338 | | }, |
339 | | /* OXPCIe200 1 Native UART */ |
340 | | { |
341 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
342 | | .dev_id = 0xc45b, |
343 | | .param = param_oxford, |
344 | | }, |
345 | | /* OXPCIe200 1 Native UART */ |
346 | | { |
347 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
348 | | .dev_id = 0xc45f, |
349 | | .param = param_oxford, |
350 | | }, |
351 | | /* OXPCIe200 1 Native UART */ |
352 | | { |
353 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
354 | | .dev_id = 0xc46b, |
355 | | .param = param_oxford, |
356 | | }, |
357 | | /* OXPCIe200 1 Native UART */ |
358 | | { |
359 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
360 | | .dev_id = 0xc46f, |
361 | | .param = param_oxford, |
362 | | }, |
363 | | /* OXPCIe200 1 Native UART */ |
364 | | { |
365 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
366 | | .dev_id = 0xc47b, |
367 | | .param = param_oxford, |
368 | | }, |
369 | | /* OXPCIe200 1 Native UART */ |
370 | | { |
371 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
372 | | .dev_id = 0xc47f, |
373 | | .param = param_oxford, |
374 | | }, |
375 | | /* OXPCIe200 1 Native UART */ |
376 | | { |
377 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
378 | | .dev_id = 0xc48b, |
379 | | .param = param_oxford, |
380 | | }, |
381 | | /* OXPCIe200 1 Native UART */ |
382 | | { |
383 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
384 | | .dev_id = 0xc48f, |
385 | | .param = param_oxford, |
386 | | }, |
387 | | /* OXPCIe200 1 Native UART */ |
388 | | { |
389 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
390 | | .dev_id = 0xc49b, |
391 | | .param = param_oxford, |
392 | | }, |
393 | | /* OXPCIe200 1 Native UART */ |
394 | | { |
395 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
396 | | .dev_id = 0xc49f, |
397 | | .param = param_oxford, |
398 | | }, |
399 | | /* OXPCIe200 1 Native UART */ |
400 | | { |
401 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
402 | | .dev_id = 0xc4ab, |
403 | | .param = param_oxford, |
404 | | }, |
405 | | /* OXPCIe200 1 Native UART */ |
406 | | { |
407 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
408 | | .dev_id = 0xc4af, |
409 | | .param = param_oxford, |
410 | | }, |
411 | | /* OXPCIe200 1 Native UART */ |
412 | | { |
413 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
414 | | .dev_id = 0xc4bb, |
415 | | .param = param_oxford, |
416 | | }, |
417 | | /* OXPCIe200 1 Native UART */ |
418 | | { |
419 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
420 | | .dev_id = 0xc4bf, |
421 | | .param = param_oxford, |
422 | | }, |
423 | | /* OXPCIe200 1 Native UART */ |
424 | | { |
425 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
426 | | .dev_id = 0xc4cb, |
427 | | .param = param_oxford, |
428 | | }, |
429 | | /* OXPCIe200 1 Native UART */ |
430 | | { |
431 | | .vendor_id = PCI_VENDOR_ID_OXSEMI, |
432 | | .dev_id = 0xc4cf, |
433 | | .param = param_oxford, |
434 | | }, |
435 | | /* Pericom PI7C9X7951 Uno UART */ |
436 | | { |
437 | | .vendor_id = PCI_VENDOR_ID_PERICOM, |
438 | | .dev_id = 0x7951, |
439 | | .param = param_pericom_1port |
440 | | }, |
441 | | /* Pericom PI7C9X7952 Duo UART */ |
442 | | { |
443 | | .vendor_id = PCI_VENDOR_ID_PERICOM, |
444 | | .dev_id = 0x7952, |
445 | | .param = param_pericom_2port |
446 | | }, |
447 | | /* Pericom PI7C9X7954 Quad UART */ |
448 | | { |
449 | | .vendor_id = PCI_VENDOR_ID_PERICOM, |
450 | | .dev_id = 0x7954, |
451 | | .param = param_pericom_4port |
452 | | }, |
453 | | /* Pericom PI7C9X7958 Octal UART */ |
454 | | { |
455 | | .vendor_id = PCI_VENDOR_ID_PERICOM, |
456 | | .dev_id = 0x7958, |
457 | | .param = param_pericom_8port |
458 | | } |
459 | | }; |
460 | | #endif |
461 | | |
462 | | static void ns16550_delayed_resume(void *data); |
463 | | |
464 | | static u8 ns_read_reg(struct ns16550 *uart, unsigned int reg) |
465 | 7.00M | { |
466 | 7.00M | void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift); |
467 | 7.00M | #ifdef CONFIG_HAS_IOPORTS |
468 | 7.00M | if ( uart->remapped_io_base == NULL ) |
469 | 7.00M | return inb(uart->io_base + reg); |
470 | 7.00M | #endif |
471 | 2 | switch ( uart->reg_width ) |
472 | 2 | { |
473 | 0 | case 1: |
474 | 0 | return readb(addr); |
475 | 0 | case 4: |
476 | 0 | return readl(addr); |
477 | 0 | default: |
478 | 0 | return 0xff; |
479 | 2 | } |
480 | 2 | } |
481 | | |
482 | | static void ns_write_reg(struct ns16550 *uart, unsigned int reg, u8 c) |
483 | 151k | { |
484 | 151k | void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift); |
485 | 151k | #ifdef CONFIG_HAS_IOPORTS |
486 | 151k | if ( uart->remapped_io_base == NULL ) |
487 | 151k | return outb(c, uart->io_base + reg); |
488 | 151k | #endif |
489 | 0 | switch ( uart->reg_width ) |
490 | 0 | { |
491 | 0 | case 1: |
492 | 0 | writeb(c, addr); |
493 | 0 | break; |
494 | 0 | case 4: |
495 | 0 | writel(c, addr); |
496 | 0 | break; |
497 | 0 | default: |
498 | 0 | /* Ignored */ |
499 | 0 | break; |
500 | 0 | } |
501 | 0 | } |
502 | | |
503 | | static int ns16550_ioport_invalid(struct ns16550 *uart) |
504 | 3.41M | { |
505 | 3.41M | return ns_read_reg(uart, UART_IER) == 0xff; |
506 | 3.41M | } |
507 | | |
508 | | static void handle_dw_usr_busy_quirk(struct ns16550 *uart) |
509 | 5.33k | { |
510 | 5.33k | if ( uart->dw_usr_bsy && |
511 | 0 | (ns_read_reg(uart, UART_IIR) & UART_IIR_BSY) == UART_IIR_BSY ) |
512 | 0 | { |
513 | 0 | /* DesignWare 8250 detects if LCR is written while the UART is |
514 | 0 | * busy and raises a "busy detect" interrupt. Read the UART |
515 | 0 | * Status Register to clear this state. |
516 | 0 | * |
517 | 0 | * Allwinner/sunxi UART hardware is similar to DesignWare 8250 |
518 | 0 | * and also contains a "busy detect" interrupt. So this quirk |
519 | 0 | * fix will also be used for Allwinner UART. |
520 | 0 | */ |
521 | 0 | ns_read_reg(uart, UART_USR); |
522 | 0 | } |
523 | 5.33k | } |
524 | | |
525 | | static void ns16550_interrupt( |
526 | | int irq, void *dev_id, struct cpu_user_regs *regs) |
527 | 9.03k | { |
528 | 9.03k | struct serial_port *port = dev_id; |
529 | 9.03k | struct ns16550 *uart = port->uart; |
530 | 9.03k | |
531 | 9.03k | uart->intr_works = 1; |
532 | 9.03k | |
533 | 14.3k | while ( !(ns_read_reg(uart, UART_IIR) & UART_IIR_NOINT) ) |
534 | 5.32k | { |
535 | 5.32k | u8 lsr = ns_read_reg(uart, UART_LSR); |
536 | 5.32k | |
537 | 5.32k | if ( (lsr & uart->lsr_mask) == uart->lsr_mask ) |
538 | 5.32k | serial_tx_interrupt(port, regs); |
539 | 5.32k | if ( lsr & UART_LSR_DR ) |
540 | 0 | serial_rx_interrupt(port, regs); |
541 | 5.32k | |
542 | 5.32k | /* A "busy-detect" condition is observed on Allwinner/sunxi UART |
543 | 5.32k | * after LCR is written during setup. It needs to be cleared at |
544 | 5.32k | * this point or UART_IIR_NOINT will never be set and this loop |
545 | 5.32k | * will continue forever. |
546 | 5.32k | * |
547 | 5.32k | * This state can be cleared by calling the dw_usr_busy quirk |
548 | 5.32k | * handler that resolves "busy-detect" for DesignWare uart. |
549 | 5.32k | */ |
550 | 5.32k | handle_dw_usr_busy_quirk(uart); |
551 | 5.32k | } |
552 | 9.03k | } |
553 | | |
554 | | /* Safe: ns16550_poll() runs as softirq so not reentrant on a given CPU. */ |
555 | | static DEFINE_PER_CPU(struct serial_port *, poll_port); |
556 | | |
557 | | static void __ns16550_poll(struct cpu_user_regs *regs) |
558 | 1 | { |
559 | 1 | struct serial_port *port = this_cpu(poll_port); |
560 | 1 | struct ns16550 *uart = port->uart; |
561 | 1 | |
562 | 1 | if ( uart->intr_works ) |
563 | 1 | return; /* Interrupts work - no more polling */ |
564 | 1 | |
565 | 0 | while ( ns_read_reg(uart, UART_LSR) & UART_LSR_DR ) |
566 | 0 | { |
567 | 0 | if ( ns16550_ioport_invalid(uart) ) |
568 | 0 | goto out; |
569 | 0 |
|
570 | 0 | serial_rx_interrupt(port, regs); |
571 | 0 | } |
572 | 0 |
|
573 | 0 | if ( ( ns_read_reg(uart, UART_LSR) & uart->lsr_mask ) == uart->lsr_mask ) |
574 | 0 | serial_tx_interrupt(port, regs); |
575 | 0 |
|
576 | 0 | out: |
577 | 0 | set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms)); |
578 | 0 | } |
579 | | |
580 | | static void ns16550_poll(void *data) |
581 | 1 | { |
582 | 1 | this_cpu(poll_port) = data; |
583 | 1 | #ifdef run_in_exception_handler |
584 | 1 | run_in_exception_handler(__ns16550_poll); |
585 | 1 | #else |
586 | | __ns16550_poll(guest_cpu_user_regs()); |
587 | | #endif |
588 | 1 | } |
589 | | |
590 | | static int ns16550_tx_ready(struct serial_port *port) |
591 | 3.41M | { |
592 | 3.41M | struct ns16550 *uart = port->uart; |
593 | 3.41M | |
594 | 3.41M | if ( ns16550_ioport_invalid(uart) ) |
595 | 0 | return -EIO; |
596 | 3.41M | |
597 | 3.41M | return ( (ns_read_reg(uart, UART_LSR) & |
598 | 3.27M | uart->lsr_mask ) == uart->lsr_mask ) ? uart->fifo_size : 0; |
599 | 3.41M | } |
600 | | |
601 | | static void ns16550_putc(struct serial_port *port, char c) |
602 | 141k | { |
603 | 141k | struct ns16550 *uart = port->uart; |
604 | 141k | ns_write_reg(uart, UART_THR, c); |
605 | 141k | } |
606 | | |
607 | | static int ns16550_getc(struct serial_port *port, char *pc) |
608 | 0 | { |
609 | 0 | struct ns16550 *uart = port->uart; |
610 | 0 |
|
611 | 0 | if ( ns16550_ioport_invalid(uart) || |
612 | 0 | !(ns_read_reg(uart, UART_LSR) & UART_LSR_DR) ) |
613 | 0 | return 0; |
614 | 0 |
|
615 | 0 | *pc = ns_read_reg(uart, UART_RBR); |
616 | 0 | return 1; |
617 | 0 | } |
618 | | |
619 | | static void pci_serial_early_init(struct ns16550 *uart) |
620 | 2 | { |
621 | 2 | #ifdef CONFIG_HAS_PCI |
622 | 2 | if ( !uart->ps_bdf_enable || uart->io_base >= 0x10000 ) |
623 | 2 | return; |
624 | 2 | |
625 | 0 | if ( uart->pb_bdf_enable ) |
626 | 0 | pci_conf_write16(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2], |
627 | 0 | PCI_IO_BASE, |
628 | 0 | (uart->io_base & 0xF000) | |
629 | 0 | ((uart->io_base & 0xF000) >> 8)); |
630 | 0 |
|
631 | 0 | pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], |
632 | 0 | PCI_BASE_ADDRESS_0, |
633 | 0 | uart->io_base | PCI_BASE_ADDRESS_SPACE_IO); |
634 | 0 | pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], |
635 | 0 | PCI_COMMAND, PCI_COMMAND_IO); |
636 | 0 | #endif |
637 | 0 | } |
638 | | |
639 | | static void ns16550_setup_preirq(struct ns16550 *uart) |
640 | 1 | { |
641 | 1 | unsigned char lcr; |
642 | 1 | unsigned int divisor; |
643 | 1 | |
644 | 1 | uart->intr_works = 0; |
645 | 1 | |
646 | 1 | pci_serial_early_init(uart); |
647 | 1 | |
648 | 1 | lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity; |
649 | 1 | |
650 | 1 | /* No interrupts. */ |
651 | 1 | ns_write_reg(uart, UART_IER, 0); |
652 | 1 | |
653 | 1 | /* Handle the DesignWare 8250 'busy-detect' quirk. */ |
654 | 1 | handle_dw_usr_busy_quirk(uart); |
655 | 1 | |
656 | 1 | /* Line control and baud-rate generator. */ |
657 | 1 | ns_write_reg(uart, UART_LCR, lcr | UART_LCR_DLAB); |
658 | 1 | if ( uart->baud != BAUD_AUTO ) |
659 | 1 | { |
660 | 1 | /* Baud rate specified: program it into the divisor latch. */ |
661 | 1 | divisor = uart->clock_hz / (uart->baud << 4); |
662 | 1 | ns_write_reg(uart, UART_DLL, (char)divisor); |
663 | 1 | ns_write_reg(uart, UART_DLM, (char)(divisor >> 8)); |
664 | 1 | } |
665 | 1 | else |
666 | 0 | { |
667 | 0 | /* Baud rate already set: read it out from the divisor latch. */ |
668 | 0 | divisor = ns_read_reg(uart, UART_DLL); |
669 | 0 | divisor |= ns_read_reg(uart, UART_DLM) << 8; |
670 | 0 | if ( divisor ) |
671 | 0 | uart->baud = uart->clock_hz / (divisor << 4); |
672 | 0 | else |
673 | 0 | printk(XENLOG_ERR |
674 | 0 | "Automatic baud rate determination was requested," |
675 | 0 | " but a baud rate was not set up\n"); |
676 | 0 | } |
677 | 1 | ns_write_reg(uart, UART_LCR, lcr); |
678 | 1 | |
679 | 1 | /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */ |
680 | 1 | ns_write_reg(uart, UART_MCR, UART_MCR_DTR | UART_MCR_RTS); |
681 | 1 | |
682 | 1 | /* Enable and clear the FIFOs. Set a large trigger threshold. */ |
683 | 1 | ns_write_reg(uart, UART_FCR, |
684 | 1 | UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX | UART_FCR_TRG14); |
685 | 1 | } |
686 | | |
687 | | static void __init ns16550_init_preirq(struct serial_port *port) |
688 | 1 | { |
689 | 1 | struct ns16550 *uart = port->uart; |
690 | 1 | |
691 | 1 | #ifdef CONFIG_HAS_IOPORTS |
692 | 1 | /* I/O ports are distinguished by their size (16 bits). */ |
693 | 1 | if ( uart->io_base >= 0x10000 ) |
694 | 1 | #endif |
695 | 0 | { |
696 | 0 | #ifdef CONFIG_X86 |
697 | 0 | enum fixed_addresses idx = FIX_COM_BEGIN + (uart - ns16550_com); |
698 | 0 |
|
699 | 0 | set_fixmap_nocache(idx, uart->io_base); |
700 | 0 | uart->remapped_io_base = (void __iomem *)fix_to_virt(idx); |
701 | 0 | uart->remapped_io_base += uart->io_base & ~PAGE_MASK; |
702 | 0 | #else |
703 | | uart->remapped_io_base = (char *)ioremap(uart->io_base, uart->io_size); |
704 | | #endif |
705 | 0 | } |
706 | 1 | |
707 | 1 | ns16550_setup_preirq(uart); |
708 | 1 | |
709 | 1 | /* Check this really is a 16550+. Otherwise we have no FIFOs. */ |
710 | 1 | if ( ((ns_read_reg(uart, UART_IIR) & 0xc0) == 0xc0) && |
711 | 1 | ((ns_read_reg(uart, UART_FCR) & UART_FCR_TRG14) == UART_FCR_TRG14) ) |
712 | 1 | uart->fifo_size = 16; |
713 | 1 | } |
714 | | |
715 | | static void ns16550_setup_postirq(struct ns16550 *uart) |
716 | 1 | { |
717 | 1 | if ( uart->irq > 0 ) |
718 | 1 | { |
719 | 1 | /* Master interrupt enable; also keep DTR/RTS asserted. */ |
720 | 1 | ns_write_reg(uart, |
721 | 1 | UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS); |
722 | 1 | |
723 | 1 | /* Enable receive interrupts. */ |
724 | 1 | ns_write_reg(uart, UART_IER, UART_IER_ERDAI); |
725 | 1 | } |
726 | 1 | |
727 | 1 | if ( uart->irq >= 0 ) |
728 | 1 | set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms)); |
729 | 1 | } |
730 | | |
731 | | static void __init ns16550_init_postirq(struct serial_port *port) |
732 | 1 | { |
733 | 1 | struct ns16550 *uart = port->uart; |
734 | 1 | int rc, bits; |
735 | 1 | |
736 | 1 | if ( uart->irq < 0 ) |
737 | 0 | return; |
738 | 1 | |
739 | 1 | serial_async_transmit(port); |
740 | 1 | |
741 | 1 | init_timer(&uart->timer, ns16550_poll, port, 0); |
742 | 1 | init_timer(&uart->resume_timer, ns16550_delayed_resume, port, 0); |
743 | 1 | |
744 | 1 | /* Calculate time to fill RX FIFO and/or empty TX FIFO for polling. */ |
745 | 1 | bits = uart->data_bits + uart->stop_bits + !!uart->parity; |
746 | 1 | uart->timeout_ms = max_t( |
747 | 1 | unsigned int, 1, (bits * uart->fifo_size * 1000) / uart->baud); |
748 | 1 | |
749 | 1 | if ( uart->irq > 0 ) |
750 | 1 | { |
751 | 1 | uart->irqaction.handler = ns16550_interrupt; |
752 | 1 | uart->irqaction.name = "ns16550"; |
753 | 1 | uart->irqaction.dev_id = port; |
754 | 1 | if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) |
755 | 0 | printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq); |
756 | 1 | } |
757 | 1 | |
758 | 1 | ns16550_setup_postirq(uart); |
759 | 1 | |
760 | 1 | #ifdef CONFIG_HAS_PCI |
761 | 1 | if ( uart->bar || uart->ps_bdf_enable ) |
762 | 0 | { |
763 | 0 | if ( !uart->param ) |
764 | 0 | pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1], |
765 | 0 | uart->ps_bdf[2])); |
766 | 0 | else |
767 | 0 | { |
768 | 0 | if ( uart->param->mmio && |
769 | 0 | rangeset_add_range(mmio_ro_ranges, |
770 | 0 | uart->io_base, |
771 | 0 | uart->io_base + uart->io_size - 1) ) |
772 | 0 | printk(XENLOG_INFO "Error while adding MMIO range of device to mmio_ro_ranges\n"); |
773 | 0 |
|
774 | 0 | if ( pci_ro_device(0, uart->ps_bdf[0], |
775 | 0 | PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2])) ) |
776 | 0 | printk(XENLOG_INFO "Could not mark config space of %02x:%02x.%u read-only.\n", |
777 | 0 | uart->ps_bdf[0], uart->ps_bdf[1], |
778 | 0 | uart->ps_bdf[2]); |
779 | 0 | } |
780 | 0 | } |
781 | 1 | #endif |
782 | 1 | } |
783 | | |
784 | | static void ns16550_suspend(struct serial_port *port) |
785 | 0 | { |
786 | 0 | struct ns16550 *uart = port->uart; |
787 | 0 |
|
788 | 0 | stop_timer(&uart->timer); |
789 | 0 |
|
790 | 0 | #ifdef CONFIG_HAS_PCI |
791 | 0 | if ( uart->bar ) |
792 | 0 | uart->cr = pci_conf_read16(0, uart->ps_bdf[0], uart->ps_bdf[1], |
793 | 0 | uart->ps_bdf[2], PCI_COMMAND); |
794 | 0 | #endif |
795 | 0 | } |
796 | | |
797 | | static void _ns16550_resume(struct serial_port *port) |
798 | 0 | { |
799 | 0 | #ifdef CONFIG_HAS_PCI |
800 | 0 | struct ns16550 *uart = port->uart; |
801 | 0 |
|
802 | 0 | if ( uart->bar ) |
803 | 0 | { |
804 | 0 | pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], |
805 | 0 | PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar); |
806 | 0 |
|
807 | 0 | /* If 64 bit BAR, write higher 32 bits to BAR+4 */ |
808 | 0 | if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) |
809 | 0 | pci_conf_write32(0, uart->ps_bdf[0], |
810 | 0 | uart->ps_bdf[1], uart->ps_bdf[2], |
811 | 0 | PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->bar64); |
812 | 0 |
|
813 | 0 | pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2], |
814 | 0 | PCI_COMMAND, uart->cr); |
815 | 0 | } |
816 | 0 | #endif |
817 | 0 |
|
818 | 0 | ns16550_setup_preirq(port->uart); |
819 | 0 | ns16550_setup_postirq(port->uart); |
820 | 0 | } |
821 | | |
822 | | static int delayed_resume_tries; |
823 | | static void ns16550_delayed_resume(void *data) |
824 | 0 | { |
825 | 0 | struct serial_port *port = data; |
826 | 0 | struct ns16550 *uart = port->uart; |
827 | 0 |
|
828 | 0 | if ( ns16550_ioport_invalid(port->uart) && delayed_resume_tries-- ) |
829 | 0 | set_timer(&uart->resume_timer, NOW() + RESUME_DELAY); |
830 | 0 | else |
831 | 0 | _ns16550_resume(port); |
832 | 0 | } |
833 | | |
834 | | static void ns16550_resume(struct serial_port *port) |
835 | 0 | { |
836 | 0 | struct ns16550 *uart = port->uart; |
837 | 0 |
|
838 | 0 | /* |
839 | 0 | * Check for ioport access, before fully resuming operation. |
840 | 0 | * On some systems, there is a SuperIO card that provides |
841 | 0 | * this legacy ioport on the LPC bus. |
842 | 0 | * |
843 | 0 | * We need to wait for dom0's ACPI processing to run the proper |
844 | 0 | * AML to re-initialize the chip, before we can use the card again. |
845 | 0 | * |
846 | 0 | * This may cause a small amount of garbage to be written |
847 | 0 | * to the serial log while we wait patiently for that AML to |
848 | 0 | * be executed. However, this is preferable to spinning in an |
849 | 0 | * infinite loop, as seen on a Lenovo T430, when serial was enabled. |
850 | 0 | */ |
851 | 0 | if ( ns16550_ioport_invalid(uart) ) |
852 | 0 | { |
853 | 0 | delayed_resume_tries = RESUME_RETRIES; |
854 | 0 | set_timer(&uart->resume_timer, NOW() + RESUME_DELAY); |
855 | 0 | } |
856 | 0 | else |
857 | 0 | _ns16550_resume(port); |
858 | 0 | } |
859 | | |
860 | | static void __init ns16550_endboot(struct serial_port *port) |
861 | 1 | { |
862 | 1 | #ifdef CONFIG_HAS_IOPORTS |
863 | 1 | struct ns16550 *uart = port->uart; |
864 | 1 | int rv; |
865 | 1 | |
866 | 1 | if ( uart->remapped_io_base ) |
867 | 0 | return; |
868 | 1 | rv = ioports_deny_access(hardware_domain, uart->io_base, uart->io_base + 7); |
869 | 1 | if ( rv != 0 ) |
870 | 0 | BUG(); |
871 | 1 | #endif |
872 | 1 | } |
873 | | |
874 | | static int __init ns16550_irq(struct serial_port *port) |
875 | 1 | { |
876 | 1 | struct ns16550 *uart = port->uart; |
877 | 1 | return ((uart->irq > 0) ? uart->irq : -1); |
878 | 1 | } |
879 | | |
880 | | static void ns16550_start_tx(struct serial_port *port) |
881 | 141k | { |
882 | 141k | struct ns16550 *uart = port->uart; |
883 | 141k | u8 ier = ns_read_reg(uart, UART_IER); |
884 | 141k | |
885 | 141k | /* Unmask transmit holding register empty interrupt if currently masked. */ |
886 | 141k | if ( !(ier & UART_IER_ETHREI) ) |
887 | 5.32k | ns_write_reg(uart, UART_IER, ier | UART_IER_ETHREI); |
888 | 141k | } |
889 | | |
890 | | static void ns16550_stop_tx(struct serial_port *port) |
891 | 5.32k | { |
892 | 5.32k | struct ns16550 *uart = port->uart; |
893 | 5.32k | u8 ier = ns_read_reg(uart, UART_IER); |
894 | 5.32k | |
895 | 5.32k | /* Mask off transmit holding register empty interrupt if currently unmasked. */ |
896 | 5.32k | if ( ier & UART_IER_ETHREI ) |
897 | 5.32k | ns_write_reg(uart, UART_IER, ier & ~UART_IER_ETHREI); |
898 | 5.32k | } |
899 | | |
900 | | #ifdef CONFIG_ARM |
901 | | static const struct vuart_info *ns16550_vuart_info(struct serial_port *port) |
902 | | { |
903 | | struct ns16550 *uart = port->uart; |
904 | | |
905 | | return &uart->vuart; |
906 | | } |
907 | | #endif |
908 | | |
909 | | static struct uart_driver __read_mostly ns16550_driver = { |
910 | | .init_preirq = ns16550_init_preirq, |
911 | | .init_postirq = ns16550_init_postirq, |
912 | | .endboot = ns16550_endboot, |
913 | | .suspend = ns16550_suspend, |
914 | | .resume = ns16550_resume, |
915 | | .tx_ready = ns16550_tx_ready, |
916 | | .putc = ns16550_putc, |
917 | | .getc = ns16550_getc, |
918 | | .irq = ns16550_irq, |
919 | | .start_tx = ns16550_start_tx, |
920 | | .stop_tx = ns16550_stop_tx, |
921 | | #ifdef CONFIG_ARM |
922 | | .vuart_info = ns16550_vuart_info, |
923 | | #endif |
924 | | }; |
925 | | |
926 | | static int __init parse_parity_char(int c) |
927 | 3 | { |
928 | 3 | switch ( c ) |
929 | 3 | { |
930 | 3 | case 'n': |
931 | 3 | return UART_PARITY_NONE; |
932 | 0 | case 'o': |
933 | 0 | return UART_PARITY_ODD; |
934 | 0 | case 'e': |
935 | 0 | return UART_PARITY_EVEN; |
936 | 0 | case 'm': |
937 | 0 | return UART_PARITY_MARK; |
938 | 0 | case 's': |
939 | 0 | return UART_PARITY_SPACE; |
940 | 3 | } |
941 | 0 | return 0; |
942 | 3 | } |
943 | | |
944 | | static int __init check_existence(struct ns16550 *uart) |
945 | 1 | { |
946 | 1 | unsigned char status, scratch, scratch2, scratch3; |
947 | 1 | |
948 | 1 | #ifdef CONFIG_HAS_IOPORTS |
949 | 1 | /* |
950 | 1 | * We can't poke MMIO UARTs until they get I/O remapped later. Assume that |
951 | 1 | * if we're getting MMIO UARTs, the arch code knows what it's doing. |
952 | 1 | */ |
953 | 1 | if ( uart->io_base >= 0x10000 ) |
954 | 0 | return 1; |
955 | 1 | #else |
956 | | return 1; /* Everything is MMIO */ |
957 | | #endif |
958 | 1 | |
959 | 1 | #ifdef CONFIG_HAS_PCI |
960 | 1 | pci_serial_early_init(uart); |
961 | 1 | #endif |
962 | 1 | |
963 | 1 | /* |
964 | 1 | * Do a simple existence test first; if we fail this, |
965 | 1 | * there's no point trying anything else. |
966 | 1 | */ |
967 | 1 | scratch = ns_read_reg(uart, UART_IER); |
968 | 1 | ns_write_reg(uart, UART_IER, 0); |
969 | 1 | |
970 | 1 | /* |
971 | 1 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL |
972 | 1 | * 16C754B) allow only to modify them if an EFR bit is set. |
973 | 1 | */ |
974 | 1 | scratch2 = ns_read_reg(uart, UART_IER) & 0x0f; |
975 | 1 | ns_write_reg(uart,UART_IER, 0x0F); |
976 | 1 | scratch3 = ns_read_reg(uart, UART_IER) & 0x0f; |
977 | 1 | ns_write_reg(uart, UART_IER, scratch); |
978 | 1 | if ( (scratch2 != 0) || (scratch3 != 0x0F) ) |
979 | 0 | return 0; |
980 | 1 | |
981 | 1 | /* |
982 | 1 | * Check to see if a UART is really there. |
983 | 1 | * Use loopback test mode. |
984 | 1 | */ |
985 | 1 | ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A); |
986 | 1 | status = ns_read_reg(uart, UART_MSR) & 0xF0; |
987 | 1 | return (status == 0x90); |
988 | 1 | } |
989 | | |
990 | | #ifdef CONFIG_HAS_PCI |
991 | | static int __init |
992 | | pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) |
993 | 0 | { |
994 | 0 | u64 orig_base = uart->io_base; |
995 | 0 | unsigned int b, d, f, nextf, i; |
996 | 0 |
|
997 | 0 | /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */ |
998 | 0 | for ( b = skip_amt ? 1 : 0; b < 0x100; b++ ) |
999 | 0 | { |
1000 | 0 | for ( d = 0; d < 0x20; d++ ) |
1001 | 0 | { |
1002 | 0 | for ( f = 0; f < 8; f = nextf ) |
1003 | 0 | { |
1004 | 0 | unsigned int bar_idx = 0, port_idx = idx; |
1005 | 0 | uint32_t bar, bar_64 = 0, len, len_64; |
1006 | 0 | u64 size = 0; |
1007 | 0 | const struct ns16550_config_param *param = uart_param; |
1008 | 0 |
|
1009 | 0 | nextf = (f || (pci_conf_read16(0, b, d, f, PCI_HEADER_TYPE) & |
1010 | 0 | 0x80)) ? f + 1 : 8; |
1011 | 0 |
|
1012 | 0 | switch ( pci_conf_read16(0, b, d, f, PCI_CLASS_DEVICE) ) |
1013 | 0 | { |
1014 | 0 | case 0x0700: /* single port serial */ |
1015 | 0 | case 0x0702: /* multi port serial */ |
1016 | 0 | case 0x0780: /* other (e.g serial+parallel) */ |
1017 | 0 | break; |
1018 | 0 | case 0xffff: |
1019 | 0 | if ( !f ) |
1020 | 0 | nextf = 8; |
1021 | 0 | /* fall through */ |
1022 | 0 | default: |
1023 | 0 | continue; |
1024 | 0 | } |
1025 | 0 |
|
1026 | 0 | /* Check for params in uart_config lookup table */ |
1027 | 0 | for ( i = 0; i < ARRAY_SIZE(uart_config); i++ ) |
1028 | 0 | { |
1029 | 0 | u16 vendor = pci_conf_read16(0, b, d, f, PCI_VENDOR_ID); |
1030 | 0 | u16 device = pci_conf_read16(0, b, d, f, PCI_DEVICE_ID); |
1031 | 0 |
|
1032 | 0 | if ( uart_config[i].vendor_id == vendor && |
1033 | 0 | uart_config[i].dev_id == device ) |
1034 | 0 | { |
1035 | 0 | param += uart_config[i].param; |
1036 | 0 | break; |
1037 | 0 | } |
1038 | 0 | } |
1039 | 0 |
|
1040 | 0 | if ( !param->bar0 ) |
1041 | 0 | { |
1042 | 0 | bar_idx = idx; |
1043 | 0 | port_idx = 0; |
1044 | 0 | } |
1045 | 0 |
|
1046 | 0 | if ( port_idx >= param->max_ports ) |
1047 | 0 | { |
1048 | 0 | idx -= param->max_ports; |
1049 | 0 | continue; |
1050 | 0 | } |
1051 | 0 |
|
1052 | 0 | uart->io_base = 0; |
1053 | 0 | bar = pci_conf_read32(0, b, d, f, |
1054 | 0 | PCI_BASE_ADDRESS_0 + bar_idx*4); |
1055 | 0 |
|
1056 | 0 | /* MMIO based */ |
1057 | 0 | if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) |
1058 | 0 | { |
1059 | 0 | pci_conf_write32(0, b, d, f, |
1060 | 0 | PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); |
1061 | 0 | len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4); |
1062 | 0 | pci_conf_write32(0, b, d, f, |
1063 | 0 | PCI_BASE_ADDRESS_0 + bar_idx*4, bar); |
1064 | 0 |
|
1065 | 0 | /* Handle 64 bit BAR if found */ |
1066 | 0 | if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 ) |
1067 | 0 | { |
1068 | 0 | bar_64 = pci_conf_read32(0, b, d, f, |
1069 | 0 | PCI_BASE_ADDRESS_0 + (bar_idx+1)*4); |
1070 | 0 | pci_conf_write32(0, b, d, f, |
1071 | 0 | PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0u); |
1072 | 0 | len_64 = pci_conf_read32(0, b, d, f, |
1073 | 0 | PCI_BASE_ADDRESS_0 + (bar_idx+1)*4); |
1074 | 0 | pci_conf_write32(0, b, d, f, |
1075 | 0 | PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, bar_64); |
1076 | 0 | size = ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_MASK; |
1077 | 0 | size &= ((u64)len_64 << 32) | len; |
1078 | 0 | } |
1079 | 0 | else |
1080 | 0 | size = len & PCI_BASE_ADDRESS_MEM_MASK; |
1081 | 0 |
|
1082 | 0 | uart->io_base = ((u64)bar_64 << 32) | |
1083 | 0 | (bar & PCI_BASE_ADDRESS_MEM_MASK); |
1084 | 0 | } |
1085 | 0 | /* IO based */ |
1086 | 0 | else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) ) |
1087 | 0 | { |
1088 | 0 | pci_conf_write32(0, b, d, f, |
1089 | 0 | PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); |
1090 | 0 | len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0); |
1091 | 0 | pci_conf_write32(0, b, d, f, |
1092 | 0 | PCI_BASE_ADDRESS_0 + bar_idx*4, bar); |
1093 | 0 | size = len & PCI_BASE_ADDRESS_IO_MASK; |
1094 | 0 |
|
1095 | 0 | uart->io_base = bar & ~PCI_BASE_ADDRESS_SPACE_IO; |
1096 | 0 | } |
1097 | 0 |
|
1098 | 0 | /* If we have an io_base, then we succeeded in the lookup. */ |
1099 | 0 | if ( !uart->io_base ) |
1100 | 0 | continue; |
1101 | 0 |
|
1102 | 0 | size &= -size; |
1103 | 0 |
|
1104 | 0 | /* |
1105 | 0 | * Require length of actually used region to be at least |
1106 | 0 | * 8 bytes times (1 << reg_shift). |
1107 | 0 | */ |
1108 | 0 | if ( size < param->first_offset + |
1109 | 0 | port_idx * param->uart_offset + |
1110 | 0 | (8 << param->reg_shift) ) |
1111 | 0 | continue; |
1112 | 0 |
|
1113 | 0 | uart->param = param; |
1114 | 0 |
|
1115 | 0 | uart->reg_shift = param->reg_shift; |
1116 | 0 | uart->reg_width = param->reg_width; |
1117 | 0 | uart->lsr_mask = param->lsr_mask; |
1118 | 0 | uart->io_base += param->first_offset + |
1119 | 0 | port_idx * param->uart_offset; |
1120 | 0 | if ( param->base_baud ) |
1121 | 0 | uart->clock_hz = param->base_baud * 16; |
1122 | 0 | if ( param->fifo_size ) |
1123 | 0 | uart->fifo_size = param->fifo_size; |
1124 | 0 |
|
1125 | 0 | uart->ps_bdf[0] = b; |
1126 | 0 | uart->ps_bdf[1] = d; |
1127 | 0 | uart->ps_bdf[2] = f; |
1128 | 0 | uart->bar_idx = bar_idx; |
1129 | 0 | uart->bar = bar; |
1130 | 0 | uart->bar64 = bar_64; |
1131 | 0 | uart->io_size = max(8U << param->reg_shift, |
1132 | 0 | param->uart_offset); |
1133 | 0 | uart->irq = pci_conf_read8(0, b, d, f, PCI_INTERRUPT_PIN) ? |
1134 | 0 | pci_conf_read8(0, b, d, f, PCI_INTERRUPT_LINE) : 0; |
1135 | 0 |
|
1136 | 0 | return 0; |
1137 | 0 | } |
1138 | 0 | } |
1139 | 0 | } |
1140 | 0 |
|
1141 | 0 | if ( !skip_amt ) |
1142 | 0 | return -1; |
1143 | 0 |
|
1144 | 0 | /* No AMT found, fallback to the defaults. */ |
1145 | 0 | uart->io_base = orig_base; |
1146 | 0 |
|
1147 | 0 | return 0; |
1148 | 0 | } |
1149 | | #endif |
1150 | | |
1151 | | /* |
1152 | | * Used to parse name value pairs and return which value it is along with |
1153 | | * pointer for the extracted value. |
1154 | | */ |
1155 | | static enum __init serial_param_type get_token(char *token, char **value) |
1156 | 0 | { |
1157 | 0 | const char *param_name; |
1158 | 0 | unsigned int i; |
1159 | 0 |
|
1160 | 0 | param_name = strsep(&token, "="); |
1161 | 0 | if ( param_name == NULL ) |
1162 | 0 | return num_serial_params; |
1163 | 0 |
|
1164 | 0 | /* Linear search for the parameter. */ |
1165 | 0 | for ( i = 0; i < ARRAY_SIZE(sp_vars); i++ ) |
1166 | 0 | { |
1167 | 0 | if ( strcmp(sp_vars[i].name, param_name) == 0 ) |
1168 | 0 | { |
1169 | 0 | *value = token; |
1170 | 0 | return sp_vars[i].type; |
1171 | 0 | } |
1172 | 0 | } |
1173 | 0 |
|
1174 | 0 | return num_serial_params; |
1175 | 0 | } |
1176 | | |
1177 | | #define PARSE_ERR(_f, _a...) \ |
1178 | 0 | do { \ |
1179 | 0 | printk( "ERROR: " _f "\n" , ## _a ); \ |
1180 | 0 | return; \ |
1181 | 0 | } while ( 0 ) |
1182 | | |
1183 | | #define PARSE_ERR_RET(_f, _a...) \ |
1184 | 0 | do { \ |
1185 | 0 | printk( "ERROR: " _f "\n" , ## _a ); \ |
1186 | 0 | return false; \ |
1187 | 0 | } while ( 0 ) |
1188 | | |
1189 | | |
1190 | | static bool __init parse_positional(struct ns16550 *uart, char **str) |
1191 | 1 | { |
1192 | 1 | int baud; |
1193 | 1 | const char *conf; |
1194 | 1 | char *name_val_pos; |
1195 | 1 | |
1196 | 1 | conf = *str; |
1197 | 1 | name_val_pos = strchr(conf, '='); |
1198 | 1 | |
1199 | 1 | /* Finding the end of the positional parameters. */ |
1200 | 1 | while ( name_val_pos > *str ) |
1201 | 0 | { |
1202 | 0 | /* Working backwards from the '=' sign. */ |
1203 | 0 | name_val_pos--; |
1204 | 0 | if ( *name_val_pos == ',' ) |
1205 | 0 | { |
1206 | 0 | *name_val_pos = '\0'; |
1207 | 0 | name_val_pos++; |
1208 | 0 | break; |
1209 | 0 | } |
1210 | 0 | } |
1211 | 1 | |
1212 | 1 | *str = name_val_pos; |
1213 | 1 | /* When there are no positional parameters, we return from the function. */ |
1214 | 1 | if ( conf == *str ) |
1215 | 0 | return true; |
1216 | 1 | |
1217 | 1 | /* Parse positional parameters here. */ |
1218 | 1 | if ( strncmp(conf, "auto", 4) == 0 ) |
1219 | 0 | { |
1220 | 0 | uart->baud = BAUD_AUTO; |
1221 | 0 | conf += 4; |
1222 | 0 | } |
1223 | 1 | else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 ) |
1224 | 1 | uart->baud = baud; |
1225 | 1 | |
1226 | 1 | if ( *conf == '/' ) |
1227 | 0 | { |
1228 | 0 | conf++; |
1229 | 0 | uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4; |
1230 | 0 | } |
1231 | 1 | |
1232 | 1 | if ( *conf == ',' && *++conf != ',' ) |
1233 | 1 | { |
1234 | 1 | uart->data_bits = simple_strtoul(conf, &conf, 10); |
1235 | 1 | |
1236 | 1 | uart->parity = parse_parity_char(*conf); |
1237 | 1 | |
1238 | 1 | uart->stop_bits = simple_strtoul(conf + 1, &conf, 10); |
1239 | 1 | } |
1240 | 1 | |
1241 | 1 | if ( *conf == ',' && *++conf != ',' ) |
1242 | 0 | { |
1243 | 0 | #ifdef CONFIG_HAS_PCI |
1244 | 0 | if ( strncmp(conf, "pci", 3) == 0 ) |
1245 | 0 | { |
1246 | 0 | if ( pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com) ) |
1247 | 0 | return true; |
1248 | 0 | conf += 3; |
1249 | 0 | } |
1250 | 0 | else if ( strncmp(conf, "amt", 3) == 0 ) |
1251 | 0 | { |
1252 | 0 | if ( pci_uart_config(uart, 0, uart - ns16550_com) ) |
1253 | 0 | return true; |
1254 | 0 | conf += 3; |
1255 | 0 | } |
1256 | 0 | else |
1257 | 0 | #endif |
1258 | 0 | { |
1259 | 0 | uart->io_base = simple_strtoul(conf, &conf, 0); |
1260 | 0 | } |
1261 | 0 | } |
1262 | 1 | |
1263 | 1 | if ( *conf == ',' && *++conf != ',' ) |
1264 | 0 | uart->irq = simple_strtol(conf, &conf, 10); |
1265 | 1 | |
1266 | 1 | #ifdef CONFIG_HAS_PCI |
1267 | 1 | if ( *conf == ',' && *++conf != ',' ) |
1268 | 0 | { |
1269 | 0 | conf = parse_pci(conf, NULL, &uart->ps_bdf[0], |
1270 | 0 | &uart->ps_bdf[1], &uart->ps_bdf[2]); |
1271 | 0 | if ( !conf ) |
1272 | 0 | PARSE_ERR_RET("Bad port PCI coordinates"); |
1273 | 0 | uart->ps_bdf_enable = true; |
1274 | 0 | } |
1275 | 1 | |
1276 | 1 | if ( *conf == ',' && *++conf != ',' ) |
1277 | 0 | { |
1278 | 0 | if ( !parse_pci(conf, NULL, &uart->pb_bdf[0], |
1279 | 0 | &uart->pb_bdf[1], &uart->pb_bdf[2]) ) |
1280 | 0 | PARSE_ERR_RET("Bad bridge PCI coordinates"); |
1281 | 0 | uart->pb_bdf_enable = true; |
1282 | 0 | } |
1283 | 1 | #endif |
1284 | 1 | |
1285 | 1 | return true; |
1286 | 1 | } |
1287 | | |
1288 | | static bool __init parse_namevalue_pairs(char *str, struct ns16550 *uart) |
1289 | 1 | { |
1290 | 1 | char *token, *start = str; |
1291 | 1 | char *param_value = NULL; |
1292 | 1 | bool dev_set = false; |
1293 | 1 | |
1294 | 1 | if ( (str == NULL) || (*str == '\0') ) |
1295 | 1 | return true; |
1296 | 1 | |
1297 | 0 | do |
1298 | 0 | { |
1299 | 0 | /* When no tokens are found, start will be NULL */ |
1300 | 0 | token = strsep(&start, ","); |
1301 | 0 |
|
1302 | 0 | switch ( get_token(token, ¶m_value) ) |
1303 | 0 | { |
1304 | 0 | case baud: |
1305 | 0 | uart->baud = simple_strtoul(param_value, NULL, 0); |
1306 | 0 | break; |
1307 | 0 |
|
1308 | 0 | case clock_hz: |
1309 | 0 | uart->clock_hz = simple_strtoul(param_value, NULL, 0) << 4; |
1310 | 0 | break; |
1311 | 0 |
|
1312 | 0 | case io_base: |
1313 | 0 | if ( dev_set ) |
1314 | 0 | { |
1315 | 0 | printk(XENLOG_WARNING |
1316 | 0 | "Can't use io_base with dev=pci or dev=amt options\n"); |
1317 | 0 | break; |
1318 | 0 | } |
1319 | 0 | uart->io_base = simple_strtoul(param_value, NULL, 0); |
1320 | 0 | break; |
1321 | 0 |
|
1322 | 0 | case irq: |
1323 | 0 | uart->irq = simple_strtoul(param_value, NULL, 0); |
1324 | 0 | break; |
1325 | 0 |
|
1326 | 0 | case data_bits: |
1327 | 0 | uart->data_bits = simple_strtoul(param_value, NULL, 0); |
1328 | 0 | break; |
1329 | 0 |
|
1330 | 0 | case parity: |
1331 | 0 | uart->parity = parse_parity_char(*param_value); |
1332 | 0 | break; |
1333 | 0 |
|
1334 | 0 | case stop_bits: |
1335 | 0 | uart->stop_bits = simple_strtoul(param_value, NULL, 0); |
1336 | 0 | break; |
1337 | 0 |
|
1338 | 0 | case reg_shift: |
1339 | 0 | uart->reg_shift = simple_strtoul(param_value, NULL, 0); |
1340 | 0 | break; |
1341 | 0 |
|
1342 | 0 | case reg_width: |
1343 | 0 | uart->reg_width = simple_strtoul(param_value, NULL, 0); |
1344 | 0 | break; |
1345 | 0 |
|
1346 | 0 | #ifdef CONFIG_HAS_PCI |
1347 | 0 | case bridge_bdf: |
1348 | 0 | if ( !parse_pci(param_value, NULL, &uart->ps_bdf[0], |
1349 | 0 | &uart->ps_bdf[1], &uart->ps_bdf[2]) ) |
1350 | 0 | PARSE_ERR_RET("Bad port PCI coordinates\n"); |
1351 | 0 | uart->ps_bdf_enable = true; |
1352 | 0 | break; |
1353 | 0 |
|
1354 | 0 | case device: |
1355 | 0 | if ( strncmp(param_value, "pci", 3) == 0 ) |
1356 | 0 | { |
1357 | 0 | pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com); |
1358 | 0 | dev_set = true; |
1359 | 0 | } |
1360 | 0 | else if ( strncmp(param_value, "amt", 3) == 0 ) |
1361 | 0 | { |
1362 | 0 | pci_uart_config(uart, 0, uart - ns16550_com); |
1363 | 0 | dev_set = true; |
1364 | 0 | } |
1365 | 0 | break; |
1366 | 0 |
|
1367 | 0 | case port_bdf: |
1368 | 0 | if ( !parse_pci(param_value, NULL, &uart->pb_bdf[0], |
1369 | 0 | &uart->pb_bdf[1], &uart->pb_bdf[2]) ) |
1370 | 0 | PARSE_ERR_RET("Bad port PCI coordinates\n"); |
1371 | 0 | uart->pb_bdf_enable = true; |
1372 | 0 | break; |
1373 | 0 | #endif |
1374 | 0 |
|
1375 | 0 | default: |
1376 | 0 | PARSE_ERR_RET("Invalid parameter: %s\n", token); |
1377 | 0 | } |
1378 | 0 | } while ( start != NULL ); |
1379 | 0 |
|
1380 | 0 | return true; |
1381 | 0 | } |
1382 | | |
1383 | | static void __init ns16550_parse_port_config( |
1384 | | struct ns16550 *uart, const char *conf) |
1385 | 2 | { |
1386 | 2 | char com_console_options[128]; |
1387 | 2 | char *str; |
1388 | 2 | |
1389 | 2 | /* No user-specified configuration? */ |
1390 | 2 | if ( (conf == NULL) || (*conf == '\0') ) |
1391 | 1 | { |
1392 | 1 | /* Some platforms may automatically probe the UART configuartion. */ |
1393 | 1 | if ( uart->baud != 0 ) |
1394 | 0 | goto config_parsed; |
1395 | 1 | return; |
1396 | 1 | } |
1397 | 2 | |
1398 | 1 | strlcpy(com_console_options, conf, ARRAY_SIZE(com_console_options)); |
1399 | 1 | str = com_console_options; |
1400 | 1 | |
1401 | 1 | /* parse positional parameters and get pointer for name-value pairs */ |
1402 | 1 | if ( !parse_positional(uart, &str) ) |
1403 | 0 | return; |
1404 | 1 | |
1405 | 1 | if ( !parse_namevalue_pairs(str, uart) ) |
1406 | 0 | return; |
1407 | 1 | |
1408 | 1 | config_parsed: |
1409 | 1 | /* Sanity checks. */ |
1410 | 1 | if ( (uart->baud != BAUD_AUTO) && |
1411 | 1 | ((uart->baud < 1200) || (uart->baud > 115200)) ) |
1412 | 0 | PARSE_ERR("Baud rate %d outside supported range.", uart->baud); |
1413 | 1 | if ( (uart->data_bits < 5) || (uart->data_bits > 8) ) |
1414 | 0 | PARSE_ERR("%d data bits are unsupported.", uart->data_bits); |
1415 | 1 | if ( (uart->reg_width != 1) && (uart->reg_width != 4) ) |
1416 | 0 | PARSE_ERR("Accepted values of reg_width are 1 and 4 only"); |
1417 | 1 | if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) ) |
1418 | 0 | PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits); |
1419 | 1 | if ( uart->io_base == 0 ) |
1420 | 0 | PARSE_ERR("I/O base address must be specified."); |
1421 | 1 | if ( !check_existence(uart) ) |
1422 | 0 | PARSE_ERR("16550-compatible serial UART not present"); |
1423 | 1 | |
1424 | 1 | /* Register with generic serial driver. */ |
1425 | 1 | serial_register_uart(uart - ns16550_com, &ns16550_driver, uart); |
1426 | 1 | } |
1427 | | |
1428 | | static void ns16550_init_common(struct ns16550 *uart) |
1429 | 2 | { |
1430 | 2 | uart->clock_hz = UART_CLOCK_HZ; |
1431 | 2 | |
1432 | 2 | /* Default is no transmit FIFO. */ |
1433 | 2 | uart->fifo_size = 1; |
1434 | 2 | |
1435 | 2 | /* Default lsr_mask = UART_LSR_THRE */ |
1436 | 2 | uart->lsr_mask = UART_LSR_THRE; |
1437 | 2 | } |
1438 | | |
1439 | | void __init ns16550_init(int index, struct ns16550_defaults *defaults) |
1440 | 2 | { |
1441 | 2 | struct ns16550 *uart; |
1442 | 2 | |
1443 | 2 | if ( (index < 0) || (index > 1) ) |
1444 | 0 | return; |
1445 | 2 | |
1446 | 2 | uart = &ns16550_com[index]; |
1447 | 2 | |
1448 | 2 | ns16550_init_common(uart); |
1449 | 2 | |
1450 | 2 | uart->baud = (defaults->baud ? : |
1451 | 2 | console_has((index == 0) ? "com1" : "com2") |
1452 | 1 | ? BAUD_AUTO : 0); |
1453 | 2 | uart->data_bits = defaults->data_bits; |
1454 | 2 | uart->parity = parse_parity_char(defaults->parity); |
1455 | 2 | uart->stop_bits = defaults->stop_bits; |
1456 | 2 | uart->irq = defaults->irq; |
1457 | 2 | uart->io_base = defaults->io_base; |
1458 | 2 | uart->io_size = 8; |
1459 | 2 | uart->reg_width = 1; |
1460 | 2 | uart->reg_shift = 0; |
1461 | 2 | |
1462 | 1 | ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2); |
1463 | 2 | } |
1464 | | |
1465 | | #ifdef CONFIG_HAS_DEVICE_TREE |
1466 | | static int __init ns16550_uart_dt_init(struct dt_device_node *dev, |
1467 | | const void *data) |
1468 | | { |
1469 | | struct ns16550 *uart; |
1470 | | int res; |
1471 | | u32 reg_shift, reg_width; |
1472 | | u64 io_size; |
1473 | | |
1474 | | uart = &ns16550_com[0]; |
1475 | | |
1476 | | ns16550_init_common(uart); |
1477 | | |
1478 | | uart->baud = BAUD_AUTO; |
1479 | | uart->data_bits = 8; |
1480 | | uart->parity = UART_PARITY_NONE; |
1481 | | uart->stop_bits = 1; |
1482 | | |
1483 | | res = dt_device_get_address(dev, 0, &uart->io_base, &io_size); |
1484 | | if ( res ) |
1485 | | return res; |
1486 | | |
1487 | | uart->io_size = io_size; |
1488 | | |
1489 | | ASSERT(uart->io_size == io_size); /* Detect truncation */ |
1490 | | |
1491 | | res = dt_property_read_u32(dev, "reg-shift", ®_shift); |
1492 | | if ( !res ) |
1493 | | uart->reg_shift = 0; |
1494 | | else |
1495 | | uart->reg_shift = reg_shift; |
1496 | | |
1497 | | res = dt_property_read_u32(dev, "reg-io-width", ®_width); |
1498 | | if ( !res ) |
1499 | | uart->reg_width = 1; |
1500 | | else |
1501 | | uart->reg_width = reg_width; |
1502 | | |
1503 | | if ( uart->reg_width != 1 && uart->reg_width != 4 ) |
1504 | | return -EINVAL; |
1505 | | |
1506 | | res = platform_get_irq(dev, 0); |
1507 | | if ( ! res ) |
1508 | | return -EINVAL; |
1509 | | uart->irq = res; |
1510 | | |
1511 | | uart->dw_usr_bsy = dt_device_is_compatible(dev, "snps,dw-apb-uart"); |
1512 | | |
1513 | | uart->vuart.base_addr = uart->io_base; |
1514 | | uart->vuart.size = uart->io_size; |
1515 | | uart->vuart.data_off = UART_THR <<uart->reg_shift; |
1516 | | uart->vuart.status_off = UART_LSR<<uart->reg_shift; |
1517 | | uart->vuart.status = UART_LSR_THRE|UART_LSR_TEMT; |
1518 | | |
1519 | | /* Register with generic serial driver. */ |
1520 | | serial_register_uart(uart - ns16550_com, &ns16550_driver, uart); |
1521 | | |
1522 | | dt_device_set_used_by(dev, DOMID_XEN); |
1523 | | |
1524 | | return 0; |
1525 | | } |
1526 | | |
1527 | | static const struct dt_device_match ns16550_dt_match[] __initconst = |
1528 | | { |
1529 | | DT_MATCH_COMPATIBLE("ns16550"), |
1530 | | DT_MATCH_COMPATIBLE("ns16550a"), |
1531 | | DT_MATCH_COMPATIBLE("snps,dw-apb-uart"), |
1532 | | { /* sentinel */ }, |
1533 | | }; |
1534 | | |
1535 | | DT_DEVICE_START(ns16550, "NS16550 UART", DEVICE_SERIAL) |
1536 | | .dt_match = ns16550_dt_match, |
1537 | | .init = ns16550_uart_dt_init, |
1538 | | DT_DEVICE_END |
1539 | | |
1540 | | #endif /* HAS_DEVICE_TREE */ |
1541 | | /* |
1542 | | * Local variables: |
1543 | | * mode: C |
1544 | | * c-file-style: "BSD" |
1545 | | * c-basic-offset: 4 |
1546 | | * tab-width: 4 |
1547 | | * indent-tabs-mode: nil |
1548 | | * End: |
1549 | | */ |