/root/src/xen/xen/include/asm/cpuid-autogen.h

Source
/*
 * Automatically generated by /root/src/xen/xen/tools/gen-cpuid.py - Do not edit!
 * Source data: /root/src/xen/xen/include/public/arch-x86/cpufeatureset.h
 */
#ifndef __XEN_X86__FEATURESET_DATA__
#define __XEN_X86__FEATURESET_DATA__

#define FEATURESET_NR_ENTRIES 10

#define CPUID_COMMON_1D_FEATURES 0x0183f3ffU

#define INIT_KNOWN_FEATURES { \
    0xbfebfbffU, \
    0xfffef3ffU, \
    0xee500800U, \
    0x2469bfffU, \
    0x0000000fU, \
    0xfdbfffffU, \
    0x0040401fU, \
    0x00000500U, \
    0x00000001U, \
    0x0000000cU, \
}

#define INIT_SPECIAL_FEATURES { \
    0x10000200U, \
    0x88200000U, \
    0x00000000U, \
    0x00000002U, \
    0x00000000U, \
    0x00002040U, \
    0x00000010U, \
    0x00000000U, \
    0x00000000U, \
    0x00000000U, \
}

#define INIT_PV_FEATURES { \
    0x1fc9cbf5U, \
    0xf6f83203U, \
    0xe2500800U, \
    0x042109e3U, \
    0x00000007U, \
    0xfdaf0b39U, \
    0x00404003U, \
    0x00000000U, \
    0x00000001U, \
    0x0000000cU, \
}

#define INIT_HVM_SHADOW_FEATURES { \
    0x1fcbfbffU, \
    0xf7f83223U, \
    0xea500800U, \
    0x042189f7U, \
    0x0000000fU, \
    0xfdbf4bbbU, \
    0x00404007U, \
    0x00000000U, \
    0x00000001U, \
    0x0000000cU, \
}

#define INIT_HVM_HAP_FEATURES { \
    0x1fcbfbffU, \
    0xf7fa3223U, \
    0xee500800U, \
    0x042189f7U, \
    0x0000000fU, \
    0xfdbf4fbbU, \
    0x0040400fU, \
    0x00000000U, \
    0x00000001U, \
    0x0000000cU, \
}

#define NR_DEEP_DEPS 19U

#define INIT_DEEP_FEATURES { \
    0x07800259U, \
    0x140a0201U, \
    0xa0000000U, \
    0x00000000U, \
    0x00000000U, \
    0x00010020U, \
    0x00000000U, \
    0x00000000U, \
    0x00000000U, \
    0x00000000U, \
}

#define INIT_DEEP_DEPS { \
    { 0x0U, /* FPU */ { \
        0x00800000U, \
        0x00000000U, \
        0xc0400000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x3U, /* PSE */ { \
        0x00020000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x4U, /* TSC */ { \
        0x00000000U, \
        0x01000000U, \
        0x08000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000002U, \
        0x00000000U, \
        0x00000100U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x6U, /* PAE */ { \
        0x00000000U, \
        0x00022000U, \
        0x24100000U, \
        0x00000001U, \
        0x00000000U, \
        0x00000400U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x9U, /* APIC */ { \
        0x00000000U, \
        0x01200000U, \
        0x00000000U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x17U, /* MMX */ { \
        0x00000000U, \
        0x00000000U, \
        0xc0400000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x18U, /* FXSR */ { \
        0x06000000U, \
        0x021a2201U, \
        0x26000000U, \
        0x000000c1U, \
        0x00000000U, \
        0x20000400U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x19U, /* SSE */ { \
        0x04000000U, \
        0x021a2201U, \
        0x24000000U, \
        0x000000c1U, \
        0x00000000U, \
        0x20000400U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x1aU, /* SSE2 */ { \
        0x00000000U, \
        0x00022000U, \
        0x24000000U, \
        0x00000001U, \
        0x00000000U, \
        0x00000400U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x20U, /* SSE3 */ { \
        0x00000000U, \
        0x00180000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x29U, /* SSSE3 */ { \
        0x00000000U, \
        0x00180000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x31U, /* PCID */ { \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000400U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x33U, /* SSE4_1 */ { \
        0x00000000U, \
        0x00100000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x3aU, /* XSAVE */ { \
        0x00000000U, \
        0x30001000U, \
        0x00000000U, \
        0x00018800U, \
        0x0000000fU, \
        0xdc234020U, \
        0x0000400aU, \
        0x00000000U, \
        0x00000000U, \
        0x0000000cU, \
    }, }, \
    { 0x3cU, /* AVX */ { \
        0x00000000U, \
        0x20001000U, \
        0x00000000U, \
        0x00010800U, \
        0x00000000U, \
        0xdc230020U, \
        0x00004002U, \
        0x00000000U, \
        0x00000000U, \
        0x0000000cU, \
    }, }, \
    { 0x5dU, /* LM */ { \
        0x00000000U, \
        0x00022000U, \
        0x04000000U, \
        0x00000001U, \
        0x00000000U, \
        0x00000400U, \
        0x00000008U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0x5fU, /* 3DNOW */ { \
        0x00000000U, \
        0x00000000U, \
        0x40000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
    }, }, \
    { 0xa5U, /* AVX2 */ { \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0xdc230000U, \
        0x00004002U, \
        0x00000000U, \
        0x00000000U, \
        0x0000000cU, \
    }, }, \
    { 0xb0U, /* AVX512F */ { \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0x00000000U, \
        0xdc220000U, \
        0x00004002U, \
        0x00000000U, \
        0x00000000U, \
        0x0000000cU, \
    }, }, \
}

#define CPUID_BITFIELD_0 \
    bool fpu:1, vme:1, de:1, pse:1, tsc:1, msr:1, pae:1, mce:1, cx8:1, :1, :1, sep:1, mtrr:1, pge:1, mca:1, cmov:1, pat:1, pse36:1, :1, clflush:1, :1, ds:1, acpi:1, mmx:1, fxsr:1, sse:1, sse2:1, ss:1, htt:1, tm1:1, :1, pbe:1

#define CPUID_BITFIELD_1 \
    bool sse3:1, pclmulqdq:1, dtes64:1, monitor:1, dscpl:1, vmx:1, smx:1, eist:1, tm2:1, ssse3:1, :1, :1, fma:1, cx16:1, xtpr:1, pdcm:1, :1, pcid:1, dca:1, sse4_1:1, sse4_2:1, x2apic:1, movbe:1, popcnt:1, tsc_deadline:1, aesni:1, xsave:1, :1, avx:1, f16c:1, rdrand:1, hypervisor:1

#define CPUID_BITFIELD_2 \
    bool :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, syscall:1, :1, :1, :1, :1, :1, :1, :1, :1, nx:1, :1, mmxext:1, :1, :1, ffxsr:1, page1gb:1, rdtscp:1, :1, lm:1, _3dnowext:1, _3dnow:1

#define CPUID_BITFIELD_3 \
    bool lahf_lm:1, cmp_legacy:1, svm:1, extapic:1, cr8_legacy:1, abm:1, sse4a:1, misalignsse:1, _3dnowprefetch:1, osvw:1, ibs:1, xop:1, skinit:1, wdt:1, :1, lwp:1, fma4:1, :1, :1, nodeid_msr:1, :1, tbm:1, topoext:1, :1, :1, :1, dbext:1, :1, :1, monitorx:1, :1, :1

#define CPUID_BITFIELD_4 \
    bool xsaveopt:1, xsavec:1, xgetbv1:1, xsaves:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1

#define CPUID_BITFIELD_5 \
    bool fsgsbase:1, tsc_adjust:1, sgx:1, bmi1:1, hle:1, avx2:1, fdp_excp_only:1, smep:1, bmi2:1, erms:1, invpcid:1, rtm:1, pqm:1, no_fpu_sel:1, mpx:1, pqe:1, avx512f:1, avx512dq:1, rdseed:1, adx:1, smap:1, avx512ifma:1, :1, clflushopt:1, clwb:1, :1, avx512pf:1, avx512er:1, avx512cd:1, sha:1, avx512bw:1, avx512vl:1

#define CPUID_BITFIELD_6 \
    bool prefetchwt1:1, avx512vbmi:1, umip:1, pku:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, avx512_vpopcntdq:1, :1, :1, :1, :1, :1, :1, :1, rdpid:1, :1, :1, :1, :1, :1, :1, :1, :1, :1

#define CPUID_BITFIELD_7 \
    bool :1, :1, :1, :1, :1, :1, :1, :1, itsc:1, :1, efro:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1

#define CPUID_BITFIELD_8 \
    bool clzero:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1

#define CPUID_BITFIELD_9 \
    bool :1, :1, avx512_4vnniw:1, avx512_4fmaps:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1


#endif /* __XEN_X86__FEATURESET_DATA__ */

Coverage Report

Created: 2017-10-25 09:10

Line	Count	Source
1		/*
2		* Automatically generated by /root/src/xen/xen/tools/gen-cpuid.py - Do not edit!
3		* Source data: /root/src/xen/xen/include/public/arch-x86/cpufeatureset.h
4		*/
5		#ifndef __XEN_X86__FEATURESET_DATA__
6		#define __XEN_X86__FEATURESET_DATA__
7
8	529	#define FEATURESET_NR_ENTRIES 10
9
10	2	#define CPUID_COMMON_1D_FEATURES 0x0183f3ffU
11
12		#define INIT_KNOWN_FEATURES { \
13		0xbfebfbffU, \
14		0xfffef3ffU, \
15		0xee500800U, \
16		0x2469bfffU, \
17		0x0000000fU, \
18		0xfdbfffffU, \
19		0x0040401fU, \
20		0x00000500U, \
21		0x00000001U, \
22		0x0000000cU, \
23		}
24
25		#define INIT_SPECIAL_FEATURES { \
26		0x10000200U, \
27		0x88200000U, \
28		0x00000000U, \
29		0x00000002U, \
30		0x00000000U, \
31		0x00002040U, \
32		0x00000010U, \
33		0x00000000U, \
34		0x00000000U, \
35		0x00000000U, \
36		}
37
38		#define INIT_PV_FEATURES { \
39		0x1fc9cbf5U, \
40		0xf6f83203U, \
41		0xe2500800U, \
42		0x042109e3U, \
43		0x00000007U, \
44		0xfdaf0b39U, \
45		0x00404003U, \
46		0x00000000U, \
47		0x00000001U, \
48		0x0000000cU, \
49		}
50
51		#define INIT_HVM_SHADOW_FEATURES { \
52		0x1fcbfbffU, \
53		0xf7f83223U, \
54		0xea500800U, \
55		0x042189f7U, \
56		0x0000000fU, \
57		0xfdbf4bbbU, \
58		0x00404007U, \
59		0x00000000U, \
60		0x00000001U, \
61		0x0000000cU, \
62		}
63
64		#define INIT_HVM_HAP_FEATURES { \
65		0x1fcbfbffU, \
66		0xf7fa3223U, \
67		0xee500800U, \
68		0x042189f7U, \
69		0x0000000fU, \
70		0xfdbf4fbbU, \
71		0x0040400fU, \
72		0x00000000U, \
73		0x00000001U, \
74		0x0000000cU, \
75		}
76
77		#define NR_DEEP_DEPS 19U
78
79		#define INIT_DEEP_FEATURES { \
80		0x07800259U, \
81		0x140a0201U, \
82		0xa0000000U, \
83		0x00000000U, \
84		0x00000000U, \
85		0x00010020U, \
86		0x00000000U, \
87		0x00000000U, \
88		0x00000000U, \
89		0x00000000U, \
90		}
91
92	9	#define INIT_DEEP_DEPS { \
93	9	{ 0x0U, /* FPU */ { \
94	9	0x00800000U, \
95	9	0x00000000U, \
96	9	0xc0400000U, \
97	9	0x00000000U, \
98	9	0x00000000U, \
99	9	0x00000000U, \
100	9	0x00000000U, \
101	9	0x00000000U, \
102	9	0x00000000U, \
103	9	0x00000000U, \
104	9	}, }, \
105	9	{ 0x3U, /* PSE */ { \
106	9	0x00020000U, \
107	9	0x00000000U, \
108	9	0x00000000U, \
109	9	0x00000000U, \
110	9	0x00000000U, \
111	9	0x00000000U, \
112	9	0x00000000U, \
113	9	0x00000000U, \
114	9	0x00000000U, \
115	9	0x00000000U, \
116	9	}, }, \
117	9	{ 0x4U, /* TSC */ { \
118	9	0x00000000U, \
119	9	0x01000000U, \
120	9	0x08000000U, \
121	9	0x00000000U, \
122	9	0x00000000U, \
123	9	0x00000002U, \
124	9	0x00000000U, \
125	9	0x00000100U, \
126	9	0x00000000U, \
127	9	0x00000000U, \
128	9	}, }, \
129	9	{ 0x6U, /* PAE */ { \
130	9	0x00000000U, \
131	9	0x00022000U, \
132	9	0x24100000U, \
133	9	0x00000001U, \
134	9	0x00000000U, \
135	9	0x00000400U, \
136	9	0x00000008U, \
137	9	0x00000000U, \
138	9	0x00000000U, \
139	9	0x00000000U, \
140	9	}, }, \
141	9	{ 0x9U, /* APIC */ { \
142	9	0x00000000U, \
143	9	0x01200000U, \
144	9	0x00000000U, \
145	9	0x00000008U, \
146	9	0x00000000U, \
147	9	0x00000000U, \
148	9	0x00000000U, \
149	9	0x00000000U, \
150	9	0x00000000U, \
151	9	0x00000000U, \
152	9	}, }, \
153	9	{ 0x17U, /* MMX */ { \
154	9	0x00000000U, \
155	9	0x00000000U, \
156	9	0xc0400000U, \
157	9	0x00000000U, \
158	9	0x00000000U, \
159	9	0x00000000U, \
160	9	0x00000000U, \
161	9	0x00000000U, \
162	9	0x00000000U, \
163	9	0x00000000U, \
164	9	}, }, \
165	9	{ 0x18U, /* FXSR */ { \
166	9	0x06000000U, \
167	9	0x021a2201U, \
168	9	0x26000000U, \
169	9	0x000000c1U, \
170	9	0x00000000U, \
171	9	0x20000400U, \
172	9	0x00000008U, \
173	9	0x00000000U, \
174	9	0x00000000U, \
175	9	0x00000000U, \
176	9	}, }, \
177	9	{ 0x19U, /* SSE */ { \
178	9	0x04000000U, \
179	9	0x021a2201U, \
180	9	0x24000000U, \
181	9	0x000000c1U, \
182	9	0x00000000U, \
183	9	0x20000400U, \
184	9	0x00000008U, \
185	9	0x00000000U, \
186	9	0x00000000U, \
187	9	0x00000000U, \
188	9	}, }, \
189	9	{ 0x1aU, /* SSE2 */ { \
190	9	0x00000000U, \
191	9	0x00022000U, \
192	9	0x24000000U, \
193	9	0x00000001U, \
194	9	0x00000000U, \
195	9	0x00000400U, \
196	9	0x00000008U, \
197	9	0x00000000U, \
198	9	0x00000000U, \
199	9	0x00000000U, \
200	9	}, }, \
201	9	{ 0x20U, /* SSE3 */ { \
202	9	0x00000000U, \
203	9	0x00180000U, \
204	9	0x00000000U, \
205	9	0x00000000U, \
206	9	0x00000000U, \
207	9	0x00000000U, \
208	9	0x00000000U, \
209	9	0x00000000U, \
210	9	0x00000000U, \
211	9	0x00000000U, \
212	9	}, }, \
213	9	{ 0x29U, /* SSSE3 */ { \
214	9	0x00000000U, \
215	9	0x00180000U, \
216	9	0x00000000U, \
217	9	0x00000000U, \
218	9	0x00000000U, \
219	9	0x00000000U, \
220	9	0x00000000U, \
221	9	0x00000000U, \
222	9	0x00000000U, \
223	9	0x00000000U, \
224	9	}, }, \
225	9	{ 0x31U, /* PCID */ { \
226	9	0x00000000U, \
227	9	0x00000000U, \
228	9	0x00000000U, \
229	9	0x00000000U, \
230	9	0x00000000U, \
231	9	0x00000400U, \
232	9	0x00000000U, \
233	9	0x00000000U, \
234	9	0x00000000U, \
235	9	0x00000000U, \
236	9	}, }, \
237	9	{ 0x33U, /* SSE4_1 */ { \
238	9	0x00000000U, \
239	9	0x00100000U, \
240	9	0x00000000U, \
241	9	0x00000000U, \
242	9	0x00000000U, \
243	9	0x00000000U, \
244	9	0x00000000U, \
245	9	0x00000000U, \
246	9	0x00000000U, \
247	9	0x00000000U, \
248	9	}, }, \
249	9	{ 0x3aU, /* XSAVE */ { \
250	9	0x00000000U, \
251	9	0x30001000U, \
252	9	0x00000000U, \
253	9	0x00018800U, \
254	9	0x0000000fU, \
255	9	0xdc234020U, \
256	9	0x0000400aU, \
257	9	0x00000000U, \
258	9	0x00000000U, \
259	9	0x0000000cU, \
260	9	}, }, \
261	9	{ 0x3cU, /* AVX */ { \
262	9	0x00000000U, \
263	9	0x20001000U, \
264	9	0x00000000U, \
265	9	0x00010800U, \
266	9	0x00000000U, \
267	9	0xdc230020U, \
268	9	0x00004002U, \
269	9	0x00000000U, \
270	9	0x00000000U, \
271	9	0x0000000cU, \
272	9	}, }, \
273	9	{ 0x5dU, /* LM */ { \
274	9	0x00000000U, \
275	9	0x00022000U, \
276	9	0x04000000U, \
277	9	0x00000001U, \
278	9	0x00000000U, \
279	9	0x00000400U, \
280	9	0x00000008U, \
281	9	0x00000000U, \
282	9	0x00000000U, \
283	9	0x00000000U, \
284	9	}, }, \
285	9	{ 0x5fU, /* 3DNOW */ { \
286	9	0x00000000U, \
287	9	0x00000000U, \
288	9	0x40000000U, \
289	9	0x00000000U, \
290	9	0x00000000U, \
291	9	0x00000000U, \
292	9	0x00000000U, \
293	9	0x00000000U, \
294	9	0x00000000U, \
295	9	0x00000000U, \
296	9	}, }, \
297	9	{ 0xa5U, /* AVX2 */ { \
298	9	0x00000000U, \
299	9	0x00000000U, \
300	9	0x00000000U, \
301	9	0x00000000U, \
302	9	0x00000000U, \
303	9	0xdc230000U, \
304	9	0x00004002U, \
305	9	0x00000000U, \
306	9	0x00000000U, \
307	9	0x0000000cU, \
308	9	}, }, \
309	9	{ 0xb0U, /* AVX512F */ { \
310	9	0x00000000U, \
311	9	0x00000000U, \
312	9	0x00000000U, \
313	9	0x00000000U, \
314	9	0x00000000U, \
315	9	0xdc220000U, \
316	9	0x00004002U, \
317	9	0x00000000U, \
318	9	0x00000000U, \
319	9	0x0000000cU, \
320	9	}, }, \
321	9	}
322
323		#define CPUID_BITFIELD_0 \
324		bool fpu:1, vme:1, de:1, pse:1, tsc:1, msr:1, pae:1, mce:1, cx8:1, :1, :1, sep:1, mtrr:1, pge:1, mca:1, cmov:1, pat:1, pse36:1, :1, clflush:1, :1, ds:1, acpi:1, mmx:1, fxsr:1, sse:1, sse2:1, ss:1, htt:1, tm1:1, :1, pbe:1
325
326		#define CPUID_BITFIELD_1 \
327		bool sse3:1, pclmulqdq:1, dtes64:1, monitor:1, dscpl:1, vmx:1, smx:1, eist:1, tm2:1, ssse3:1, :1, :1, fma:1, cx16:1, xtpr:1, pdcm:1, :1, pcid:1, dca:1, sse4_1:1, sse4_2:1, x2apic:1, movbe:1, popcnt:1, tsc_deadline:1, aesni:1, xsave:1, :1, avx:1, f16c:1, rdrand:1, hypervisor:1
328
329		#define CPUID_BITFIELD_2 \
330		bool :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, syscall:1, :1, :1, :1, :1, :1, :1, :1, :1, nx:1, :1, mmxext:1, :1, :1, ffxsr:1, page1gb:1, rdtscp:1, :1, lm:1, _3dnowext:1, _3dnow:1
331
332		#define CPUID_BITFIELD_3 \
333		bool lahf_lm:1, cmp_legacy:1, svm:1, extapic:1, cr8_legacy:1, abm:1, sse4a:1, misalignsse:1, _3dnowprefetch:1, osvw:1, ibs:1, xop:1, skinit:1, wdt:1, :1, lwp:1, fma4:1, :1, :1, nodeid_msr:1, :1, tbm:1, topoext:1, :1, :1, :1, dbext:1, :1, :1, monitorx:1, :1, :1
334
335		#define CPUID_BITFIELD_4 \
336		bool xsaveopt:1, xsavec:1, xgetbv1:1, xsaves:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1
337
338		#define CPUID_BITFIELD_5 \
339		bool fsgsbase:1, tsc_adjust:1, sgx:1, bmi1:1, hle:1, avx2:1, fdp_excp_only:1, smep:1, bmi2:1, erms:1, invpcid:1, rtm:1, pqm:1, no_fpu_sel:1, mpx:1, pqe:1, avx512f:1, avx512dq:1, rdseed:1, adx:1, smap:1, avx512ifma:1, :1, clflushopt:1, clwb:1, :1, avx512pf:1, avx512er:1, avx512cd:1, sha:1, avx512bw:1, avx512vl:1
340
341		#define CPUID_BITFIELD_6 \
342		bool prefetchwt1:1, avx512vbmi:1, umip:1, pku:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, avx512_vpopcntdq:1, :1, :1, :1, :1, :1, :1, :1, rdpid:1, :1, :1, :1, :1, :1, :1, :1, :1, :1
343
344		#define CPUID_BITFIELD_7 \
345		bool :1, :1, :1, :1, :1, :1, :1, :1, itsc:1, :1, efro:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1
346
347		#define CPUID_BITFIELD_8 \
348		bool clzero:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1
349
350		#define CPUID_BITFIELD_9 \
351		bool :1, :1, avx512_4vnniw:1, avx512_4fmaps:1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1, :1
352
353
354		#endif /* __XEN_X86__FEATURESET_DATA__ */