/root/src/xen/xen/include/asm/hvm/svm/amd-iommu-proto.h
Line | Count | Source (jump to first uncovered line) |
1 | | /* |
2 | | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
3 | | * Author: Leo Duran <leo.duran@amd.com> |
4 | | * Author: Wei Wang <wei.wang2@amd.com> - adapted to xen |
5 | | * |
6 | | * This program is free software; you can redistribute it and/or modify |
7 | | * it under the terms of the GNU General Public License as published by |
8 | | * the Free Software Foundation; either version 2 of the License, or |
9 | | * (at your option) any later version. |
10 | | * |
11 | | * This program is distributed in the hope that it will be useful, |
12 | | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | | * GNU General Public License for more details. |
15 | | * |
16 | | * You should have received a copy of the GNU General Public License |
17 | | * along with this program; If not, see <http://www.gnu.org/licenses/>. |
18 | | */ |
19 | | |
20 | | #ifndef _ASM_X86_64_AMD_IOMMU_PROTO_H |
21 | | #define _ASM_X86_64_AMD_IOMMU_PROTO_H |
22 | | |
23 | | #include <xen/sched.h> |
24 | | #include <asm/amd-iommu.h> |
25 | | #include <asm/apicdef.h> |
26 | | #include <xen/domain_page.h> |
27 | | |
28 | | struct acpi_ivrs_hardware; |
29 | | |
30 | | #define for_each_amd_iommu(amd_iommu) \ |
31 | 0 | list_for_each_entry(amd_iommu, \ |
32 | 0 | &amd_iommu_head, list) |
33 | | |
34 | 0 | #define DMA_32BIT_MASK 0x00000000ffffffffULL |
35 | | |
36 | | #define AMD_IOMMU_DEBUG(fmt, args...) \ |
37 | 0 | do \ |
38 | 0 | { \ |
39 | 0 | if ( iommu_debug ) \ |
40 | 0 | printk(XENLOG_INFO "AMD-Vi: " fmt, ## args); \ |
41 | 0 | } while(0) |
42 | | |
43 | | /* amd-iommu-detect functions */ |
44 | | int amd_iommu_get_ivrs_dev_entries(void); |
45 | | int amd_iommu_get_supported_ivhd_type(void); |
46 | | int amd_iommu_detect_one_acpi(const struct acpi_ivrs_hardware *); |
47 | | int amd_iommu_detect_acpi(void); |
48 | | void get_iommu_features(struct amd_iommu *iommu); |
49 | | |
50 | | /* amd-iommu-init functions */ |
51 | | int amd_iommu_init(void); |
52 | | int amd_iommu_update_ivrs_mapping_acpi(void); |
53 | | |
54 | | /* mapping functions */ |
55 | | int __must_check amd_iommu_map_page(struct domain *d, unsigned long gfn, |
56 | | unsigned long mfn, unsigned int flags); |
57 | | int __must_check amd_iommu_unmap_page(struct domain *d, unsigned long gfn); |
58 | | u64 amd_iommu_get_next_table_from_pte(u32 *entry); |
59 | | int __must_check amd_iommu_alloc_root(struct domain_iommu *hd); |
60 | | int amd_iommu_reserve_domain_unity_map(struct domain *domain, |
61 | | u64 phys_addr, unsigned long size, |
62 | | int iw, int ir); |
63 | | |
64 | | /* Share p2m table with iommu */ |
65 | | void amd_iommu_share_p2m(struct domain *d); |
66 | | |
67 | | /* device table functions */ |
68 | | int get_dma_requestor_id(u16 seg, u16 bdf); |
69 | | void amd_iommu_set_intremap_table( |
70 | | u32 *dte, u64 intremap_ptr, u8 int_valid); |
71 | | void amd_iommu_set_root_page_table( |
72 | | u32 *dte, u64 root_ptr, u16 domain_id, u8 paging_mode, u8 valid); |
73 | | void iommu_dte_set_iotlb(u32 *dte, u8 i); |
74 | | void iommu_dte_add_device_entry(u32 *dte, struct ivrs_mappings *ivrs_dev); |
75 | | void iommu_dte_set_guest_cr3(u32 *dte, u16 dom_id, u64 gcr3, |
76 | | int gv, unsigned int glx); |
77 | | |
78 | | /* send cmd to iommu */ |
79 | | void amd_iommu_flush_all_pages(struct domain *d); |
80 | | void amd_iommu_flush_pages(struct domain *d, unsigned long gfn, |
81 | | unsigned int order); |
82 | | void amd_iommu_flush_iotlb(u8 devfn, const struct pci_dev *pdev, |
83 | | uint64_t gaddr, unsigned int order); |
84 | | void amd_iommu_flush_device(struct amd_iommu *iommu, uint16_t bdf); |
85 | | void amd_iommu_flush_intremap(struct amd_iommu *iommu, uint16_t bdf); |
86 | | void amd_iommu_flush_all_caches(struct amd_iommu *iommu); |
87 | | |
88 | | /* find iommu for bdf */ |
89 | | struct amd_iommu *find_iommu_for_device(int seg, int bdf); |
90 | | |
91 | | /* interrupt remapping */ |
92 | | int amd_iommu_setup_ioapic_remapping(void); |
93 | | void *amd_iommu_alloc_intremap_table(unsigned long **); |
94 | | int amd_iommu_free_intremap_table(u16 seg, struct ivrs_mappings *); |
95 | | void amd_iommu_ioapic_update_ire( |
96 | | unsigned int apic, unsigned int reg, unsigned int value); |
97 | | unsigned int amd_iommu_read_ioapic_from_ire( |
98 | | unsigned int apic, unsigned int reg); |
99 | | int amd_iommu_msi_msg_update_ire( |
100 | | struct msi_desc *msi_desc, struct msi_msg *msg); |
101 | | void amd_iommu_read_msi_from_ire( |
102 | | struct msi_desc *msi_desc, struct msi_msg *msg); |
103 | | int amd_setup_hpet_msi(struct msi_desc *msi_desc); |
104 | | |
105 | | extern struct ioapic_sbdf { |
106 | | u16 bdf, seg; |
107 | | u8 id; |
108 | | bool cmdline; |
109 | | u16 *pin_2_idx; |
110 | | } ioapic_sbdf[MAX_IO_APICS]; |
111 | | |
112 | | extern unsigned int nr_ioapic_sbdf; |
113 | | unsigned int ioapic_id_to_index(unsigned int apic_id); |
114 | | unsigned int get_next_ioapic_sbdf_index(void); |
115 | | |
116 | | extern struct hpet_sbdf { |
117 | | u16 bdf, seg, id; |
118 | | enum { |
119 | | HPET_NONE, |
120 | | HPET_CMDL, |
121 | | HPET_IVHD, |
122 | | } init; |
123 | | } hpet_sbdf; |
124 | | |
125 | | extern void *shared_intremap_table; |
126 | | extern unsigned long *shared_intremap_inuse; |
127 | | |
128 | | /* power management support */ |
129 | | void amd_iommu_resume(void); |
130 | | int __must_check amd_iommu_suspend(void); |
131 | | void amd_iommu_crash_shutdown(void); |
132 | | |
133 | | /* guest iommu support */ |
134 | | void amd_iommu_send_guest_cmd(struct amd_iommu *iommu, u32 cmd[]); |
135 | | void guest_iommu_add_ppr_log(struct domain *d, u32 entry[]); |
136 | | void guest_iommu_add_event_log(struct domain *d, u32 entry[]); |
137 | | int guest_iommu_init(struct domain* d); |
138 | | void guest_iommu_destroy(struct domain *d); |
139 | | int guest_iommu_set_base(struct domain *d, uint64_t base); |
140 | | |
141 | | static inline u32 get_field_from_reg_u32(u32 reg_value, u32 mask, u32 shift) |
142 | 0 | { |
143 | 0 | u32 field; |
144 | 0 | field = (reg_value & mask) >> shift; |
145 | 0 | return field; |
146 | 0 | } Unexecuted instantiation: iommu_init.c:get_field_from_reg_u32 Unexecuted instantiation: pci_amd_iommu.c:get_field_from_reg_u32 Unexecuted instantiation: iommu_intr.c:get_field_from_reg_u32 Unexecuted instantiation: iommu_cmd.c:get_field_from_reg_u32 Unexecuted instantiation: iommu_guest.c:get_field_from_reg_u32 Unexecuted instantiation: p2m.c:get_field_from_reg_u32 Unexecuted instantiation: p2m-pt.c:get_field_from_reg_u32 Unexecuted instantiation: iommu_map.c:get_field_from_reg_u32 |
147 | | |
148 | | static inline u32 set_field_in_reg_u32(u32 field, u32 reg_value, |
149 | | u32 mask, u32 shift, u32 *reg) |
150 | 0 | { |
151 | 0 | reg_value &= ~mask; |
152 | 0 | reg_value |= (field << shift) & mask; |
153 | 0 | if (reg) |
154 | 0 | *reg = reg_value; |
155 | 0 | return reg_value; |
156 | 0 | } Unexecuted instantiation: iommu_map.c:set_field_in_reg_u32 Unexecuted instantiation: pci_amd_iommu.c:set_field_in_reg_u32 Unexecuted instantiation: iommu_intr.c:set_field_in_reg_u32 Unexecuted instantiation: iommu_cmd.c:set_field_in_reg_u32 Unexecuted instantiation: iommu_guest.c:set_field_in_reg_u32 Unexecuted instantiation: p2m.c:set_field_in_reg_u32 Unexecuted instantiation: p2m-pt.c:set_field_in_reg_u32 Unexecuted instantiation: iommu_init.c:set_field_in_reg_u32 |
157 | | |
158 | | static inline u8 get_field_from_byte(u8 value, u8 mask) |
159 | 0 | { |
160 | 0 | return (value & mask) / (mask & -mask); |
161 | 0 | } Unexecuted instantiation: iommu_init.c:get_field_from_byte Unexecuted instantiation: p2m-pt.c:get_field_from_byte Unexecuted instantiation: iommu_map.c:get_field_from_byte Unexecuted instantiation: pci_amd_iommu.c:get_field_from_byte Unexecuted instantiation: iommu_intr.c:get_field_from_byte Unexecuted instantiation: iommu_cmd.c:get_field_from_byte Unexecuted instantiation: iommu_guest.c:get_field_from_byte Unexecuted instantiation: p2m.c:get_field_from_byte |
162 | | |
163 | | static inline unsigned long region_to_pages(unsigned long addr, unsigned long size) |
164 | 0 | { |
165 | 0 | return (PAGE_ALIGN(addr + size) - (addr & PAGE_MASK)) >> PAGE_SHIFT; |
166 | 0 | } Unexecuted instantiation: iommu_map.c:region_to_pages Unexecuted instantiation: iommu_init.c:region_to_pages Unexecuted instantiation: pci_amd_iommu.c:region_to_pages Unexecuted instantiation: iommu_intr.c:region_to_pages Unexecuted instantiation: iommu_cmd.c:region_to_pages Unexecuted instantiation: iommu_guest.c:region_to_pages Unexecuted instantiation: p2m.c:region_to_pages Unexecuted instantiation: p2m-pt.c:region_to_pages |
167 | | |
168 | | static inline struct page_info* alloc_amd_iommu_pgtable(void) |
169 | 0 | { |
170 | 0 | struct page_info *pg; |
171 | 0 | void *vaddr; |
172 | 0 |
|
173 | 0 | pg = alloc_domheap_page(NULL, 0); |
174 | 0 | if ( pg == NULL ) |
175 | 0 | return 0; |
176 | 0 | vaddr = __map_domain_page(pg); |
177 | 0 | memset(vaddr, 0, PAGE_SIZE); |
178 | 0 | unmap_domain_page(vaddr); |
179 | 0 | return pg; |
180 | 0 | } Unexecuted instantiation: p2m.c:alloc_amd_iommu_pgtable Unexecuted instantiation: iommu_init.c:alloc_amd_iommu_pgtable Unexecuted instantiation: iommu_map.c:alloc_amd_iommu_pgtable Unexecuted instantiation: pci_amd_iommu.c:alloc_amd_iommu_pgtable Unexecuted instantiation: p2m-pt.c:alloc_amd_iommu_pgtable Unexecuted instantiation: iommu_cmd.c:alloc_amd_iommu_pgtable Unexecuted instantiation: iommu_guest.c:alloc_amd_iommu_pgtable Unexecuted instantiation: iommu_intr.c:alloc_amd_iommu_pgtable |
181 | | |
182 | | static inline void free_amd_iommu_pgtable(struct page_info *pg) |
183 | 0 | { |
184 | 0 | if ( pg != 0 ) |
185 | 0 | free_domheap_page(pg); |
186 | 0 | } Unexecuted instantiation: iommu_init.c:free_amd_iommu_pgtable Unexecuted instantiation: iommu_map.c:free_amd_iommu_pgtable Unexecuted instantiation: pci_amd_iommu.c:free_amd_iommu_pgtable Unexecuted instantiation: iommu_intr.c:free_amd_iommu_pgtable Unexecuted instantiation: iommu_cmd.c:free_amd_iommu_pgtable Unexecuted instantiation: iommu_guest.c:free_amd_iommu_pgtable Unexecuted instantiation: p2m.c:free_amd_iommu_pgtable Unexecuted instantiation: p2m-pt.c:free_amd_iommu_pgtable |
187 | | |
188 | | static inline void* __alloc_amd_iommu_tables(int order) |
189 | 0 | { |
190 | 0 | void *buf; |
191 | 0 | buf = alloc_xenheap_pages(order, 0); |
192 | 0 | return buf; |
193 | 0 | } Unexecuted instantiation: iommu_map.c:__alloc_amd_iommu_tables Unexecuted instantiation: pci_amd_iommu.c:__alloc_amd_iommu_tables Unexecuted instantiation: iommu_init.c:__alloc_amd_iommu_tables Unexecuted instantiation: p2m-pt.c:__alloc_amd_iommu_tables Unexecuted instantiation: p2m.c:__alloc_amd_iommu_tables Unexecuted instantiation: iommu_guest.c:__alloc_amd_iommu_tables Unexecuted instantiation: iommu_cmd.c:__alloc_amd_iommu_tables Unexecuted instantiation: iommu_intr.c:__alloc_amd_iommu_tables |
194 | | |
195 | | static inline void __free_amd_iommu_tables(void *table, int order) |
196 | 0 | { |
197 | 0 | free_xenheap_pages(table, order); |
198 | 0 | } Unexecuted instantiation: iommu_map.c:__free_amd_iommu_tables Unexecuted instantiation: p2m-pt.c:__free_amd_iommu_tables Unexecuted instantiation: p2m.c:__free_amd_iommu_tables Unexecuted instantiation: iommu_guest.c:__free_amd_iommu_tables Unexecuted instantiation: iommu_init.c:__free_amd_iommu_tables Unexecuted instantiation: iommu_intr.c:__free_amd_iommu_tables Unexecuted instantiation: pci_amd_iommu.c:__free_amd_iommu_tables Unexecuted instantiation: iommu_cmd.c:__free_amd_iommu_tables |
199 | | |
200 | | static inline void iommu_set_bit(uint32_t *reg, uint32_t bit) |
201 | 0 | { |
202 | 0 | set_field_in_reg_u32(IOMMU_CONTROL_ENABLED, *reg, 1U << bit, bit, reg); |
203 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_set_bit Unexecuted instantiation: iommu_cmd.c:iommu_set_bit Unexecuted instantiation: p2m-pt.c:iommu_set_bit Unexecuted instantiation: p2m.c:iommu_set_bit Unexecuted instantiation: iommu_guest.c:iommu_set_bit Unexecuted instantiation: iommu_intr.c:iommu_set_bit Unexecuted instantiation: pci_amd_iommu.c:iommu_set_bit Unexecuted instantiation: iommu_map.c:iommu_set_bit |
204 | | |
205 | | static inline void iommu_clear_bit(uint32_t *reg, uint32_t bit) |
206 | 0 | { |
207 | 0 | set_field_in_reg_u32(IOMMU_CONTROL_DISABLED, *reg, 1U << bit, bit, reg); |
208 | 0 | } Unexecuted instantiation: iommu_cmd.c:iommu_clear_bit Unexecuted instantiation: iommu_init.c:iommu_clear_bit Unexecuted instantiation: p2m.c:iommu_clear_bit Unexecuted instantiation: iommu_guest.c:iommu_clear_bit Unexecuted instantiation: iommu_intr.c:iommu_clear_bit Unexecuted instantiation: pci_amd_iommu.c:iommu_clear_bit Unexecuted instantiation: iommu_map.c:iommu_clear_bit Unexecuted instantiation: p2m-pt.c:iommu_clear_bit |
209 | | |
210 | | static inline uint32_t iommu_get_bit(uint32_t reg, uint32_t bit) |
211 | 0 | { |
212 | 0 | return get_field_from_reg_u32(reg, 1U << bit, bit); |
213 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_get_bit Unexecuted instantiation: iommu_map.c:iommu_get_bit Unexecuted instantiation: pci_amd_iommu.c:iommu_get_bit Unexecuted instantiation: iommu_guest.c:iommu_get_bit Unexecuted instantiation: p2m-pt.c:iommu_get_bit Unexecuted instantiation: p2m.c:iommu_get_bit Unexecuted instantiation: iommu_intr.c:iommu_get_bit Unexecuted instantiation: iommu_cmd.c:iommu_get_bit |
214 | | |
215 | | static inline int iommu_has_cap(struct amd_iommu *iommu, uint32_t bit) |
216 | 0 | { |
217 | 0 | return !!(iommu->cap.header & (1u << bit)); |
218 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_has_cap Unexecuted instantiation: p2m-pt.c:iommu_has_cap Unexecuted instantiation: iommu_map.c:iommu_has_cap Unexecuted instantiation: pci_amd_iommu.c:iommu_has_cap Unexecuted instantiation: iommu_intr.c:iommu_has_cap Unexecuted instantiation: iommu_cmd.c:iommu_has_cap Unexecuted instantiation: iommu_guest.c:iommu_has_cap Unexecuted instantiation: p2m.c:iommu_has_cap |
219 | | |
220 | | static inline int amd_iommu_has_feature(struct amd_iommu *iommu, uint32_t bit) |
221 | 0 | { |
222 | 0 | if ( !iommu_has_cap(iommu, PCI_CAP_EFRSUP_SHIFT) ) |
223 | 0 | return 0; |
224 | 0 | return !!(iommu->features & (1U << bit)); |
225 | 0 | } Unexecuted instantiation: p2m-pt.c:amd_iommu_has_feature Unexecuted instantiation: iommu_guest.c:amd_iommu_has_feature Unexecuted instantiation: iommu_cmd.c:amd_iommu_has_feature Unexecuted instantiation: iommu_intr.c:amd_iommu_has_feature Unexecuted instantiation: pci_amd_iommu.c:amd_iommu_has_feature Unexecuted instantiation: iommu_map.c:amd_iommu_has_feature Unexecuted instantiation: iommu_init.c:amd_iommu_has_feature Unexecuted instantiation: p2m.c:amd_iommu_has_feature |
226 | | |
227 | | /* access tail or head pointer of ring buffer */ |
228 | | static inline uint32_t iommu_get_rb_pointer(uint32_t reg) |
229 | 0 | { |
230 | 0 | return get_field_from_reg_u32(reg, IOMMU_RING_BUFFER_PTR_MASK, |
231 | 0 | IOMMU_RING_BUFFER_PTR_SHIFT); |
232 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_get_rb_pointer Unexecuted instantiation: iommu_map.c:iommu_get_rb_pointer Unexecuted instantiation: pci_amd_iommu.c:iommu_get_rb_pointer Unexecuted instantiation: iommu_intr.c:iommu_get_rb_pointer Unexecuted instantiation: iommu_cmd.c:iommu_get_rb_pointer Unexecuted instantiation: iommu_guest.c:iommu_get_rb_pointer Unexecuted instantiation: p2m.c:iommu_get_rb_pointer Unexecuted instantiation: p2m-pt.c:iommu_get_rb_pointer |
233 | | |
234 | | static inline void iommu_set_rb_pointer(uint32_t *reg, uint32_t val) |
235 | 0 | { |
236 | 0 | set_field_in_reg_u32(val, *reg, IOMMU_RING_BUFFER_PTR_MASK, |
237 | 0 | IOMMU_RING_BUFFER_PTR_SHIFT, reg); |
238 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_set_rb_pointer Unexecuted instantiation: iommu_map.c:iommu_set_rb_pointer Unexecuted instantiation: pci_amd_iommu.c:iommu_set_rb_pointer Unexecuted instantiation: iommu_intr.c:iommu_set_rb_pointer Unexecuted instantiation: iommu_guest.c:iommu_set_rb_pointer Unexecuted instantiation: p2m.c:iommu_set_rb_pointer Unexecuted instantiation: p2m-pt.c:iommu_set_rb_pointer Unexecuted instantiation: iommu_cmd.c:iommu_set_rb_pointer |
239 | | |
240 | | /* access device id field from iommu cmd */ |
241 | | static inline uint16_t iommu_get_devid_from_cmd(uint32_t cmd) |
242 | 0 | { |
243 | 0 | return get_field_from_reg_u32(cmd, IOMMU_CMD_DEVICE_ID_MASK, |
244 | 0 | IOMMU_CMD_DEVICE_ID_SHIFT); |
245 | 0 | } Unexecuted instantiation: p2m-pt.c:iommu_get_devid_from_cmd Unexecuted instantiation: p2m.c:iommu_get_devid_from_cmd Unexecuted instantiation: iommu_guest.c:iommu_get_devid_from_cmd Unexecuted instantiation: iommu_cmd.c:iommu_get_devid_from_cmd Unexecuted instantiation: iommu_intr.c:iommu_get_devid_from_cmd Unexecuted instantiation: pci_amd_iommu.c:iommu_get_devid_from_cmd Unexecuted instantiation: iommu_map.c:iommu_get_devid_from_cmd Unexecuted instantiation: iommu_init.c:iommu_get_devid_from_cmd |
246 | | |
247 | | static inline void iommu_set_devid_to_cmd(uint32_t *cmd, uint16_t id) |
248 | 0 | { |
249 | 0 | set_field_in_reg_u32(id, *cmd, IOMMU_CMD_DEVICE_ID_MASK, |
250 | 0 | IOMMU_CMD_DEVICE_ID_SHIFT, cmd); |
251 | 0 | } Unexecuted instantiation: p2m-pt.c:iommu_set_devid_to_cmd Unexecuted instantiation: iommu_map.c:iommu_set_devid_to_cmd Unexecuted instantiation: pci_amd_iommu.c:iommu_set_devid_to_cmd Unexecuted instantiation: iommu_intr.c:iommu_set_devid_to_cmd Unexecuted instantiation: iommu_cmd.c:iommu_set_devid_to_cmd Unexecuted instantiation: iommu_guest.c:iommu_set_devid_to_cmd Unexecuted instantiation: p2m.c:iommu_set_devid_to_cmd Unexecuted instantiation: iommu_init.c:iommu_set_devid_to_cmd |
252 | | |
253 | | /* access address field from iommu cmd */ |
254 | | static inline uint32_t iommu_get_addr_lo_from_cmd(uint32_t cmd) |
255 | 0 | { |
256 | 0 | return get_field_from_reg_u32(cmd, IOMMU_CMD_ADDR_LOW_MASK, |
257 | 0 | IOMMU_CMD_ADDR_LOW_SHIFT); |
258 | 0 | } Unexecuted instantiation: p2m-pt.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: p2m.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: iommu_guest.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: iommu_cmd.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: iommu_intr.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: pci_amd_iommu.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: iommu_map.c:iommu_get_addr_lo_from_cmd Unexecuted instantiation: iommu_init.c:iommu_get_addr_lo_from_cmd |
259 | | |
260 | | static inline uint32_t iommu_get_addr_hi_from_cmd(uint32_t cmd) |
261 | 0 | { |
262 | 0 | return get_field_from_reg_u32(cmd, IOMMU_CMD_ADDR_LOW_MASK, |
263 | 0 | IOMMU_CMD_ADDR_HIGH_SHIFT); |
264 | 0 | } Unexecuted instantiation: p2m.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: iommu_guest.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: iommu_cmd.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: p2m-pt.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: iommu_intr.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: pci_amd_iommu.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: iommu_map.c:iommu_get_addr_hi_from_cmd Unexecuted instantiation: iommu_init.c:iommu_get_addr_hi_from_cmd |
265 | | |
266 | | /* access address field from event log entry */ |
267 | 0 | #define iommu_get_devid_from_event iommu_get_devid_from_cmd |
268 | | |
269 | | /* access iommu base addresses field from mmio regs */ |
270 | | static inline void iommu_set_addr_lo_to_reg(uint32_t *reg, uint32_t addr) |
271 | 0 | { |
272 | 0 | set_field_in_reg_u32(addr, *reg, IOMMU_REG_BASE_ADDR_LOW_MASK, |
273 | 0 | IOMMU_REG_BASE_ADDR_LOW_SHIFT, reg); |
274 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: iommu_map.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: pci_amd_iommu.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: iommu_intr.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: p2m-pt.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: iommu_guest.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: p2m.c:iommu_set_addr_lo_to_reg Unexecuted instantiation: iommu_cmd.c:iommu_set_addr_lo_to_reg |
275 | | |
276 | | static inline void iommu_set_addr_hi_to_reg(uint32_t *reg, uint32_t addr) |
277 | 0 | { |
278 | 0 | set_field_in_reg_u32(addr, *reg, IOMMU_REG_BASE_ADDR_HIGH_MASK, |
279 | 0 | IOMMU_REG_BASE_ADDR_HIGH_SHIFT, reg); |
280 | 0 | } Unexecuted instantiation: p2m-pt.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: p2m.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: iommu_guest.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: iommu_cmd.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: iommu_intr.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: pci_amd_iommu.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: iommu_map.c:iommu_set_addr_hi_to_reg Unexecuted instantiation: iommu_init.c:iommu_set_addr_hi_to_reg |
281 | | |
282 | | static inline int iommu_is_pte_present(const u32 *entry) |
283 | 0 | { |
284 | 0 | return get_field_from_reg_u32(entry[0], |
285 | 0 | IOMMU_PDE_PRESENT_MASK, |
286 | 0 | IOMMU_PDE_PRESENT_SHIFT); |
287 | 0 | } Unexecuted instantiation: p2m-pt.c:iommu_is_pte_present Unexecuted instantiation: p2m.c:iommu_is_pte_present Unexecuted instantiation: iommu_guest.c:iommu_is_pte_present Unexecuted instantiation: iommu_cmd.c:iommu_is_pte_present Unexecuted instantiation: iommu_intr.c:iommu_is_pte_present Unexecuted instantiation: pci_amd_iommu.c:iommu_is_pte_present Unexecuted instantiation: iommu_map.c:iommu_is_pte_present Unexecuted instantiation: iommu_init.c:iommu_is_pte_present |
288 | | |
289 | | static inline unsigned int iommu_next_level(const u32 *entry) |
290 | 0 | { |
291 | 0 | return get_field_from_reg_u32(entry[0], |
292 | 0 | IOMMU_PDE_NEXT_LEVEL_MASK, |
293 | 0 | IOMMU_PDE_NEXT_LEVEL_SHIFT); |
294 | 0 | } Unexecuted instantiation: iommu_init.c:iommu_next_level Unexecuted instantiation: iommu_map.c:iommu_next_level Unexecuted instantiation: pci_amd_iommu.c:iommu_next_level Unexecuted instantiation: iommu_intr.c:iommu_next_level Unexecuted instantiation: iommu_guest.c:iommu_next_level Unexecuted instantiation: p2m.c:iommu_next_level Unexecuted instantiation: p2m-pt.c:iommu_next_level Unexecuted instantiation: iommu_cmd.c:iommu_next_level |
295 | | |
296 | | #endif /* _ASM_X86_64_AMD_IOMMU_PROTO_H */ |