/root/src/xen/xen/include/asm/x86-defns.h
Line | Count | Source (jump to first uncovered line) |
1 | | #ifndef __XEN_X86_DEFNS_H__ |
2 | | #define __XEN_X86_DEFNS_H__ |
3 | | |
4 | | /* |
5 | | * EFLAGS bits |
6 | | */ |
7 | 0 | #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ |
8 | 5.08M | #define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ |
9 | 0 | #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ |
10 | 0 | #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ |
11 | 0 | #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ |
12 | 0 | #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ |
13 | 497k | #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ |
14 | 174M | #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ |
15 | 97.1k | #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ |
16 | 0 | #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ |
17 | 0 | #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ |
18 | 37.0k | #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ |
19 | 497k | #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ |
20 | 157k | #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ |
21 | 37.0k | #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ |
22 | 0 | #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ |
23 | 0 | #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ |
24 | 0 | #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ |
25 | | |
26 | | #define X86_EFLAGS_ARITH_MASK \ |
27 | 0 | (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ |
28 | 0 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) |
29 | | |
30 | | /* |
31 | | * Intel CPU flags in CR0 |
32 | | */ |
33 | 136k | #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ |
34 | 5.94k | #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ |
35 | 5.94k | #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ |
36 | 169k | #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ |
37 | 7.76k | #define X86_CR0_ET 0x00000010 /* Extension type (RO) */ |
38 | 11.5k | #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ |
39 | 3.87k | #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ |
40 | 3.87k | #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ |
41 | 3.87k | #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ |
42 | 7.80k | #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ |
43 | 43.5k | #define X86_CR0_PG 0x80000000 /* Paging (RW) */ |
44 | | |
45 | | /* |
46 | | * Intel CPU features in CR4 |
47 | | */ |
48 | 99 | #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ |
49 | 99 | #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ |
50 | 100 | #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ |
51 | 100 | #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ |
52 | 269 | #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ |
53 | 16.0k | #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ |
54 | 7.92k | #define X86_CR4_MCE 0x00000040 /* Machine check enable */ |
55 | 40.2k | #define X86_CR4_PGE 0x00000080 /* enable global pages */ |
56 | 98 | #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ |
57 | 101 | #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ |
58 | 101 | #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ |
59 | 0 | #define X86_CR4_UMIP 0x00000800 /* enable UMIP */ |
60 | 7.81k | #define X86_CR4_VMXE 0x00002000 /* enable VMX */ |
61 | | #define X86_CR4_SMXE 0x00004000 /* enable SMX */ |
62 | 102 | #define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ |
63 | 296 | #define X86_CR4_PCIDE 0x00020000 /* enable PCID */ |
64 | 644 | #define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ |
65 | 271 | #define X86_CR4_SMEP 0x00100000 /* enable SMEP */ |
66 | 354 | #define X86_CR4_SMAP 0x00200000 /* enable SMAP */ |
67 | 1.42k | #define X86_CR4_PKE 0x00400000 /* enable PKE */ |
68 | | |
69 | | #endif /* __XEN_X86_DEFNS_H__ */ |