From 460f73851142a2a625ae51750154579e6992fe63 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Thu, 26 Apr 2018 10:56:28 +0100 Subject: [PATCH] x86/AMD: Mitigations for GPZ SP4 - Speculative Store Bypass AMD processors will execute loads and stores with the same base register in program order, which is typically how a compiler emits code. Therefore, by default no mitigating actions are taken, despite there being corner cases which are vulnerable to the issue. For performance testing, or for users with particularly sensitive workloads, the `spec-ctrl=ssbd` command line option is available to force Xen to disable Memory Disambiguation on applicable hardware. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- docs/misc/xen-command-line.markdown | 7 ++++++- xen/arch/x86/cpu/amd.c | 20 ++++++++++++++++++++ xen/arch/x86/spec_ctrl.c | 3 +++ xen/include/asm-x86/spec_ctrl.h | 1 + 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown index 903eab7..e2f4ae3 100644 --- a/docs/misc/xen-command-line.markdown +++ b/docs/misc/xen-command-line.markdown @@ -1399,7 +1399,7 @@ false disable the quirk workaround, which is also the default. ### spec-ctrl (x86) > `= List of [ , xen=, {pv,hvm,msr-sc,rsb}=, -> bti-thunk=retpoline|lfence|jmp, {ibrs,ibpb}= ]` +> bti-thunk=retpoline|lfence|jmp, {ibrs,ibpb,ssbd}= ]` Controls for speculative execution sidechannel mitigations. By default, Xen will pick the most appropriate mitigations based on compiled in support, @@ -1443,6 +1443,11 @@ On hardware supporting IBPB (Indirect Branch Prediction Barrier), the `ibpb=` option can be used to force (the default) or prevent Xen from issuing branch prediction barriers on vcpu context switches. +On hardware supporting SSBD (Speculative Store Bypass Disable), the `ssbd=` +option can be used to force or prevent Xen using the feature itself. On AMD +hardware, this is a global option applied at boot, and not virtualised for +guest use. + ### sync\_console > `= ` diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 9d27e2a..efd943a 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -10,6 +10,7 @@ #include #include #include /* amd_init_cpu */ +#include #include #include @@ -496,6 +497,25 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) c->x86_capability); } + /* + * If the user has explicitly chosen to disable Memory Disambiguation + * to mitigiate Speculative Store Bypass, poke the appropriate MSR. + */ + if (opt_ssbd) { + int bit = -1; + + switch (c->x86) { + case 0x15: bit = 54; break; + case 0x16: bit = 33; break; + case 0x17: bit = 10; break; + } + + if (bit >= 0 && !rdmsr_safe(MSR_AMD64_LS_CFG, value)) { + value |= 1ull << bit; + wrmsr_safe(MSR_AMD64_LS_CFG, value); + } + } + switch(c->x86) { case 0xf ... 0x17: diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index afb6e5a..8df606c 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -43,6 +43,7 @@ static enum ind_thunk { } opt_thunk __initdata = THUNK_DEFAULT; static int8_t __initdata opt_ibrs = -1; bool_t __read_mostly opt_ibpb = 1; +bool_t __read_mostly opt_ssbd; bool_t __initdata bsp_delay_spec_ctrl; uint8_t __read_mostly default_xen_spec_ctrl; @@ -164,6 +165,8 @@ static int __init parse_spec_ctrl(const char *s) opt_ibrs = val; else if ( (val = parse_boolean("ibpb", s, ss)) >= 0 ) opt_ibpb = val; + else if ( (val = parse_boolean("ssbd", s, ss)) >= 0 ) + opt_ssbd = val; else rc = -EINVAL; diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h index d36f0e9..dd084d2 100644 --- a/xen/include/asm-x86/spec_ctrl.h +++ b/xen/include/asm-x86/spec_ctrl.h @@ -27,6 +27,7 @@ void init_speculation_mitigations(void); extern bool_t opt_ibpb; +extern bool_t opt_ssbd; extern bool_t bsp_delay_spec_ctrl; extern uint8_t default_xen_spec_ctrl; -- 2.1.4