MSR load and save lists are a VT-x capability whereby hardware logically performs a rdmsr() from the load list on VMentry, and a wrmsr() to the save list on VMexit.

This facility is used by Xen for a number of MSRs, including the LBR registers if the guest enables MSR_DEBUGCTL.LBR.

On Haswell and later hardware, the LBR format includes two TSX bits (61 and 62) in the LBR entries.

When TSX has been disabled (most usually via microcode), hardware writes LBR records into the MSR load/save area wit the TSX bits cleared. However with TSX disabled, hardware expects the TSX bits to be part of the linear address in the record (i.e. properly sign extended).

Therefore, when an LBR record is generated in the upper canonical region, the value written into the save record by VMexit is not tolerated by the VMentry logic, resulting in a vmentry failure, e.g:

   (XEN) d1v0 vmentry failure (reason 0x80000022): MSR loading (entry 3)
   (XEN)   msr 00000680 val 1fff800000102e60 (mbz 0)

In the affected configuration, Xen must fix up the VMentry load list on every VMentry for the VM to continue to function. This test sets up such a condition, and checks to see whether it keeps running to completion.

See also: tests/lbr-tsx-vmentry/main.c