debuggers.hg

annotate xen/arch/x86/pci-pc.c @ 3658:0ef6e8e6e85d

bitkeeper revision 1.1159.212.71 (4200f0afX_JumfbEHQex6TdFENULMQ)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xen-unstable.bk
into labyrinth.cl.cam.ac.uk:/auto/groups/xeno/users/iap10/xeno-clone/xen-unstable.bk
author iap10@labyrinth.cl.cam.ac.uk
date Wed Feb 02 15:24:31 2005 +0000 (2005-02-02)
parents 51052c8b6456 10a0f6b0a996
children 8472fafee3cf
rev   line source
kaf24@1490 1 /*
kaf24@1490 2 * Low-Level PCI Support for PC
kaf24@1490 3 *
kaf24@1490 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
kaf24@1490 5 */
kaf24@1490 6
kaf24@1490 7 #include <xen/config.h>
kaf24@1490 8 #include <xen/types.h>
kaf24@1490 9 #include <xen/kernel.h>
kaf24@1490 10 #include <xen/sched.h>
kaf24@1490 11 #include <xen/pci.h>
kaf24@1490 12 #include <xen/init.h>
kaf24@1490 13 #include <xen/ioport.h>
kaf24@1490 14 #include <xen/acpi.h>
kaf24@1490 15
kaf24@1490 16 /*#include <asm/segment.h>*/
kaf24@1490 17 #include <asm/io.h>
kaf24@1490 18 #include <asm/smp.h>
kaf24@1490 19 #include <asm/smpboot.h>
kaf24@1490 20
kaf24@1490 21 #include "pci-x86.h"
kaf24@1490 22
kaf24@1490 23 extern int numnodes;
kaf24@1490 24 #define __KERNEL_CS __HYPERVISOR_CS
kaf24@1490 25 #define __KERNEL_DS __HYPERVISOR_DS
kaf24@1490 26
kaf24@1490 27 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
kaf24@1490 28
kaf24@1490 29 int pcibios_last_bus = -1;
kaf24@1490 30 struct pci_bus *pci_root_bus = NULL;
kaf24@1490 31 struct pci_ops *pci_root_ops = NULL;
kaf24@1490 32
kaf24@1490 33 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
kaf24@1490 34 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
kaf24@1490 35
kaf24@1490 36 static int pci_using_acpi_prt = 0;
kaf24@1490 37
kaf24@1490 38 #ifdef CONFIG_MULTIQUAD
kaf24@1490 39 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
kaf24@1490 40 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
kaf24@1490 41 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
kaf24@1490 42 #else
kaf24@1490 43 #define BUS2QUAD(global) (0)
kaf24@1490 44 #define BUS2LOCAL(global) (global)
kaf24@1490 45 #define QUADLOCAL2BUS(quad,local) (local)
kaf24@1490 46 #endif
kaf24@1490 47
kaf24@1490 48 /*
kaf24@1490 49 * This interrupt-safe spinlock protects all accesses to PCI
kaf24@1490 50 * configuration space.
kaf24@1490 51 */
kaf24@1490 52 static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
kaf24@1490 53
kaf24@1490 54
kaf24@1490 55 /*
kaf24@1490 56 * Functions for accessing PCI configuration space with type 1 accesses
kaf24@1490 57 */
kaf24@1490 58
kaf24@1490 59 #ifdef CONFIG_PCI_DIRECT
kaf24@1490 60
kaf24@1490 61 #ifdef CONFIG_MULTIQUAD
kaf24@1490 62 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
kaf24@1490 63 (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
kaf24@1490 64
kaf24@1490 65 static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */
kaf24@1490 66 {
kaf24@1490 67 unsigned long flags;
kaf24@1490 68
kaf24@1490 69 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
kaf24@1490 70 return -EINVAL;
kaf24@1490 71
kaf24@1490 72 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 73
kaf24@1490 74 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
kaf24@1490 75
kaf24@1490 76 switch (len) {
kaf24@1490 77 case 1:
kaf24@1490 78 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
kaf24@1490 79 break;
kaf24@1490 80 case 2:
kaf24@1490 81 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
kaf24@1490 82 break;
kaf24@1490 83 case 4:
kaf24@1490 84 *value = inl_quad(0xCFC, BUS2QUAD(bus));
kaf24@1490 85 break;
kaf24@1490 86 }
kaf24@1490 87
kaf24@1490 88 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 89
kaf24@1490 90 return 0;
kaf24@1490 91 }
kaf24@1490 92
kaf24@1490 93 static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */
kaf24@1490 94 {
kaf24@1490 95 unsigned long flags;
kaf24@1490 96
kaf24@1490 97 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
kaf24@1490 98 return -EINVAL;
kaf24@1490 99
kaf24@1490 100 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 101
kaf24@1490 102 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
kaf24@1490 103
kaf24@1490 104 switch (len) {
kaf24@1490 105 case 1:
kaf24@1490 106 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
kaf24@1490 107 break;
kaf24@1490 108 case 2:
kaf24@1490 109 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
kaf24@1490 110 break;
kaf24@1490 111 case 4:
kaf24@1490 112 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
kaf24@1490 113 break;
kaf24@1490 114 }
kaf24@1490 115
kaf24@1490 116 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 117
kaf24@1490 118 return 0;
kaf24@1490 119 }
kaf24@1490 120
kaf24@1490 121 static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value)
kaf24@1490 122 {
kaf24@1490 123 int result;
kaf24@1490 124 u32 data;
kaf24@1490 125
kaf24@1490 126 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 127 PCI_FUNC(dev->devfn), where, 1, &data);
kaf24@1490 128
kaf24@1490 129 *value = (u8)data;
kaf24@1490 130
kaf24@1490 131 return result;
kaf24@1490 132 }
kaf24@1490 133
kaf24@1490 134 static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value)
kaf24@1490 135 {
kaf24@1490 136 int result;
kaf24@1490 137 u32 data;
kaf24@1490 138
kaf24@1490 139 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 140 PCI_FUNC(dev->devfn), where, 2, &data);
kaf24@1490 141
kaf24@1490 142 *value = (u16)data;
kaf24@1490 143
kaf24@1490 144 return result;
kaf24@1490 145 }
kaf24@1490 146
kaf24@1490 147 static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value)
kaf24@1490 148 {
kaf24@1490 149 if (!value)
kaf24@1490 150 return -EINVAL;
kaf24@1490 151
kaf24@1490 152 return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 153 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 154 }
kaf24@1490 155
kaf24@1490 156 static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value)
kaf24@1490 157 {
kaf24@1490 158 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 159 PCI_FUNC(dev->devfn), where, 1, value);
kaf24@1490 160 }
kaf24@1490 161
kaf24@1490 162 static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value)
kaf24@1490 163 {
kaf24@1490 164 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 165 PCI_FUNC(dev->devfn), where, 2, value);
kaf24@1490 166 }
kaf24@1490 167
kaf24@1490 168 static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value)
kaf24@1490 169 {
kaf24@1490 170 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 171 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 172 }
kaf24@1490 173
kaf24@1490 174 static struct pci_ops pci_direct_mq_conf1 = {
kaf24@1490 175 pci_conf1_read_mq_config_byte,
kaf24@1490 176 pci_conf1_read_mq_config_word,
kaf24@1490 177 pci_conf1_read_mq_config_dword,
kaf24@1490 178 pci_conf1_write_mq_config_byte,
kaf24@1490 179 pci_conf1_write_mq_config_word,
kaf24@1490 180 pci_conf1_write_mq_config_dword
kaf24@1490 181 };
kaf24@1490 182
kaf24@1490 183 #endif /* !CONFIG_MULTIQUAD */
kaf24@1490 184 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
kaf24@1490 185 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
kaf24@1490 186
kaf24@1490 187 static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */
kaf24@1490 188 {
kaf24@1490 189 unsigned long flags;
kaf24@1490 190
kaf24@1490 191 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
kaf24@1490 192 return -EINVAL;
kaf24@1490 193
kaf24@1490 194 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 195
kaf24@1490 196 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
kaf24@1490 197
kaf24@1490 198 switch (len) {
kaf24@1490 199 case 1:
kaf24@1490 200 *value = inb(0xCFC + (reg & 3));
kaf24@1490 201 break;
kaf24@1490 202 case 2:
kaf24@1490 203 *value = inw(0xCFC + (reg & 2));
kaf24@1490 204 break;
kaf24@1490 205 case 4:
kaf24@1490 206 *value = inl(0xCFC);
kaf24@1490 207 break;
kaf24@1490 208 }
kaf24@1490 209
kaf24@1490 210 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 211
kaf24@1490 212 return 0;
kaf24@1490 213 }
kaf24@1490 214
kaf24@1490 215 static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */
kaf24@1490 216 {
kaf24@1490 217 unsigned long flags;
kaf24@1490 218
kaf24@1490 219 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
kaf24@1490 220 return -EINVAL;
kaf24@1490 221
kaf24@1490 222 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 223
kaf24@1490 224 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
kaf24@1490 225
kaf24@1490 226 switch (len) {
kaf24@1490 227 case 1:
kaf24@1490 228 outb((u8)value, 0xCFC + (reg & 3));
kaf24@1490 229 break;
kaf24@1490 230 case 2:
kaf24@1490 231 outw((u16)value, 0xCFC + (reg & 2));
kaf24@1490 232 break;
kaf24@1490 233 case 4:
kaf24@1490 234 outl((u32)value, 0xCFC);
kaf24@1490 235 break;
kaf24@1490 236 }
kaf24@1490 237
kaf24@1490 238 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 239
kaf24@1490 240 return 0;
kaf24@1490 241 }
kaf24@1490 242
kaf24@1490 243 #undef PCI_CONF1_ADDRESS
kaf24@1490 244
kaf24@1490 245 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
kaf24@1490 246 {
kaf24@1490 247 int result;
kaf24@1490 248 u32 data;
kaf24@1490 249
kaf24@1490 250 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 251 PCI_FUNC(dev->devfn), where, 1, &data);
kaf24@1490 252
kaf24@1490 253 *value = (u8)data;
kaf24@1490 254
kaf24@1490 255 return result;
kaf24@1490 256 }
kaf24@1490 257
kaf24@1490 258 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
kaf24@1490 259 {
kaf24@1490 260 int result;
kaf24@1490 261 u32 data;
kaf24@1490 262
kaf24@1490 263 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 264 PCI_FUNC(dev->devfn), where, 2, &data);
kaf24@1490 265
kaf24@1490 266 *value = (u16)data;
kaf24@1490 267
kaf24@1490 268 return result;
kaf24@1490 269 }
kaf24@1490 270
kaf24@1490 271 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
kaf24@1490 272 {
kaf24@1490 273 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 274 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 275 }
kaf24@1490 276
kaf24@1490 277 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
kaf24@1490 278 {
kaf24@1490 279 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 280 PCI_FUNC(dev->devfn), where, 1, value);
kaf24@1490 281 }
kaf24@1490 282
kaf24@1490 283 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
kaf24@1490 284 {
kaf24@1490 285 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 286 PCI_FUNC(dev->devfn), where, 2, value);
kaf24@1490 287 }
kaf24@1490 288
kaf24@1490 289 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
kaf24@1490 290 {
kaf24@1490 291 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 292 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 293 }
kaf24@1490 294
kaf24@1490 295 static struct pci_ops pci_direct_conf1 = {
kaf24@1490 296 pci_conf1_read_config_byte,
kaf24@1490 297 pci_conf1_read_config_word,
kaf24@1490 298 pci_conf1_read_config_dword,
kaf24@1490 299 pci_conf1_write_config_byte,
kaf24@1490 300 pci_conf1_write_config_word,
kaf24@1490 301 pci_conf1_write_config_dword
kaf24@1490 302 };
kaf24@1490 303
kaf24@1490 304
kaf24@1490 305 /*
kaf24@1490 306 * Functions for accessing PCI configuration space with type 2 accesses
kaf24@1490 307 */
kaf24@1490 308
kaf24@1490 309 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
kaf24@1490 310
kaf24@1490 311 static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
kaf24@1490 312 {
kaf24@1490 313 unsigned long flags;
kaf24@1490 314
kaf24@1490 315 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
kaf24@1490 316 return -EINVAL;
kaf24@1490 317
kaf24@1490 318 if (dev & 0x10)
kaf24@1490 319 return PCIBIOS_DEVICE_NOT_FOUND;
kaf24@1490 320
kaf24@1490 321 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 322
kaf24@1490 323 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
kaf24@1490 324 outb((u8)bus, 0xCFA);
kaf24@1490 325
kaf24@1490 326 switch (len) {
kaf24@1490 327 case 1:
kaf24@1490 328 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 329 break;
kaf24@1490 330 case 2:
kaf24@1490 331 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 332 break;
kaf24@1490 333 case 4:
kaf24@1490 334 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 335 break;
kaf24@1490 336 }
kaf24@1490 337
kaf24@1490 338 outb (0, 0xCF8);
kaf24@1490 339
kaf24@1490 340 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 341
kaf24@1490 342 return 0;
kaf24@1490 343 }
kaf24@1490 344
kaf24@1490 345 static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
kaf24@1490 346 {
kaf24@1490 347 unsigned long flags;
kaf24@1490 348
kaf24@1490 349 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
kaf24@1490 350 return -EINVAL;
kaf24@1490 351
kaf24@1490 352 if (dev & 0x10)
kaf24@1490 353 return PCIBIOS_DEVICE_NOT_FOUND;
kaf24@1490 354
kaf24@1490 355 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 356
kaf24@1490 357 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
kaf24@1490 358 outb((u8)bus, 0xCFA);
kaf24@1490 359
kaf24@1490 360 switch (len) {
kaf24@1490 361 case 1:
kaf24@1490 362 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 363 break;
kaf24@1490 364 case 2:
kaf24@1490 365 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 366 break;
kaf24@1490 367 case 4:
kaf24@1490 368 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
kaf24@1490 369 break;
kaf24@1490 370 }
kaf24@1490 371
kaf24@1490 372 outb (0, 0xCF8);
kaf24@1490 373
kaf24@1490 374 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 375
kaf24@1490 376 return 0;
kaf24@1490 377 }
kaf24@1490 378
kaf24@1490 379 #undef PCI_CONF2_ADDRESS
kaf24@1490 380
kaf24@1490 381 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
kaf24@1490 382 {
kaf24@1490 383 int result;
kaf24@1490 384 u32 data;
kaf24@1490 385 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 386 PCI_FUNC(dev->devfn), where, 1, &data);
kaf24@1490 387 *value = (u8)data;
kaf24@1490 388 return result;
kaf24@1490 389 }
kaf24@1490 390
kaf24@1490 391 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
kaf24@1490 392 {
kaf24@1490 393 int result;
kaf24@1490 394 u32 data;
kaf24@1490 395 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 396 PCI_FUNC(dev->devfn), where, 2, &data);
kaf24@1490 397 *value = (u16)data;
kaf24@1490 398 return result;
kaf24@1490 399 }
kaf24@1490 400
kaf24@1490 401 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
kaf24@1490 402 {
kaf24@1490 403 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 404 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 405 }
kaf24@1490 406
kaf24@1490 407 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
kaf24@1490 408 {
kaf24@1490 409 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 410 PCI_FUNC(dev->devfn), where, 1, value);
kaf24@1490 411 }
kaf24@1490 412
kaf24@1490 413 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
kaf24@1490 414 {
kaf24@1490 415 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 416 PCI_FUNC(dev->devfn), where, 2, value);
kaf24@1490 417 }
kaf24@1490 418
kaf24@1490 419 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
kaf24@1490 420 {
kaf24@1490 421 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 422 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 423 }
kaf24@1490 424
kaf24@1490 425 static struct pci_ops pci_direct_conf2 = {
kaf24@1490 426 pci_conf2_read_config_byte,
kaf24@1490 427 pci_conf2_read_config_word,
kaf24@1490 428 pci_conf2_read_config_dword,
kaf24@1490 429 pci_conf2_write_config_byte,
kaf24@1490 430 pci_conf2_write_config_word,
kaf24@1490 431 pci_conf2_write_config_dword
kaf24@1490 432 };
kaf24@1490 433
kaf24@1490 434
kaf24@1490 435 /*
kaf24@1490 436 * Before we decide to use direct hardware access mechanisms, we try to do some
kaf24@1490 437 * trivial checks to ensure it at least _seems_ to be working -- we just test
kaf24@1490 438 * whether bus 00 contains a host bridge (this is similar to checking
kaf24@1490 439 * techniques used in XFree86, but ours should be more reliable since we
kaf24@1490 440 * attempt to make use of direct access hints provided by the PCI BIOS).
kaf24@1490 441 *
kaf24@1490 442 * This should be close to trivial, but it isn't, because there are buggy
kaf24@1490 443 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
kaf24@1490 444 */
kaf24@1490 445 static int __devinit pci_sanity_check(struct pci_ops *o)
kaf24@1490 446 {
kaf24@1490 447 u16 x;
kaf24@1490 448 struct pci_bus bus; /* Fake bus and device */
kaf24@1490 449 struct pci_dev dev;
kaf24@1490 450
kaf24@1490 451 if (pci_probe & PCI_NO_CHECKS)
kaf24@1490 452 return 1;
kaf24@1490 453 bus.number = 0;
kaf24@1490 454 dev.bus = &bus;
kaf24@1490 455 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
kaf24@1490 456 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
kaf24@1490 457 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
kaf24@1490 458 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
kaf24@1490 459 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
kaf24@1490 460 return 1;
kaf24@1490 461 DBG("PCI: Sanity check failed\n");
kaf24@1490 462 return 0;
kaf24@1490 463 }
kaf24@1490 464
kaf24@1490 465 static struct pci_ops * __devinit pci_check_direct(void)
kaf24@1490 466 {
kaf24@1490 467 unsigned int tmp;
kaf24@1490 468 unsigned long flags;
kaf24@1490 469
kaf24@1490 470 __save_flags(flags); __cli();
kaf24@1490 471
kaf24@1490 472 /*
kaf24@1490 473 * Check if configuration type 1 works.
kaf24@1490 474 */
kaf24@1490 475 if (pci_probe & PCI_PROBE_CONF1) {
kaf24@1490 476 outb (0x01, 0xCFB);
kaf24@1490 477 tmp = inl (0xCF8);
kaf24@1490 478 outl (0x80000000, 0xCF8);
kaf24@1490 479 if (inl (0xCF8) == 0x80000000 &&
kaf24@1490 480 pci_sanity_check(&pci_direct_conf1)) {
kaf24@1490 481 outl (tmp, 0xCF8);
kaf24@1490 482 __restore_flags(flags);
kaf24@1490 483 printk(KERN_INFO "PCI: Using configuration type 1\n");
kaf24@1490 484 request_region(0xCF8, 8, "PCI conf1");
kaf24@1490 485
kaf24@1490 486 #ifdef CONFIG_MULTIQUAD
kaf24@1490 487 /* Multi-Quad has an extended PCI Conf1 */
kaf24@1490 488 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
kaf24@1490 489 return &pci_direct_mq_conf1;
kaf24@1490 490 #endif
kaf24@1490 491 return &pci_direct_conf1;
kaf24@1490 492 }
kaf24@1490 493 outl (tmp, 0xCF8);
kaf24@1490 494 }
kaf24@1490 495
kaf24@1490 496 /*
kaf24@1490 497 * Check if configuration type 2 works.
kaf24@1490 498 */
kaf24@1490 499 if (pci_probe & PCI_PROBE_CONF2) {
kaf24@1490 500 outb (0x00, 0xCFB);
kaf24@1490 501 outb (0x00, 0xCF8);
kaf24@1490 502 outb (0x00, 0xCFA);
kaf24@1490 503 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
kaf24@1490 504 pci_sanity_check(&pci_direct_conf2)) {
kaf24@1490 505 __restore_flags(flags);
kaf24@1490 506 printk(KERN_INFO "PCI: Using configuration type 2\n");
kaf24@1490 507 request_region(0xCF8, 4, "PCI conf2");
kaf24@1490 508 return &pci_direct_conf2;
kaf24@1490 509 }
kaf24@1490 510 }
kaf24@1490 511
kaf24@1490 512 __restore_flags(flags);
kaf24@1490 513 return NULL;
kaf24@1490 514 }
kaf24@1490 515
kaf24@1490 516 #endif
kaf24@1490 517
kaf24@1490 518 /*
kaf24@1490 519 * BIOS32 and PCI BIOS handling.
kaf24@1490 520 */
kaf24@1490 521
kaf24@1490 522 #ifdef CONFIG_PCI_BIOS
kaf24@1490 523
kaf24@1490 524 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
kaf24@1490 525 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
kaf24@1490 526 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
kaf24@1490 527 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
kaf24@1490 528 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
kaf24@1490 529 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
kaf24@1490 530 #define PCIBIOS_READ_CONFIG_WORD 0xb109
kaf24@1490 531 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
kaf24@1490 532 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
kaf24@1490 533 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
kaf24@1490 534 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
kaf24@1490 535 #define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
kaf24@1490 536 #define PCIBIOS_SET_PCI_HW_INT 0xb10f
kaf24@1490 537
kaf24@1490 538 /* BIOS32 signature: "_32_" */
kaf24@1490 539 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
kaf24@1490 540
kaf24@1490 541 /* PCI signature: "PCI " */
kaf24@1490 542 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
kaf24@1490 543
kaf24@1490 544 /* PCI service signature: "$PCI" */
kaf24@1490 545 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
kaf24@1490 546
kaf24@1490 547 /* PCI BIOS hardware mechanism flags */
kaf24@1490 548 #define PCIBIOS_HW_TYPE1 0x01
kaf24@1490 549 #define PCIBIOS_HW_TYPE2 0x02
kaf24@1490 550 #define PCIBIOS_HW_TYPE1_SPEC 0x10
kaf24@1490 551 #define PCIBIOS_HW_TYPE2_SPEC 0x20
kaf24@1490 552
kaf24@1490 553 /*
kaf24@1490 554 * This is the standard structure used to identify the entry point
kaf24@1490 555 * to the BIOS32 Service Directory, as documented in
kaf24@1490 556 * Standard BIOS 32-bit Service Directory Proposal
kaf24@1490 557 * Revision 0.4 May 24, 1993
kaf24@1490 558 * Phoenix Technologies Ltd.
kaf24@1490 559 * Norwood, MA
kaf24@1490 560 * and the PCI BIOS specification.
kaf24@1490 561 */
kaf24@1490 562
kaf24@1490 563 union bios32 {
kaf24@1490 564 struct {
kaf24@1490 565 unsigned long signature; /* _32_ */
kaf24@1490 566 unsigned long entry; /* 32 bit physical address */
kaf24@1490 567 unsigned char revision; /* Revision level, 0 */
kaf24@1490 568 unsigned char length; /* Length in paragraphs should be 01 */
kaf24@1490 569 unsigned char checksum; /* All bytes must add up to zero */
kaf24@1490 570 unsigned char reserved[5]; /* Must be zero */
kaf24@1490 571 } fields;
kaf24@1490 572 char chars[16];
kaf24@1490 573 };
kaf24@1490 574
kaf24@1490 575 /*
kaf24@1490 576 * Physical address of the service directory. I don't know if we're
kaf24@1490 577 * allowed to have more than one of these or not, so just in case
kaf24@1490 578 * we'll make pcibios_present() take a memory start parameter and store
kaf24@1490 579 * the array there.
kaf24@1490 580 */
kaf24@1490 581
kaf24@1490 582 static struct {
kaf24@1490 583 unsigned long address;
kaf24@1490 584 unsigned short segment;
kaf24@1490 585 } bios32_indirect = { 0, __KERNEL_CS };
kaf24@1490 586
kaf24@1490 587 /*
kaf24@1490 588 * Returns the entry point for the given service, NULL on error
kaf24@1490 589 */
kaf24@1490 590
kaf24@1490 591 static unsigned long bios32_service(unsigned long service)
kaf24@1490 592 {
kaf24@1490 593 unsigned char return_code; /* %al */
kaf24@1490 594 unsigned long address; /* %ebx */
kaf24@1490 595 unsigned long length; /* %ecx */
kaf24@1490 596 unsigned long entry; /* %edx */
kaf24@1490 597 unsigned long flags;
kaf24@1490 598
kaf24@1490 599 __save_flags(flags); __cli();
kaf24@1490 600 __asm__("lcall *(%%edi); cld"
kaf24@1490 601 : "=a" (return_code),
kaf24@1490 602 "=b" (address),
kaf24@1490 603 "=c" (length),
kaf24@1490 604 "=d" (entry)
kaf24@1490 605 : "0" (service),
kaf24@1490 606 "1" (0),
kaf24@1490 607 "D" (&bios32_indirect));
kaf24@1490 608 __restore_flags(flags);
kaf24@1490 609
kaf24@1490 610 switch (return_code) {
kaf24@1490 611 case 0:
kaf24@1490 612 return address + entry;
kaf24@1490 613 case 0x80: /* Not present */
kaf24@1490 614 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
kaf24@1490 615 return 0;
kaf24@1490 616 default: /* Shouldn't happen */
kaf24@1490 617 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
kaf24@1490 618 service, return_code);
kaf24@1490 619 return 0;
kaf24@1490 620 }
kaf24@1490 621 }
kaf24@1490 622
kaf24@1490 623 static struct {
kaf24@1490 624 unsigned long address;
kaf24@1490 625 unsigned short segment;
kaf24@1490 626 } pci_indirect = { 0, __KERNEL_CS };
kaf24@1490 627
kaf24@1490 628 static int pci_bios_present;
kaf24@1490 629
kaf24@1490 630 static int __devinit check_pcibios(void)
kaf24@1490 631 {
kaf24@1490 632 u32 signature, eax, ebx, ecx;
kaf24@1490 633 u8 status, major_ver, minor_ver, hw_mech;
kaf24@1490 634 unsigned long flags, pcibios_entry;
kaf24@1490 635
kaf24@1490 636 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
kaf24@1490 637 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
kaf24@1490 638
kaf24@1490 639 __save_flags(flags); __cli();
kaf24@1490 640 __asm__(
kaf24@1490 641 "lcall *(%%edi); cld\n\t"
kaf24@1490 642 "jc 1f\n\t"
kaf24@1490 643 "xor %%ah, %%ah\n"
kaf24@1490 644 "1:"
kaf24@1490 645 : "=d" (signature),
kaf24@1490 646 "=a" (eax),
kaf24@1490 647 "=b" (ebx),
kaf24@1490 648 "=c" (ecx)
kaf24@1490 649 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
kaf24@1490 650 "D" (&pci_indirect)
kaf24@1490 651 : "memory");
kaf24@1490 652 __restore_flags(flags);
kaf24@1490 653
kaf24@1490 654 status = (eax >> 8) & 0xff;
kaf24@1490 655 hw_mech = eax & 0xff;
kaf24@1490 656 major_ver = (ebx >> 8) & 0xff;
kaf24@1490 657 minor_ver = ebx & 0xff;
kaf24@1490 658 if (pcibios_last_bus < 0)
kaf24@1490 659 pcibios_last_bus = ecx & 0xff;
kaf24@1490 660 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
kaf24@1490 661 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
kaf24@1490 662 if (status || signature != PCI_SIGNATURE) {
kaf24@1490 663 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
kaf24@1490 664 status, signature);
kaf24@1490 665 return 0;
kaf24@1490 666 }
kaf24@1490 667 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
kaf24@1490 668 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
kaf24@1490 669 #ifdef CONFIG_PCI_DIRECT
kaf24@1490 670 if (!(hw_mech & PCIBIOS_HW_TYPE1))
kaf24@1490 671 pci_probe &= ~PCI_PROBE_CONF1;
kaf24@1490 672 if (!(hw_mech & PCIBIOS_HW_TYPE2))
kaf24@1490 673 pci_probe &= ~PCI_PROBE_CONF2;
kaf24@1490 674 #endif
kaf24@1490 675 return 1;
kaf24@1490 676 }
kaf24@1490 677 return 0;
kaf24@1490 678 }
kaf24@1490 679
kaf24@1490 680 static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
kaf24@1490 681 unsigned short index, unsigned char *bus, unsigned char *device_fn)
kaf24@1490 682 {
kaf24@1490 683 unsigned short bx;
kaf24@1490 684 unsigned short ret;
kaf24@2822 685 unsigned long flags;
kaf24@1490 686
kaf24@2822 687 __save_flags(flags); __cli();
kaf24@1490 688 __asm__("lcall *(%%edi); cld\n\t"
kaf24@1490 689 "jc 1f\n\t"
kaf24@1490 690 "xor %%ah, %%ah\n"
kaf24@1490 691 "1:"
kaf24@1490 692 : "=b" (bx),
kaf24@1490 693 "=a" (ret)
kaf24@1490 694 : "1" (PCIBIOS_FIND_PCI_DEVICE),
kaf24@1490 695 "c" (device_id),
kaf24@1490 696 "d" (vendor),
kaf24@1490 697 "S" ((int) index),
kaf24@1490 698 "D" (&pci_indirect));
kaf24@2822 699 __restore_flags(flags);
kaf24@1490 700 *bus = (bx >> 8) & 0xff;
kaf24@1490 701 *device_fn = bx & 0xff;
kaf24@1490 702 return (int) (ret & 0xff00) >> 8;
kaf24@1490 703 }
kaf24@1490 704
kaf24@1490 705 static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
kaf24@1490 706 {
kaf24@1490 707 unsigned long result = 0;
kaf24@1490 708 unsigned long flags;
kaf24@1490 709 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
kaf24@1490 710
kaf24@1490 711 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
kaf24@1490 712 return -EINVAL;
kaf24@1490 713
kaf24@1490 714 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 715
kaf24@1490 716 switch (len) {
kaf24@1490 717 case 1:
kaf24@1490 718 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 719 "jc 1f\n\t"
kaf24@1490 720 "xor %%ah, %%ah\n"
kaf24@1490 721 "1:"
kaf24@1490 722 : "=c" (*value),
kaf24@1490 723 "=a" (result)
kaf24@1490 724 : "1" (PCIBIOS_READ_CONFIG_BYTE),
kaf24@1490 725 "b" (bx),
kaf24@1490 726 "D" ((long)reg),
kaf24@1490 727 "S" (&pci_indirect));
kaf24@1490 728 break;
kaf24@1490 729 case 2:
kaf24@1490 730 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 731 "jc 1f\n\t"
kaf24@1490 732 "xor %%ah, %%ah\n"
kaf24@1490 733 "1:"
kaf24@1490 734 : "=c" (*value),
kaf24@1490 735 "=a" (result)
kaf24@1490 736 : "1" (PCIBIOS_READ_CONFIG_WORD),
kaf24@1490 737 "b" (bx),
kaf24@1490 738 "D" ((long)reg),
kaf24@1490 739 "S" (&pci_indirect));
kaf24@1490 740 break;
kaf24@1490 741 case 4:
kaf24@1490 742 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 743 "jc 1f\n\t"
kaf24@1490 744 "xor %%ah, %%ah\n"
kaf24@1490 745 "1:"
kaf24@1490 746 : "=c" (*value),
kaf24@1490 747 "=a" (result)
kaf24@1490 748 : "1" (PCIBIOS_READ_CONFIG_DWORD),
kaf24@1490 749 "b" (bx),
kaf24@1490 750 "D" ((long)reg),
kaf24@1490 751 "S" (&pci_indirect));
kaf24@1490 752 break;
kaf24@1490 753 }
kaf24@1490 754
kaf24@1490 755 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 756
kaf24@1490 757 return (int)((result & 0xff00) >> 8);
kaf24@1490 758 }
kaf24@1490 759
kaf24@1490 760 static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
kaf24@1490 761 {
kaf24@1490 762 unsigned long result = 0;
kaf24@1490 763 unsigned long flags;
kaf24@1490 764 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
kaf24@1490 765
kaf24@1490 766 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
kaf24@1490 767 return -EINVAL;
kaf24@1490 768
kaf24@1490 769 spin_lock_irqsave(&pci_config_lock, flags);
kaf24@1490 770
kaf24@1490 771 switch (len) {
kaf24@1490 772 case 1:
kaf24@1490 773 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 774 "jc 1f\n\t"
kaf24@1490 775 "xor %%ah, %%ah\n"
kaf24@1490 776 "1:"
kaf24@1490 777 : "=a" (result)
kaf24@1490 778 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
kaf24@1490 779 "c" (value),
kaf24@1490 780 "b" (bx),
kaf24@1490 781 "D" ((long)reg),
kaf24@1490 782 "S" (&pci_indirect));
kaf24@1490 783 break;
kaf24@1490 784 case 2:
kaf24@1490 785 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 786 "jc 1f\n\t"
kaf24@1490 787 "xor %%ah, %%ah\n"
kaf24@1490 788 "1:"
kaf24@1490 789 : "=a" (result)
kaf24@1490 790 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
kaf24@1490 791 "c" (value),
kaf24@1490 792 "b" (bx),
kaf24@1490 793 "D" ((long)reg),
kaf24@1490 794 "S" (&pci_indirect));
kaf24@1490 795 break;
kaf24@1490 796 case 4:
kaf24@1490 797 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 798 "jc 1f\n\t"
kaf24@1490 799 "xor %%ah, %%ah\n"
kaf24@1490 800 "1:"
kaf24@1490 801 : "=a" (result)
kaf24@1490 802 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
kaf24@1490 803 "c" (value),
kaf24@1490 804 "b" (bx),
kaf24@1490 805 "D" ((long)reg),
kaf24@1490 806 "S" (&pci_indirect));
kaf24@1490 807 break;
kaf24@1490 808 }
kaf24@1490 809
kaf24@1490 810 spin_unlock_irqrestore(&pci_config_lock, flags);
kaf24@1490 811
kaf24@1490 812 return (int)((result & 0xff00) >> 8);
kaf24@1490 813 }
kaf24@1490 814
kaf24@1490 815 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
kaf24@1490 816 {
kaf24@1490 817 int result;
kaf24@1490 818 u32 data;
kaf24@1490 819
kaf24@1490 820 if (!value)
kaf24@1490 821 BUG();
kaf24@1490 822
kaf24@1490 823 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 824 PCI_FUNC(dev->devfn), where, 1, &data);
kaf24@1490 825
kaf24@1490 826 *value = (u8)data;
kaf24@1490 827
kaf24@1490 828 return result;
kaf24@1490 829 }
kaf24@1490 830
kaf24@1490 831 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
kaf24@1490 832 {
kaf24@1490 833 int result;
kaf24@1490 834 u32 data;
kaf24@1490 835
kaf24@1490 836 if (!value)
kaf24@1490 837 BUG();
kaf24@1490 838
kaf24@1490 839 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 840 PCI_FUNC(dev->devfn), where, 2, &data);
kaf24@1490 841
kaf24@1490 842 *value = (u16)data;
kaf24@1490 843
kaf24@1490 844 return result;
kaf24@1490 845 }
kaf24@1490 846
kaf24@1490 847 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
kaf24@1490 848 {
kaf24@1490 849 if (!value)
kaf24@1490 850 BUG();
kaf24@1490 851
kaf24@1490 852 return pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 853 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 854 }
kaf24@1490 855
kaf24@1490 856 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
kaf24@1490 857 {
kaf24@1490 858 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 859 PCI_FUNC(dev->devfn), where, 1, value);
kaf24@1490 860 }
kaf24@1490 861
kaf24@1490 862 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
kaf24@1490 863 {
kaf24@1490 864 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 865 PCI_FUNC(dev->devfn), where, 2, value);
kaf24@1490 866 }
kaf24@1490 867
kaf24@1490 868 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
kaf24@1490 869 {
kaf24@1490 870 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
kaf24@1490 871 PCI_FUNC(dev->devfn), where, 4, value);
kaf24@1490 872 }
kaf24@1490 873
kaf24@1490 874
kaf24@1490 875 /*
kaf24@1490 876 * Function table for BIOS32 access
kaf24@1490 877 */
kaf24@1490 878
kaf24@1490 879 static struct pci_ops pci_bios_access = {
kaf24@1490 880 pci_bios_read_config_byte,
kaf24@1490 881 pci_bios_read_config_word,
kaf24@1490 882 pci_bios_read_config_dword,
kaf24@1490 883 pci_bios_write_config_byte,
kaf24@1490 884 pci_bios_write_config_word,
kaf24@1490 885 pci_bios_write_config_dword
kaf24@1490 886 };
kaf24@1490 887
kaf24@1490 888 /*
kaf24@1490 889 * Try to find PCI BIOS.
kaf24@1490 890 */
kaf24@1490 891
kaf24@1490 892 static struct pci_ops * __devinit pci_find_bios(void)
kaf24@1490 893 {
kaf24@1490 894 union bios32 *check;
kaf24@1490 895 unsigned char sum;
kaf24@1490 896 int i, length;
kaf24@1490 897
kaf24@1490 898 /*
kaf24@1490 899 * Follow the standard procedure for locating the BIOS32 Service
kaf24@1490 900 * directory by scanning the permissible address range from
kaf24@1490 901 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
kaf24@1490 902 */
kaf24@1490 903
kaf24@1490 904 for (check = (union bios32 *) __va(0xe0000);
kaf24@1490 905 check <= (union bios32 *) __va(0xffff0);
kaf24@1490 906 ++check) {
kaf24@1490 907 if (check->fields.signature != BIOS32_SIGNATURE)
kaf24@1490 908 continue;
kaf24@1490 909 length = check->fields.length * 16;
kaf24@1490 910 if (!length)
kaf24@1490 911 continue;
kaf24@1490 912 sum = 0;
kaf24@1490 913 for (i = 0; i < length ; ++i)
kaf24@1490 914 sum += check->chars[i];
kaf24@1490 915 if (sum != 0)
kaf24@1490 916 continue;
kaf24@1490 917 if (check->fields.revision != 0) {
kaf24@1490 918 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
kaf24@1490 919 check->fields.revision, check);
kaf24@1490 920 continue;
kaf24@1490 921 }
kaf24@1490 922 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
kaf24@1490 923 if (check->fields.entry >= 0x100000) {
kaf24@1490 924 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
kaf24@1490 925 return NULL;
kaf24@1490 926 } else {
kaf24@1490 927 unsigned long bios32_entry = check->fields.entry;
kaf24@1490 928 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
kaf24@1490 929 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
kaf24@1490 930 if (check_pcibios())
kaf24@1490 931 return &pci_bios_access;
kaf24@1490 932 }
kaf24@1490 933 break; /* Hopefully more than one BIOS32 cannot happen... */
kaf24@1490 934 }
kaf24@1490 935
kaf24@1490 936 return NULL;
kaf24@1490 937 }
kaf24@1490 938
kaf24@1490 939 /*
kaf24@1490 940 * Sort the device list according to PCI BIOS. Nasty hack, but since some
kaf24@1490 941 * fool forgot to define the `correct' device order in the PCI BIOS specs
kaf24@1490 942 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
kaf24@1490 943 * which used BIOS ordering, we are bound to do this...
kaf24@1490 944 */
kaf24@1490 945
kaf24@1490 946 static void __devinit pcibios_sort(void)
kaf24@1490 947 {
kaf24@1490 948 LIST_HEAD(sorted_devices);
kaf24@1490 949 struct list_head *ln;
kaf24@1490 950 struct pci_dev *dev, *d;
kaf24@1490 951 int idx, found;
kaf24@1490 952 unsigned char bus, devfn;
kaf24@1490 953
kaf24@1490 954 DBG("PCI: Sorting device list...\n");
kaf24@1490 955 while (!list_empty(&pci_devices)) {
kaf24@1490 956 ln = pci_devices.next;
kaf24@1490 957 dev = pci_dev_g(ln);
kaf24@1490 958 idx = found = 0;
kaf24@1490 959 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
kaf24@1490 960 idx++;
kaf24@1490 961 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
kaf24@1490 962 d = pci_dev_g(ln);
kaf24@1490 963 if (d->bus->number == bus && d->devfn == devfn) {
kaf24@1490 964 list_del(&d->global_list);
kaf24@1490 965 list_add_tail(&d->global_list, &sorted_devices);
kaf24@1490 966 if (d == dev)
kaf24@1490 967 found = 1;
kaf24@1490 968 break;
kaf24@1490 969 }
kaf24@1490 970 }
kaf24@1490 971 if (ln == &pci_devices) {
kaf24@1490 972 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
kaf24@1490 973 /*
kaf24@1490 974 * We must not continue scanning as several buggy BIOSes
kaf24@1490 975 * return garbage after the last device. Grr.
kaf24@1490 976 */
kaf24@1490 977 break;
kaf24@1490 978 }
kaf24@1490 979 }
kaf24@1490 980 if (!found) {
kaf24@1490 981 printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
kaf24@1490 982 dev->bus->number, dev->devfn);
kaf24@1490 983 list_del(&dev->global_list);
kaf24@1490 984 list_add_tail(&dev->global_list, &sorted_devices);
kaf24@1490 985 }
kaf24@1490 986 }
kaf24@1490 987 list_splice(&sorted_devices, &pci_devices);
kaf24@1490 988 }
kaf24@1490 989
kaf24@1490 990 /*
kaf24@1490 991 * BIOS Functions for IRQ Routing
kaf24@1490 992 */
kaf24@1490 993
kaf24@1490 994 struct irq_routing_options {
kaf24@1490 995 u16 size;
kaf24@1490 996 struct irq_info *table;
kaf24@1490 997 u16 segment;
kaf24@1490 998 } __attribute__((packed));
kaf24@1490 999
kaf24@1490 1000 struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
kaf24@1490 1001 {
kaf24@1490 1002 struct irq_routing_options opt;
kaf24@1490 1003 struct irq_routing_table *rt = NULL;
kaf24@1490 1004 int ret, map;
kaf24@1490 1005 unsigned long page;
kaf24@2822 1006 unsigned long flags;
kaf24@1490 1007
kaf24@1490 1008 if (!pci_bios_present)
kaf24@1490 1009 return NULL;
kaf24@1958 1010 page = alloc_xenheap_page();
kaf24@1490 1011 if (!page)
kaf24@1490 1012 return NULL;
kaf24@1490 1013 opt.table = (struct irq_info *) page;
kaf24@1490 1014 opt.size = PAGE_SIZE;
kaf24@1490 1015 opt.segment = __KERNEL_DS;
kaf24@1490 1016
kaf24@1490 1017 DBG("PCI: Fetching IRQ routing table... ");
kaf24@2822 1018 __save_flags(flags); __cli();
kaf24@1490 1019 __asm__("push %%es\n\t"
kaf24@1490 1020 "push %%ds\n\t"
kaf24@1490 1021 "pop %%es\n\t"
kaf24@1490 1022 "lcall *(%%esi); cld\n\t"
kaf24@1490 1023 "pop %%es\n\t"
kaf24@1490 1024 "jc 1f\n\t"
kaf24@1490 1025 "xor %%ah, %%ah\n"
kaf24@1490 1026 "1:"
kaf24@1490 1027 : "=a" (ret),
kaf24@1627 1028 "=b" (map)
kaf24@1490 1029 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
kaf24@1490 1030 "1" (0),
kaf24@1627 1031 "D" (&opt),
kaf24@1627 1032 "S" (&pci_indirect)
kaf24@1627 1033 : "memory");
kaf24@2822 1034 __restore_flags(flags);
kaf24@1490 1035 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
kaf24@1490 1036 if (ret & 0xff00)
kaf24@1490 1037 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
kaf24@1490 1038 else if (opt.size) {
iap10@3652 1039 rt = _xmalloc(sizeof(struct irq_routing_table) + opt.size);
kaf24@1490 1040 if (rt) {
kaf24@1490 1041 memset(rt, 0, sizeof(struct irq_routing_table));
kaf24@1490 1042 rt->size = opt.size + sizeof(struct irq_routing_table);
kaf24@1490 1043 rt->exclusive_irqs = map;
kaf24@1490 1044 memcpy(rt->slots, (void *) page, opt.size);
kaf24@1490 1045 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
kaf24@1490 1046 }
kaf24@1490 1047 }
kaf24@1958 1048 free_xenheap_page(page);
kaf24@1490 1049 return rt;
kaf24@1490 1050 }
kaf24@1490 1051
kaf24@1490 1052
kaf24@1490 1053 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
kaf24@1490 1054 {
kaf24@1490 1055 int ret;
kaf24@2822 1056 unsigned long flags;
kaf24@1490 1057
kaf24@2822 1058 __save_flags(flags); __cli();
kaf24@1490 1059 __asm__("lcall *(%%esi); cld\n\t"
kaf24@1490 1060 "jc 1f\n\t"
kaf24@1490 1061 "xor %%ah, %%ah\n"
kaf24@1490 1062 "1:"
kaf24@1490 1063 : "=a" (ret)
kaf24@1490 1064 : "0" (PCIBIOS_SET_PCI_HW_INT),
kaf24@1490 1065 "b" ((dev->bus->number << 8) | dev->devfn),
kaf24@1490 1066 "c" ((irq << 8) | (pin + 10)),
kaf24@1490 1067 "S" (&pci_indirect));
kaf24@2822 1068 __restore_flags(flags);
kaf24@1490 1069 return !(ret & 0xff00);
kaf24@1490 1070 }
kaf24@1490 1071
kaf24@1490 1072 #endif
kaf24@1490 1073
kaf24@1490 1074 /*
kaf24@1490 1075 * Several buggy motherboards address only 16 devices and mirror
kaf24@1490 1076 * them to next 16 IDs. We try to detect this `feature' on all
kaf24@1490 1077 * primary buses (those containing host bridges as they are
kaf24@1490 1078 * expected to be unique) and remove the ghost devices.
kaf24@1490 1079 */
kaf24@1490 1080
kaf24@1490 1081 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
kaf24@1490 1082 {
kaf24@1490 1083 struct list_head *ln, *mn;
kaf24@1490 1084 struct pci_dev *d, *e;
kaf24@1490 1085 int mirror = PCI_DEVFN(16,0);
kaf24@1490 1086 int seen_host_bridge = 0;
kaf24@1490 1087 int i;
kaf24@1490 1088
kaf24@1490 1089 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
kaf24@1490 1090 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
kaf24@1490 1091 d = pci_dev_b(ln);
kaf24@1490 1092 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
kaf24@1490 1093 seen_host_bridge++;
kaf24@1490 1094 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
kaf24@1490 1095 e = pci_dev_b(mn);
kaf24@1490 1096 if (e->devfn != d->devfn + mirror ||
kaf24@1490 1097 e->vendor != d->vendor ||
kaf24@1490 1098 e->device != d->device ||
kaf24@1490 1099 e->class != d->class)
kaf24@1490 1100 continue;
kaf24@1490 1101 for(i=0; i<PCI_NUM_RESOURCES; i++)
kaf24@1490 1102 if (e->resource[i].start != d->resource[i].start ||
kaf24@1490 1103 e->resource[i].end != d->resource[i].end ||
kaf24@1490 1104 e->resource[i].flags != d->resource[i].flags)
kaf24@1490 1105 continue;
kaf24@1490 1106 break;
kaf24@1490 1107 }
kaf24@1490 1108 if (mn == &b->devices)
kaf24@1490 1109 return;
kaf24@1490 1110 }
kaf24@1490 1111 if (!seen_host_bridge)
kaf24@1490 1112 return;
kaf24@1490 1113 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
kaf24@1490 1114
kaf24@1490 1115 ln = &b->devices;
kaf24@1490 1116 while (ln->next != &b->devices) {
kaf24@1490 1117 d = pci_dev_b(ln->next);
kaf24@1490 1118 if (d->devfn >= mirror) {
kaf24@1490 1119 list_del(&d->global_list);
kaf24@1490 1120 list_del(&d->bus_list);
kaf24@1958 1121 xfree(d);
kaf24@1490 1122 } else
kaf24@1490 1123 ln = ln->next;
kaf24@1490 1124 }
kaf24@1490 1125 }
kaf24@1490 1126
kaf24@1490 1127 /*
kaf24@1490 1128 * Discover remaining PCI buses in case there are peer host bridges.
kaf24@1490 1129 * We use the number of last PCI bus provided by the PCI BIOS.
kaf24@1490 1130 */
kaf24@1490 1131 static void __devinit pcibios_fixup_peer_bridges(void)
kaf24@1490 1132 {
kaf24@1490 1133 int n;
kaf24@1490 1134 struct pci_bus bus;
kaf24@1490 1135 struct pci_dev dev;
kaf24@1490 1136 u16 l;
kaf24@1490 1137
kaf24@1490 1138 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
kaf24@1490 1139 return;
kaf24@1490 1140 DBG("PCI: Peer bridge fixup\n");
kaf24@1490 1141 for (n=0; n <= pcibios_last_bus; n++) {
kaf24@1490 1142 if (pci_bus_exists(&pci_root_buses, n))
kaf24@1490 1143 continue;
kaf24@1490 1144 bus.number = n;
kaf24@1490 1145 bus.ops = pci_root_ops;
kaf24@1490 1146 dev.bus = &bus;
kaf24@1490 1147 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
kaf24@1490 1148 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
kaf24@1490 1149 l != 0x0000 && l != 0xffff) {
kaf24@1490 1150 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
kaf24@1490 1151 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
kaf24@1490 1152 pci_scan_bus(n, pci_root_ops, NULL);
kaf24@1490 1153 break;
kaf24@1490 1154 }
kaf24@1490 1155 }
kaf24@1490 1156 }
kaf24@1490 1157
kaf24@1490 1158 /*
kaf24@1490 1159 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
kaf24@1490 1160 */
kaf24@1490 1161
kaf24@1490 1162 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
kaf24@1490 1163 {
kaf24@1490 1164 /*
kaf24@1490 1165 * i450NX -- Find and scan all secondary buses on all PXB's.
kaf24@1490 1166 */
kaf24@1490 1167 int pxb, reg;
kaf24@1490 1168 u8 busno, suba, subb;
kaf24@1490 1169 #ifdef CONFIG_MULTIQUAD
kaf24@1490 1170 int quad = BUS2QUAD(d->bus->number);
kaf24@1490 1171 #endif
kaf24@1490 1172 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
kaf24@1490 1173 reg = 0xd0;
kaf24@1490 1174 for(pxb=0; pxb<2; pxb++) {
kaf24@1490 1175 pci_read_config_byte(d, reg++, &busno);
kaf24@1490 1176 pci_read_config_byte(d, reg++, &suba);
kaf24@1490 1177 pci_read_config_byte(d, reg++, &subb);
kaf24@1490 1178 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
kaf24@1490 1179 if (busno)
kaf24@1490 1180 pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL); /* Bus A */
kaf24@1490 1181 if (suba < subb)
kaf24@1490 1182 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL); /* Bus B */
kaf24@1490 1183 }
kaf24@1490 1184 pcibios_last_bus = -1;
kaf24@1490 1185 }
kaf24@1490 1186
kaf24@1490 1187 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
kaf24@1490 1188 {
kaf24@1490 1189 /*
kaf24@1490 1190 * i450GX and i450KX -- Find and scan all secondary buses.
kaf24@1490 1191 * (called separately for each PCI bridge found)
kaf24@1490 1192 */
kaf24@1490 1193 u8 busno;
kaf24@1490 1194 pci_read_config_byte(d, 0x4a, &busno);
kaf24@1490 1195 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
kaf24@1490 1196 pci_scan_bus(busno, pci_root_ops, NULL);
kaf24@1490 1197 pcibios_last_bus = -1;
kaf24@1490 1198 }
kaf24@1490 1199
kaf24@1490 1200 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
kaf24@1490 1201 {
kaf24@1490 1202 /*
kaf24@1490 1203 * UM8886BF IDE controller sets region type bits incorrectly,
kaf24@1490 1204 * therefore they look like memory despite of them being I/O.
kaf24@1490 1205 */
kaf24@1490 1206 int i;
kaf24@1490 1207
kaf24@1490 1208 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
kaf24@1490 1209 for(i=0; i<4; i++)
kaf24@1490 1210 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
kaf24@1490 1211 }
kaf24@1490 1212
kaf24@1490 1213 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
kaf24@1490 1214 {
kaf24@1490 1215 /*
kaf24@1490 1216 * NCR 53C810 returns class code 0 (at least on some systems).
kaf24@1490 1217 * Fix class to be PCI_CLASS_STORAGE_SCSI
kaf24@1490 1218 */
kaf24@1490 1219 if (!d->class) {
kaf24@1490 1220 printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
kaf24@1490 1221 d->class = PCI_CLASS_STORAGE_SCSI << 8;
kaf24@1490 1222 }
kaf24@1490 1223 }
kaf24@1490 1224
kaf24@1490 1225 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
kaf24@1490 1226 {
kaf24@1490 1227 int i;
kaf24@1490 1228
kaf24@1490 1229 /*
kaf24@1490 1230 * PCI IDE controllers use non-standard I/O port decoding, respect it.
kaf24@1490 1231 */
kaf24@1490 1232 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
kaf24@1490 1233 return;
kaf24@1490 1234 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
kaf24@1490 1235 for(i=0; i<4; i++) {
kaf24@1490 1236 struct resource *r = &d->resource[i];
kaf24@1490 1237 if ((r->start & ~0x80) == 0x374) {
kaf24@1490 1238 r->start |= 2;
kaf24@1490 1239 r->end = r->start;
kaf24@1490 1240 }
kaf24@1490 1241 }
kaf24@1490 1242 }
kaf24@1490 1243
kaf24@1490 1244 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
kaf24@1490 1245 {
kaf24@1490 1246 int i;
kaf24@1490 1247
kaf24@1490 1248 /*
kaf24@1490 1249 * There exist PCI IDE controllers which have utter garbage
kaf24@1490 1250 * in first four base registers. Ignore that.
kaf24@1490 1251 */
kaf24@1490 1252 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
kaf24@1490 1253 for(i=0; i<4; i++)
kaf24@1490 1254 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
kaf24@1490 1255 }
kaf24@1490 1256
kaf24@1490 1257 static void __devinit pci_fixup_latency(struct pci_dev *d)
kaf24@1490 1258 {
kaf24@1490 1259 /*
kaf24@1490 1260 * SiS 5597 and 5598 chipsets require latency timer set to
kaf24@1490 1261 * at most 32 to avoid lockups.
kaf24@1490 1262 */
kaf24@1490 1263 DBG("PCI: Setting max latency to 32\n");
kaf24@1490 1264 pcibios_max_latency = 32;
kaf24@1490 1265 }
kaf24@1490 1266
kaf24@1490 1267 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
kaf24@1490 1268 {
kaf24@1490 1269 /*
kaf24@1490 1270 * PIIX4 ACPI device: hardwired IRQ9
kaf24@1490 1271 */
kaf24@1490 1272 d->irq = 9;
kaf24@1490 1273 }
kaf24@1490 1274
kaf24@1490 1275 /*
kaf24@1490 1276 * Addresses issues with problems in the memory write queue timer in
kaf24@1490 1277 * certain VIA Northbridges. This bugfix is per VIA's specifications,
kaf24@1490 1278 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
kaf24@1490 1279 * to trigger a bug in its integrated ProSavage video card, which
kaf24@1490 1280 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
kaf24@1490 1281 * until VIA can provide us with definitive information on why screen
kaf24@1490 1282 * corruption occurs, and what exactly those bits do.
kaf24@1490 1283 *
kaf24@1490 1284 * VIA 8363,8622,8361 Northbridges:
kaf24@1490 1285 * - bits 5, 6, 7 at offset 0x55 need to be turned off
kaf24@1490 1286 * VIA 8367 (KT266x) Northbridges:
kaf24@1490 1287 * - bits 5, 6, 7 at offset 0x95 need to be turned off
kaf24@1490 1288 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
kaf24@1490 1289 * - bits 6, 7 at offset 0x55 need to be turned off
kaf24@1490 1290 */
kaf24@1490 1291
kaf24@1490 1292 #define VIA_8363_KL133_REVISION_ID 0x81
kaf24@1490 1293 #define VIA_8363_KM133_REVISION_ID 0x84
kaf24@1490 1294
kaf24@1490 1295 static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
kaf24@1490 1296 {
kaf24@1490 1297 u8 v;
kaf24@1490 1298 u8 revision;
kaf24@1490 1299 int where = 0x55;
kaf24@1490 1300 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
kaf24@1490 1301
kaf24@1490 1302 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
kaf24@1490 1303
kaf24@1490 1304 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
kaf24@1490 1305 /* fix pci bus latency issues resulted by NB bios error
kaf24@1490 1306 it appears on bug free^Wreduced kt266x's bios forces
kaf24@1490 1307 NB latency to zero */
kaf24@1490 1308 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
kaf24@1490 1309
kaf24@1490 1310 where = 0x95; /* the memory write queue timer register is
kaf24@1490 1311 different for the KT266x's: 0x95 not 0x55 */
kaf24@1490 1312 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
kaf24@1490 1313 (revision == VIA_8363_KL133_REVISION_ID ||
kaf24@1490 1314 revision == VIA_8363_KM133_REVISION_ID)) {
kaf24@1490 1315 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
kaf24@1490 1316 causes screen corruption on the KL133/KM133 */
kaf24@1490 1317 }
kaf24@1490 1318
kaf24@1490 1319 pci_read_config_byte(d, where, &v);
kaf24@1490 1320 if (v & ~mask) {
kaf24@1490 1321 printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
kaf24@1490 1322 d->device, revision, where, v, mask, v & mask);
kaf24@1490 1323 v &= mask;
kaf24@1490 1324 pci_write_config_byte(d, where, v);
kaf24@1490 1325 }
kaf24@1490 1326 }
kaf24@1490 1327
kaf24@1490 1328 /*
kaf24@1490 1329 * For some reasons Intel decided that certain parts of their
kaf24@1490 1330 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
kaf24@1490 1331 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
kaf24@1490 1332 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
kaf24@1490 1333 * to Intel terminology. These devices do forward all addresses from
kaf24@1490 1334 * system to PCI bus no matter what are their window settings, so they are
kaf24@1490 1335 * "transparent" (or subtractive decoding) from programmers point of view.
kaf24@1490 1336 */
kaf24@1490 1337 static void __init pci_fixup_transparent_bridge(struct pci_dev *dev)
kaf24@1490 1338 {
kaf24@1490 1339 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
kaf24@1490 1340 (dev->device & 0xff00) == 0x2400)
kaf24@1490 1341 dev->transparent = 1;
kaf24@1490 1342 }
kaf24@1490 1343
kaf24@1490 1344 struct pci_fixup pcibios_fixups[] = {
kaf24@1490 1345 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
kaf24@1490 1346 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
kaf24@1490 1347 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
kaf24@1490 1348 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
kaf24@1490 1349 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
kaf24@1490 1350 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
kaf24@1490 1351 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
kaf24@1490 1352 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi },
kaf24@1490 1353 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug },
kaf24@1490 1354 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug },
kaf24@1490 1355 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug },
kaf24@1490 1356 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug },
kaf24@1490 1357 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 },
kaf24@1490 1358 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge },
kaf24@1490 1359 { 0 }
kaf24@1490 1360 };
kaf24@1490 1361
kaf24@1490 1362 /*
kaf24@1490 1363 * Called after each bus is probed, but before its children
kaf24@1490 1364 * are examined.
kaf24@1490 1365 */
kaf24@1490 1366
kaf24@1490 1367 void __devinit pcibios_fixup_bus(struct pci_bus *b)
kaf24@1490 1368 {
kaf24@1490 1369 pcibios_fixup_ghosts(b);
kaf24@1490 1370 pci_read_bridge_bases(b);
kaf24@1490 1371 }
kaf24@1490 1372
kaf24@1490 1373 struct pci_bus * __devinit pcibios_scan_root(int busnum)
kaf24@1490 1374 {
kaf24@1490 1375 struct pci_bus *bus;
kaf24@1490 1376
kaf24@3568 1377 pci_for_each_bus(bus) {
kaf24@1490 1378 if (bus->number == busnum) {
kaf24@1490 1379 /* Already scanned */
kaf24@1490 1380 return bus;
kaf24@1490 1381 }
kaf24@1490 1382 }
kaf24@1490 1383
kaf24@1490 1384 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
kaf24@1490 1385
kaf24@1490 1386 return pci_scan_bus(busnum, pci_root_ops, NULL);
kaf24@1490 1387 }
kaf24@1490 1388
kaf24@1490 1389 void __devinit pcibios_config_init(void)
kaf24@1490 1390 {
kaf24@1490 1391 /*
kaf24@1490 1392 * Try all known PCI access methods. Note that we support using
kaf24@1490 1393 * both PCI BIOS and direct access, with a preference for direct.
kaf24@1490 1394 */
kaf24@1490 1395
kaf24@1490 1396 #ifdef CONFIG_PCI_DIRECT
kaf24@1490 1397 struct pci_ops *tmp = NULL;
kaf24@1490 1398 #endif
kaf24@1490 1399
kaf24@1490 1400
kaf24@1490 1401 #ifdef CONFIG_PCI_BIOS
kaf24@1490 1402 if ((pci_probe & PCI_PROBE_BIOS)
kaf24@1490 1403 && ((pci_root_ops = pci_find_bios()))) {
kaf24@1490 1404 pci_probe |= PCI_BIOS_SORT;
kaf24@1490 1405 pci_bios_present = 1;
kaf24@1490 1406 pci_config_read = pci_bios_read;
kaf24@1490 1407 pci_config_write = pci_bios_write;
kaf24@1490 1408 }
kaf24@1490 1409 #endif
kaf24@1490 1410
kaf24@1490 1411 #ifdef CONFIG_PCI_DIRECT
kaf24@1490 1412 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
kaf24@1490 1413 && (tmp = pci_check_direct())) {
kaf24@1490 1414 pci_root_ops = tmp;
kaf24@1490 1415 if (pci_root_ops == &pci_direct_conf1) {
kaf24@1490 1416 pci_config_read = pci_conf1_read;
kaf24@1490 1417 pci_config_write = pci_conf1_write;
kaf24@1490 1418 }
kaf24@1490 1419 else {
kaf24@1490 1420 pci_config_read = pci_conf2_read;
kaf24@1490 1421 pci_config_write = pci_conf2_write;
kaf24@1490 1422 }
kaf24@1490 1423 }
kaf24@1490 1424 #endif
kaf24@1490 1425
kaf24@1490 1426 return;
kaf24@1490 1427 }
kaf24@1490 1428
kaf24@1490 1429 void __init pcibios_init(void)
kaf24@1490 1430 {
kaf24@1490 1431 int quad;
kaf24@1490 1432
kaf24@1490 1433 if (!pci_root_ops)
kaf24@1490 1434 pcibios_config_init();
kaf24@1490 1435 if (!pci_root_ops) {
kaf24@1490 1436 printk(KERN_WARNING "PCI: System does not support PCI\n");
kaf24@1490 1437 return;
kaf24@1490 1438 }
kaf24@1490 1439
kaf24@1490 1440 pcibios_set_cacheline_size();
kaf24@1490 1441
kaf24@1490 1442 printk(KERN_INFO "PCI: Probing PCI hardware\n");
kaf24@1490 1443 #ifdef CONFIG_ACPI_PCI
kaf24@1490 1444 if (!acpi_noirq && !acpi_pci_irq_init()) {
kaf24@1490 1445 pci_using_acpi_prt = 1;
kaf24@1490 1446 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
kaf24@1490 1447 printk(KERN_INFO "PCI: if you experience problems, try using option 'pci=noacpi' or even 'acpi=off'\n");
kaf24@1490 1448 }
kaf24@1490 1449 #endif
kaf24@1490 1450 if (!pci_using_acpi_prt) {
kaf24@1490 1451 pci_root_bus = pcibios_scan_root(0);
kaf24@1490 1452 pcibios_irq_init();
kaf24@1490 1453 pcibios_fixup_peer_bridges();
kaf24@1490 1454 pcibios_fixup_irqs();
kaf24@1490 1455 }
kaf24@1490 1456 if (clustered_apic_mode && (numnodes > 1)) {
kaf24@1490 1457 for (quad = 1; quad < numnodes; ++quad) {
kaf24@1490 1458 printk("Scanning PCI bus %d for quad %d\n",
kaf24@1490 1459 QUADLOCAL2BUS(quad,0), quad);
kaf24@1490 1460 pci_scan_bus(QUADLOCAL2BUS(quad,0),
kaf24@1490 1461 pci_root_ops, NULL);
kaf24@1490 1462 }
kaf24@1490 1463 }
kaf24@1490 1464
kaf24@1490 1465 pcibios_resource_survey();
kaf24@1490 1466
kaf24@1490 1467 #ifdef CONFIG_PCI_BIOS
kaf24@1490 1468 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
kaf24@1490 1469 pcibios_sort();
kaf24@1490 1470 #endif
kaf24@1490 1471 }
kaf24@1490 1472
kaf24@1490 1473 char * __devinit pcibios_setup(char *str)
kaf24@1490 1474 {
kaf24@1490 1475 if (!strcmp(str, "off")) {
kaf24@1490 1476 pci_probe = 0;
kaf24@1490 1477 return NULL;
kaf24@1490 1478 }
kaf24@1490 1479 #ifdef CONFIG_PCI_BIOS
kaf24@1490 1480 else if (!strcmp(str, "bios")) {
kaf24@1490 1481 pci_probe = PCI_PROBE_BIOS;
kaf24@1490 1482 return NULL;
kaf24@1490 1483 } else if (!strcmp(str, "nobios")) {
kaf24@1490 1484 pci_probe &= ~PCI_PROBE_BIOS;
kaf24@1490 1485 return NULL;
kaf24@1490 1486 } else if (!strcmp(str, "nosort")) {
kaf24@1490 1487 pci_probe |= PCI_NO_SORT;
kaf24@1490 1488 return NULL;
kaf24@1490 1489 } else if (!strcmp(str, "biosirq")) {
kaf24@1490 1490 pci_probe |= PCI_BIOS_IRQ_SCAN;
kaf24@1490 1491 return NULL;
kaf24@1490 1492 }
kaf24@1490 1493 #endif
kaf24@1490 1494 #ifdef CONFIG_PCI_DIRECT
kaf24@1490 1495 else if (!strcmp(str, "conf1")) {
kaf24@1490 1496 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
kaf24@1490 1497 return NULL;
kaf24@1490 1498 }
kaf24@1490 1499 else if (!strcmp(str, "conf2")) {
kaf24@1490 1500 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
kaf24@1490 1501 return NULL;
kaf24@1490 1502 }
kaf24@1490 1503 #endif
kaf24@1490 1504 else if (!strcmp(str, "rom")) {
kaf24@1490 1505 pci_probe |= PCI_ASSIGN_ROMS;
kaf24@1490 1506 return NULL;
kaf24@1490 1507 } else if (!strcmp(str, "assign-busses")) {
kaf24@1490 1508 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
kaf24@1490 1509 return NULL;
kaf24@1490 1510 } else if (!strncmp(str, "irqmask=", 8)) {
kaf24@1490 1511 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
kaf24@1490 1512 return NULL;
kaf24@1490 1513 } else if (!strncmp(str, "lastbus=", 8)) {
kaf24@1490 1514 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
kaf24@1490 1515 return NULL;
kaf24@1490 1516 } else if (!strncmp(str, "noacpi", 6)) {
kaf24@1490 1517 acpi_noirq_set();
kaf24@1490 1518 return NULL;
kaf24@1490 1519 }
kaf24@1490 1520 return str;
kaf24@1490 1521 }
kaf24@1490 1522
kaf24@1490 1523 unsigned int pcibios_assign_all_busses(void)
kaf24@1490 1524 {
kaf24@1490 1525 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
kaf24@1490 1526 }
kaf24@1490 1527
kaf24@1490 1528 int pcibios_enable_device(struct pci_dev *dev, int mask)
kaf24@1490 1529 {
kaf24@1490 1530 int err;
kaf24@1490 1531
kaf24@1490 1532 if ((err = pcibios_enable_resources(dev, mask)) < 0)
kaf24@1490 1533 return err;
kaf24@1490 1534
kaf24@1490 1535 #ifdef CONFIG_ACPI_PCI
kaf24@1490 1536 if (pci_using_acpi_prt) {
kaf24@1490 1537 acpi_pci_irq_enable(dev);
kaf24@1490 1538 return 0;
kaf24@1490 1539 }
kaf24@1490 1540 #endif
kaf24@1490 1541
kaf24@1490 1542 pcibios_enable_irq(dev);
kaf24@1490 1543
kaf24@1490 1544 return 0;
kaf24@1490 1545 }