debuggers.hg

annotate tools/ioemu/iodev/dma.h @ 3680:26a00896163a

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bitkeeper revision 1.1159.240.3 (4202bd17uoTYqnlSeqvW9fHjznmCHg)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xen-unstable.bk
into labyrinth.cl.cam.ac.uk:/auto/groups/xeno/users/iap10/xeno-clone/xen-unstable.bk
author iap10@labyrinth.cl.cam.ac.uk
date Fri Feb 04 00:08:55 2005 +0000 (2005-02-04)
parents 2c56c6b39a48 f89816eaeaad
children d3f0465c034e
rev   line source
iap10@3441 1 /////////////////////////////////////////////////////////////////////////
iap10@3441 2 // $Id: dma.h,v 1.15 2003/05/03 07:41:27 vruppert Exp $
iap10@3441 3 /////////////////////////////////////////////////////////////////////////
iap10@3441 4 //
iap10@3441 5 // Copyright (C) 2002 MandrakeSoft S.A.
iap10@3441 6 //
iap10@3441 7 // MandrakeSoft S.A.
iap10@3441 8 // 43, rue d'Aboukir
iap10@3441 9 // 75002 Paris - France
iap10@3441 10 // http://www.linux-mandrake.com/
iap10@3441 11 // http://www.mandrakesoft.com/
iap10@3441 12 //
iap10@3441 13 // This library is free software; you can redistribute it and/or
iap10@3441 14 // modify it under the terms of the GNU Lesser General Public
iap10@3441 15 // License as published by the Free Software Foundation; either
iap10@3441 16 // version 2 of the License, or (at your option) any later version.
iap10@3441 17 //
iap10@3441 18 // This library is distributed in the hope that it will be useful,
iap10@3441 19 // but WITHOUT ANY WARRANTY; without even the implied warranty of
iap10@3441 20 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
iap10@3441 21 // Lesser General Public License for more details.
iap10@3441 22 //
iap10@3441 23 // You should have received a copy of the GNU Lesser General Public
iap10@3441 24 // License along with this library; if not, write to the Free Software
iap10@3441 25 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
iap10@3441 26
iap10@3441 27
iap10@3441 28 #ifndef _PCDMA_H
iap10@3441 29 #define _PCDMA_H
iap10@3441 30
iap10@3441 31
iap10@3441 32 #if BX_USE_DMA_SMF
iap10@3441 33 # define BX_DMA_SMF static
iap10@3441 34 # define BX_DMA_THIS theDmaDevice->
iap10@3441 35 #else
iap10@3441 36 # define BX_DMA_SMF
iap10@3441 37 # define BX_DMA_THIS this->
iap10@3441 38 #endif
iap10@3441 39
iap10@3441 40
iap10@3441 41
iap10@3441 42 class bx_dma_c : public bx_dma_stub_c {
iap10@3441 43 public:
iap10@3441 44
iap10@3441 45 bx_dma_c();
iap10@3441 46 ~bx_dma_c(void);
iap10@3441 47
iap10@3441 48 virtual void init(void);
iap10@3677 49 virtual void bios_init(void);
iap10@3441 50 virtual void reset(unsigned type);
iap10@3441 51 virtual void raise_HLDA(void);
iap10@3441 52 virtual void set_DRQ(unsigned channel, bx_bool val);
iap10@3441 53 virtual unsigned get_TC(void);
iap10@3441 54
iap10@3441 55 virtual unsigned registerDMA8Channel(unsigned channel,
iap10@3441 56 void (* dmaRead)(Bit8u *data_byte),
iap10@3441 57 void (* dmaWrite)(Bit8u *data_byte),
iap10@3441 58 const char *name);
iap10@3441 59 virtual unsigned registerDMA16Channel(unsigned channel,
iap10@3441 60 void (* dmaRead)(Bit16u *data_word),
iap10@3441 61 void (* dmaWrite)(Bit16u *data_word),
iap10@3441 62 const char *name);
iap10@3441 63 virtual unsigned unregisterDMAChannel(unsigned channel);
iap10@3441 64
iap10@3441 65 private:
iap10@3441 66
iap10@3441 67 static Bit32u read_handler(void *this_ptr, Bit32u address, unsigned io_len);
iap10@3441 68 static void write_handler(void *this_ptr, Bit32u address, Bit32u value, unsigned io_len);
iap10@3441 69 #if !BX_USE_DMA_SMF
iap10@3441 70 Bit32u read( Bit32u address, unsigned io_len) BX_CPP_AttrRegparmN(2);
iap10@3441 71 void write(Bit32u address, Bit32u value, unsigned io_len) BX_CPP_AttrRegparmN(3);
iap10@3441 72 #endif
iap10@3441 73 BX_DMA_SMF void control_HRQ(bx_bool ma_sl);
iap10@3441 74 BX_DMA_SMF void reset_controller(unsigned num);
iap10@3441 75
iap10@3441 76 struct {
iap10@3441 77 bx_bool DRQ[4]; // DMA Request
iap10@3441 78 bx_bool DACK[4]; // DMA Acknowlege
iap10@3441 79
iap10@3441 80 bx_bool mask[4];
iap10@3441 81 bx_bool flip_flop;
iap10@3441 82 Bit8u status_reg;
iap10@3441 83 Bit8u command_reg;
iap10@3441 84 Bit8u request_reg;
iap10@3441 85 Bit8u temporary_reg;
iap10@3441 86 struct {
iap10@3441 87 struct {
iap10@3441 88 Bit8u mode_type;
iap10@3441 89 Bit8u address_decrement;
iap10@3441 90 Bit8u autoinit_enable;
iap10@3441 91 Bit8u transfer_type;
iap10@3441 92 } mode;
iap10@3441 93 Bit16u base_address;
iap10@3441 94 Bit16u current_address;
iap10@3441 95 Bit16u base_count;
iap10@3441 96 Bit16u current_count;
iap10@3441 97 Bit8u page_reg;
iap10@3441 98 bx_bool used;
iap10@3441 99 } chan[4]; /* DMA channels 0..3 */
iap10@3441 100 } s[2]; // state information DMA-1 / DMA-2
iap10@3441 101
iap10@3441 102 bx_bool HLDA; // Hold Acknowlege
iap10@3441 103 bx_bool TC; // Terminal Count
iap10@3441 104
iap10@3441 105 struct {
iap10@3441 106 void (* dmaRead8)(Bit8u *data_byte);
iap10@3441 107 void (* dmaWrite8)(Bit8u *data_byte);
iap10@3441 108 void (* dmaRead16)(Bit16u *data_word);
iap10@3441 109 void (* dmaWrite16)(Bit16u *data_word);
iap10@3441 110 } h[4]; // DMA read and write handlers
iap10@3441 111
iap10@3441 112 };
iap10@3441 113
iap10@3441 114 #endif // #ifndef _PCDMA_H