debuggers.hg

annotate xen/include/asm-x86/smp.h @ 3659:bf2c38625b39

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bitkeeper revision 1.1159.212.72 (42011b79Y7C9nEKFZ5pdQXwp8jC9hw)

More x86/64. Now boot secondary CPUs, but I seem to have problems
executing IRET, so interrupts are fatal.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Wed Feb 02 18:27:05 2005 +0000 (2005-02-02)
parents bd470dc06d31
children bbe8541361dd
rev   line source
kaf24@1490 1 #ifndef __ASM_SMP_H
kaf24@1490 2 #define __ASM_SMP_H
kaf24@1490 3
kaf24@1490 4 #ifndef __ASSEMBLY__
kaf24@1490 5 #include <xen/config.h>
kaf24@1490 6 #include <asm/fixmap.h>
kaf24@1490 7 #include <asm/mpspec.h>
kaf24@1490 8 #include <asm/io_apic.h>
kaf24@1490 9 #include <asm/apic.h>
kaf24@1490 10 #endif
kaf24@1490 11
kaf24@1490 12 #ifdef CONFIG_SMP
kaf24@1490 13 #ifndef __ASSEMBLY__
kaf24@1490 14
kaf24@1490 15 /*
kaf24@1490 16 * Private routines/data
kaf24@1490 17 */
kaf24@1490 18
kaf24@1490 19 extern void smp_alloc_memory(void);
kaf24@1490 20 extern unsigned long phys_cpu_present_map;
kaf24@1490 21 extern unsigned long cpu_online_map;
kaf24@1490 22 extern volatile unsigned long smp_invalidate_needed;
kaf24@1490 23 extern int pic_mode;
kaf24@1490 24 extern int smp_num_siblings;
kaf24@1490 25 extern int cpu_sibling_map[];
kaf24@1490 26
kaf24@1490 27 /*
kaf24@1490 28 * On x86 all CPUs are mapped 1:1 to the APIC space.
kaf24@1490 29 * This simplifies scheduling and IPI sending and
kaf24@1490 30 * compresses data structures.
kaf24@1490 31 */
kaf24@1490 32 static inline int cpu_logical_map(int cpu)
kaf24@1490 33 {
kaf24@1490 34 return cpu;
kaf24@1490 35 }
kaf24@1490 36 static inline int cpu_number_map(int cpu)
kaf24@1490 37 {
kaf24@1490 38 return cpu;
kaf24@1490 39 }
kaf24@1490 40
kaf24@1490 41 /*
kaf24@1490 42 * Some lowlevel functions might want to know about
kaf24@1490 43 * the real APIC ID <-> CPU # mapping.
kaf24@1490 44 */
kaf24@1490 45 #define MAX_APICID 256
kaf24@1490 46 extern volatile int cpu_to_physical_apicid[NR_CPUS];
kaf24@1490 47 extern volatile int physical_apicid_to_cpu[MAX_APICID];
kaf24@1490 48 extern volatile int cpu_to_logical_apicid[NR_CPUS];
kaf24@1490 49 extern volatile int logical_apicid_to_cpu[MAX_APICID];
kaf24@1490 50
kaf24@1490 51 /*
kaf24@1490 52 * General functions that each host system must provide.
kaf24@1490 53 */
kaf24@1490 54
kaf24@1490 55 /*extern void smp_boot_cpus(void);*/
kaf24@1490 56 extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
kaf24@1490 57
kaf24@1490 58 /*
kaf24@1490 59 * This function is needed by all SMP systems. It must _always_ be valid
kaf24@1490 60 * from the initial startup. We map APIC_BASE very early in page_setup(),
kaf24@1490 61 * so this is correct in the x86 case.
kaf24@1490 62 */
kaf24@1490 63
kaf24@1490 64 #define smp_processor_id() (current->processor)
kaf24@1490 65
kaf24@1490 66 static __inline int hard_smp_processor_id(void)
kaf24@1490 67 {
kaf24@1490 68 /* we don't want to mark this access volatile - bad code generation */
kaf24@1490 69 return GET_APIC_ID(*(unsigned *)(APIC_BASE+APIC_ID));
kaf24@1490 70 }
kaf24@1490 71
kaf24@1490 72 static __inline int logical_smp_processor_id(void)
kaf24@1490 73 {
kaf24@1490 74 /* we don't want to mark this access volatile - bad code generation */
kaf24@1490 75 return GET_APIC_LOGICAL_ID(*(unsigned *)(APIC_BASE+APIC_LDR));
kaf24@1490 76 }
kaf24@1490 77
kaf24@1490 78 #endif /* !__ASSEMBLY__ */
kaf24@1490 79
kaf24@1490 80 #define NO_PROC_ID 0xFF /* No processor magic marker */
kaf24@1490 81
kaf24@1490 82 /*
kaf24@1490 83 * This magic constant controls our willingness to transfer
kaf24@1490 84 * a process across CPUs. Such a transfer incurs misses on the L1
kaf24@1490 85 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
kaf24@1490 86 * gut feeling is this will vary by board in value. For a board
kaf24@1490 87 * with separate L2 cache it probably depends also on the RSS, and
kaf24@1490 88 * for a board with shared L2 cache it ought to decay fast as other
kaf24@1490 89 * processes are run.
kaf24@1490 90 */
kaf24@1490 91
kaf24@1490 92 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
kaf24@1490 93
kaf24@1490 94 #endif
kaf24@1490 95 #endif