debuggers.hg

annotate xen/include/asm-x86/processor.h @ 3635:ed902e5c4b49

bitkeeper revision 1.1159.212.62 (41fff40aESe4aWS82z_rLHeonXpxuQ)

More x86/64 stuff.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Tue Feb 01 21:26:34 2005 +0000 (2005-02-01)
parents 578b6c14e635
children a4b03d935138 0ef6e8e6e85d
rev   line source
kaf24@1490 1 /*
kaf24@1518 2 * include/asm-x86/processor.h
kaf24@1490 3 *
kaf24@1490 4 * Copyright (C) 1994 Linus Torvalds
kaf24@1490 5 */
kaf24@1490 6
kaf24@1518 7 #ifndef __ASM_X86_PROCESSOR_H
kaf24@1518 8 #define __ASM_X86_PROCESSOR_H
kaf24@1490 9
kaf24@3079 10 #ifndef __ASSEMBLY__
kaf24@1490 11 #include <asm/page.h>
kaf24@1490 12 #include <asm/types.h>
kaf24@1490 13 #include <asm/cpufeature.h>
kaf24@1490 14 #include <asm/desc.h>
kaf24@1490 15 #include <asm/flushtlb.h>
kaf24@1490 16 #include <asm/pdb.h>
kaf24@1490 17 #include <xen/config.h>
kaf24@1490 18 #include <xen/spinlock.h>
iap10@3328 19 #include <asm/vmx_vmcs.h>
kaf24@2827 20 #include <public/xen.h>
kaf24@3079 21 #endif
kaf24@3079 22
kaf24@3079 23 /*
kaf24@3079 24 * CPU vendor IDs
kaf24@3079 25 */
kaf24@3079 26 #define X86_VENDOR_INTEL 0
kaf24@3079 27 #define X86_VENDOR_CYRIX 1
kaf24@3079 28 #define X86_VENDOR_AMD 2
kaf24@3079 29 #define X86_VENDOR_UMC 3
kaf24@3079 30 #define X86_VENDOR_NEXGEN 4
kaf24@3079 31 #define X86_VENDOR_CENTAUR 5
kaf24@3079 32 #define X86_VENDOR_RISE 6
kaf24@3079 33 #define X86_VENDOR_TRANSMETA 7
kaf24@3079 34 #define X86_VENDOR_NSC 8
kaf24@3079 35 #define X86_VENDOR_SIS 9
kaf24@3232 36 #define X86_VENDOR_NUM 10
kaf24@3079 37 #define X86_VENDOR_UNKNOWN 0xff
kaf24@3079 38
kaf24@3079 39 /*
kaf24@3079 40 * EFLAGS bits
kaf24@3079 41 */
kaf24@3079 42 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
kaf24@3079 43 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
kaf24@3079 44 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
kaf24@3079 45 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
kaf24@3079 46 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
kaf24@3079 47 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
kaf24@3079 48 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
kaf24@3079 49 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
kaf24@3079 50 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
kaf24@3079 51 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
kaf24@3079 52 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
kaf24@3079 53 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
kaf24@3079 54 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
kaf24@3079 55 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
kaf24@3079 56 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
kaf24@3079 57 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
kaf24@3079 58 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
kaf24@3079 59
kaf24@3079 60 /*
kaf24@3079 61 * Intel CPU flags in CR0
kaf24@3079 62 */
kaf24@3079 63 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
kaf24@3079 64 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
kaf24@3079 65 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
kaf24@3079 66 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
kaf24@3079 67 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
kaf24@3079 68 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
kaf24@3079 69 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
kaf24@3079 70 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
kaf24@3079 71 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
kaf24@3079 72 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
kaf24@3079 73
kaf24@3079 74 /*
kaf24@3079 75 * Intel CPU features in CR4
kaf24@3079 76 */
kaf24@3079 77 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
kaf24@3079 78 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
kaf24@3079 79 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
kaf24@3079 80 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
kaf24@3079 81 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
kaf24@3079 82 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
kaf24@3079 83 #define X86_CR4_MCE 0x0040 /* Machine check enable */
kaf24@3079 84 #define X86_CR4_PGE 0x0080 /* enable global pages */
kaf24@3079 85 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
kaf24@3079 86 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
kaf24@3079 87 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
iap10@3328 88 #define X86_CR4_VMXE 0x2000 /* enable VMX */
kaf24@3079 89
kaf24@3079 90 /*
kaf24@3090 91 * Trap/fault mnemonics.
kaf24@3090 92 */
kaf24@3090 93 #define TRAP_divide_error 0
kaf24@3090 94 #define TRAP_debug 1
kaf24@3090 95 #define TRAP_nmi 2
kaf24@3090 96 #define TRAP_int3 3
kaf24@3090 97 #define TRAP_overflow 4
kaf24@3090 98 #define TRAP_bounds 5
kaf24@3090 99 #define TRAP_invalid_op 6
kaf24@3090 100 #define TRAP_no_device 7
kaf24@3090 101 #define TRAP_double_fault 8
kaf24@3090 102 #define TRAP_copro_seg 9
kaf24@3090 103 #define TRAP_invalid_tss 10
kaf24@3090 104 #define TRAP_no_segment 11
kaf24@3090 105 #define TRAP_stack_error 12
kaf24@3090 106 #define TRAP_gp_fault 13
kaf24@3090 107 #define TRAP_page_fault 14
kaf24@3090 108 #define TRAP_spurious_int 15
kaf24@3090 109 #define TRAP_copro_error 16
kaf24@3090 110 #define TRAP_alignment_check 17
kaf24@3090 111 #define TRAP_machine_check 18
kaf24@3090 112 #define TRAP_simd_error 19
kaf24@3633 113 #define TRAP_deferred_nmi 31
kaf24@3090 114
kaf24@3090 115 /*
kaf24@3090 116 * Non-fatal fault/trap handlers return an error code to the caller. If the
kaf24@3090 117 * code is non-zero, it means that either the exception was not due to a fault
kaf24@3090 118 * (i.e., it was a trap) or that the fault has been fixed up so the instruction
kaf24@3090 119 * replay ought to succeed.
kaf24@3090 120 */
kaf24@3090 121 #define EXCRET_not_a_fault 1 /* It was a trap. No instruction replay needed. */
kaf24@3090 122 #define EXCRET_fault_fixed 1 /* It was fault that we fixed: try a replay. */
kaf24@3090 123
kaf24@3090 124 /*
kaf24@3081 125 * 'trap_bounce' flags values.
kaf24@3079 126 */
kaf24@3127 127 #define TBF_EXCEPTION 1
kaf24@3127 128 #define TBF_EXCEPTION_ERRCODE 2
kaf24@3127 129 #define TBF_EXCEPTION_CR2 4
kaf24@3127 130 #define TBF_INTERRUPT 8
kaf24@3127 131 #define TBF_FAILSAFE 16
kaf24@3127 132
kaf24@3127 133 /*
kaf24@3127 134 * thread.flags values.
kaf24@3127 135 */
kaf24@3127 136 #define TF_failsafe_return 1
kaf24@3079 137
kaf24@3079 138 #ifndef __ASSEMBLY__
kaf24@1490 139
kaf24@1543 140 struct domain;
cl349@2957 141 struct exec_domain;
kaf24@1490 142
kaf24@1490 143 /*
kaf24@1490 144 * Default implementation of macro that returns current
kaf24@1490 145 * instruction pointer ("program counter").
kaf24@1490 146 */
kaf24@1518 147 #ifdef __x86_64__
kaf24@1518 148 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
kaf24@1518 149 #else
kaf24@1490 150 #define current_text_addr() \
kaf24@1490 151 ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
kaf24@1518 152 #endif
kaf24@1490 153
kaf24@1490 154 /*
kaf24@1490 155 * CPU type and hardware bug flags. Kept separately for each CPU.
kaf24@1490 156 * Members of this structure are referenced in head.S, so think twice
kaf24@1490 157 * before touching them. [mj]
kaf24@1490 158 */
kaf24@1490 159
kaf24@1490 160 struct cpuinfo_x86 {
kaf24@1490 161 __u8 x86; /* CPU family */
kaf24@1490 162 __u8 x86_vendor; /* CPU vendor */
kaf24@1490 163 __u8 x86_model;
kaf24@1490 164 __u8 x86_mask;
kaf24@1490 165 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
kaf24@1490 166 __u32 x86_capability[NCAPINTS];
kaf24@1490 167 char x86_vendor_id[16];
kaf24@1518 168 int x86_cache_size; /* in KB - for CPUS that support this call */
kaf24@1518 169 int x86_clflush_size;
kaf24@1518 170 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined */
kaf24@1490 171 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
kaf24@1490 172
kaf24@1490 173 /*
kaf24@1490 174 * capabilities of CPUs
kaf24@1490 175 */
kaf24@1490 176
kaf24@1490 177 extern struct cpuinfo_x86 boot_cpu_data;
kaf24@1490 178 extern struct tss_struct init_tss[NR_CPUS];
kaf24@1490 179
kaf24@1490 180 #ifdef CONFIG_SMP
kaf24@1490 181 extern struct cpuinfo_x86 cpu_data[];
kaf24@1490 182 #define current_cpu_data cpu_data[smp_processor_id()]
kaf24@1490 183 #else
kaf24@1490 184 #define cpu_data (&boot_cpu_data)
kaf24@1490 185 #define current_cpu_data boot_cpu_data
kaf24@1490 186 #endif
kaf24@1490 187
kaf24@1490 188 extern char ignore_irq13;
kaf24@1490 189
kaf24@1490 190 extern void identify_cpu(struct cpuinfo_x86 *);
kaf24@1490 191 extern void print_cpu_info(struct cpuinfo_x86 *);
kaf24@1490 192 extern void dodgy_tsc(void);
kaf24@1490 193
kaf24@1490 194 /*
kaf24@1490 195 * Generic CPUID function
kaf24@1490 196 */
kaf24@1490 197 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
kaf24@1490 198 {
kaf24@1490 199 __asm__("cpuid"
kaf24@1490 200 : "=a" (*eax),
kaf24@1490 201 "=b" (*ebx),
kaf24@1490 202 "=c" (*ecx),
kaf24@1490 203 "=d" (*edx)
kaf24@1490 204 : "0" (op));
kaf24@1490 205 }
kaf24@1490 206
kaf24@1490 207 /*
kaf24@1490 208 * CPUID functions returning a single datum
kaf24@1490 209 */
kaf24@1490 210 static inline unsigned int cpuid_eax(unsigned int op)
kaf24@1490 211 {
kaf24@1490 212 unsigned int eax;
kaf24@1490 213
kaf24@1490 214 __asm__("cpuid"
kaf24@1490 215 : "=a" (eax)
kaf24@1490 216 : "0" (op)
kaf24@1490 217 : "bx", "cx", "dx");
kaf24@1490 218 return eax;
kaf24@1490 219 }
kaf24@1490 220 static inline unsigned int cpuid_ebx(unsigned int op)
kaf24@1490 221 {
kaf24@1490 222 unsigned int eax, ebx;
kaf24@1490 223
kaf24@1490 224 __asm__("cpuid"
kaf24@1490 225 : "=a" (eax), "=b" (ebx)
kaf24@1490 226 : "0" (op)
kaf24@1490 227 : "cx", "dx" );
kaf24@1490 228 return ebx;
kaf24@1490 229 }
kaf24@1490 230 static inline unsigned int cpuid_ecx(unsigned int op)
kaf24@1490 231 {
kaf24@1490 232 unsigned int eax, ecx;
kaf24@1490 233
kaf24@1490 234 __asm__("cpuid"
kaf24@1490 235 : "=a" (eax), "=c" (ecx)
kaf24@1490 236 : "0" (op)
kaf24@1490 237 : "bx", "dx" );
kaf24@1490 238 return ecx;
kaf24@1490 239 }
kaf24@1490 240 static inline unsigned int cpuid_edx(unsigned int op)
kaf24@1490 241 {
kaf24@1490 242 unsigned int eax, edx;
kaf24@1490 243
kaf24@1490 244 __asm__("cpuid"
kaf24@1490 245 : "=a" (eax), "=d" (edx)
kaf24@1490 246 : "0" (op)
kaf24@1490 247 : "bx", "cx");
kaf24@1490 248 return edx;
kaf24@1490 249 }
kaf24@1490 250
kaf24@1490 251
kaf24@1490 252 #define read_cr0() ({ \
kaf24@1518 253 unsigned long __dummy; \
kaf24@1490 254 __asm__( \
kaf24@1518 255 "mov"__OS" %%cr0,%0\n\t" \
kaf24@1490 256 :"=r" (__dummy)); \
kaf24@1490 257 __dummy; \
kaf24@1490 258 })
kaf24@1490 259
kaf24@1490 260 #define write_cr0(x) \
kaf24@3314 261 __asm__("mov"__OS" %0,%%cr0": :"r" ((unsigned long)x));
kaf24@1490 262
kaf24@3232 263 #define read_cr4() ({ \
kaf24@3314 264 unsigned long __dummy; \
kaf24@3232 265 __asm__( \
kaf24@3314 266 "mov"__OS" %%cr4,%0\n\t" \
kaf24@3232 267 :"=r" (__dummy)); \
kaf24@3232 268 __dummy; \
kaf24@3232 269 })
kaf24@3232 270
kaf24@3232 271 #define write_cr4(x) \
kaf24@3314 272 __asm__("mov"__OS" %0,%%cr4": :"r" ((unsigned long)x));
kaf24@1490 273
kaf24@1490 274 /*
kaf24@1490 275 * Save the cr4 feature set we're using (ie
kaf24@1490 276 * Pentium 4MB enable and PPro Global page
kaf24@1490 277 * enable), so that any CPU's that boot up
kaf24@1490 278 * after us can get the correct flags.
kaf24@1490 279 */
kaf24@1490 280 extern unsigned long mmu_cr4_features;
kaf24@1490 281
kaf24@1490 282 static inline void set_in_cr4 (unsigned long mask)
kaf24@1490 283 {
kaf24@1490 284 mmu_cr4_features |= mask;
kaf24@1518 285 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
kaf24@1518 286 "or"__OS" %0,%%"__OP"ax\n\t"
kaf24@1518 287 "mov"__OS" %%"__OP"ax,%%cr4\n"
kaf24@1490 288 : : "irg" (mask)
kaf24@1490 289 :"ax");
kaf24@1490 290 }
kaf24@1490 291
kaf24@1490 292 static inline void clear_in_cr4 (unsigned long mask)
kaf24@1490 293 {
kaf24@1490 294 mmu_cr4_features &= ~mask;
kaf24@1518 295 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
kaf24@1518 296 "and"__OS" %0,%%"__OP"ax\n\t"
kaf24@3314 297 "mov"__OS" %%"__OP"ax,%%cr4\n"
kaf24@1490 298 : : "irg" (~mask)
kaf24@1490 299 :"ax");
kaf24@1490 300 }
kaf24@1490 301
kaf24@3232 302 /*
kaf24@3232 303 * NSC/Cyrix CPU configuration register indexes
kaf24@3232 304 */
kaf24@3232 305
kaf24@3232 306 #define CX86_PCR0 0x20
kaf24@3232 307 #define CX86_GCR 0xb8
kaf24@3232 308 #define CX86_CCR0 0xc0
kaf24@3232 309 #define CX86_CCR1 0xc1
kaf24@3232 310 #define CX86_CCR2 0xc2
kaf24@3232 311 #define CX86_CCR3 0xc3
kaf24@3232 312 #define CX86_CCR4 0xe8
kaf24@3232 313 #define CX86_CCR5 0xe9
kaf24@3232 314 #define CX86_CCR6 0xea
kaf24@3232 315 #define CX86_CCR7 0xeb
kaf24@3232 316 #define CX86_PCR1 0xf0
kaf24@3232 317 #define CX86_DIR0 0xfe
kaf24@3232 318 #define CX86_DIR1 0xff
kaf24@3232 319 #define CX86_ARR_BASE 0xc4
kaf24@3232 320 #define CX86_RCR_BASE 0xdc
kaf24@3232 321
kaf24@3232 322 /*
kaf24@3232 323 * NSC/Cyrix CPU indexed register access macros
kaf24@3232 324 */
kaf24@3232 325
kaf24@3232 326 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
kaf24@3232 327
kaf24@3232 328 #define setCx86(reg, data) do { \
kaf24@3232 329 outb((reg), 0x22); \
kaf24@3232 330 outb((data), 0x23); \
kaf24@3232 331 } while (0)
kaf24@3232 332
kaf24@3088 333 #define IOBMP_BYTES 8192
kaf24@3088 334 #define IOBMP_BYTES_PER_SELBIT (IOBMP_BYTES / 64)
kaf24@3088 335 #define IOBMP_BITS_PER_SELBIT (IOBMP_BYTES_PER_SELBIT * 8)
kaf24@3113 336 #define IOBMP_OFFSET offsetof(struct tss_struct, io_bitmap)
kaf24@3088 337 #define IOBMP_INVALID_OFFSET 0x8000
kaf24@1490 338
kaf24@1518 339 struct i387_state {
kaf24@1518 340 u8 state[512]; /* big enough for FXSAVE */
kaf24@1490 341 } __attribute__ ((aligned (16)));
kaf24@1490 342
kaf24@1490 343 struct tss_struct {
kaf24@1490 344 unsigned short back_link,__blh;
kaf24@1518 345 #ifdef __x86_64__
kaf24@1518 346 u64 rsp0;
kaf24@1518 347 u64 rsp1;
kaf24@1518 348 u64 rsp2;
kaf24@1518 349 u64 reserved1;
kaf24@1518 350 u64 ist[7];
kaf24@1518 351 u64 reserved2;
kaf24@1518 352 u16 reserved3;
kaf24@1518 353 #else
kaf24@1518 354 u32 esp0;
kaf24@1518 355 u16 ss0,__ss0h;
kaf24@1518 356 u32 esp1;
kaf24@1518 357 u16 ss1,__ss1h;
kaf24@1518 358 u32 esp2;
kaf24@1518 359 u16 ss2,__ss2h;
kaf24@1518 360 u32 __cr3;
kaf24@1518 361 u32 eip;
kaf24@1518 362 u32 eflags;
kaf24@1518 363 u32 eax,ecx,edx,ebx;
kaf24@1518 364 u32 esp;
kaf24@1518 365 u32 ebp;
kaf24@1518 366 u32 esi;
kaf24@1518 367 u32 edi;
kaf24@1518 368 u16 es, __esh;
kaf24@1518 369 u16 cs, __csh;
kaf24@1518 370 u16 ss, __ssh;
kaf24@1518 371 u16 ds, __dsh;
kaf24@1518 372 u16 fs, __fsh;
kaf24@1518 373 u16 gs, __gsh;
kaf24@1518 374 u16 ldt, __ldth;
kaf24@1518 375 u16 trace;
kaf24@1518 376 #endif
kaf24@1518 377 u16 bitmap;
kaf24@3113 378 u8 io_bitmap[IOBMP_BYTES+1];
kaf24@1518 379 /* Pads the TSS to be cacheline-aligned (total size is 0x2080). */
kaf24@3113 380 u8 __cacheline_filler[23];
kaf24@1490 381 };
kaf24@1490 382
kaf24@3081 383 struct trap_bounce {
kaf24@3081 384 unsigned long error_code;
kaf24@3081 385 unsigned long cr2;
kaf24@3081 386 unsigned short flags; /* TBF_ */
kaf24@3081 387 unsigned short cs;
kaf24@3081 388 unsigned long eip;
kaf24@3081 389 };
kaf24@3081 390
kaf24@1490 391 struct thread_struct {
kaf24@1518 392 unsigned long guestos_sp;
kaf24@1518 393 unsigned long guestos_ss;
kaf24@3081 394
kaf24@3127 395 unsigned long flags; /* TF_ */
kaf24@3127 396
kaf24@3081 397 /* Hardware debugging registers */
kaf24@1518 398 unsigned long debugreg[8]; /* %%db0-7 debug registers */
kaf24@3081 399
kaf24@3081 400 /* floating point info */
kaf24@1518 401 struct i387_state i387;
kaf24@3081 402
kaf24@3081 403 /* general user-visible register state */
kaf24@2722 404 execution_context_t user_ctxt;
kaf24@3081 405
cl349@3319 406 void (*schedule_tail) (struct exec_domain *);
kaf24@3310 407
kaf24@3081 408 /*
kaf24@3081 409 * Return vectors pushed to us by guest OS.
kaf24@3081 410 * The stack frame for events is exactly that of an x86 hardware interrupt.
kaf24@3081 411 * The stack frame for a failsafe callback is augmented with saved values
kaf24@3081 412 * for segment registers %ds, %es, %fs and %gs:
kaf24@3081 413 * %ds, %es, %fs, %gs, %eip, %cs, %eflags [, %oldesp, %oldss]
kaf24@3081 414 */
kaf24@3081 415 unsigned long event_selector; /* 08: entry CS */
kaf24@3081 416 unsigned long event_address; /* 12: entry EIP */
kaf24@3081 417
kaf24@3081 418 unsigned long failsafe_selector; /* 16: entry CS */
kaf24@3081 419 unsigned long failsafe_address; /* 20: entry EIP */
kaf24@3081 420
kaf24@3081 421 /* Bounce information for propagating an exception to guest OS. */
kaf24@3081 422 struct trap_bounce trap_bounce;
kaf24@3081 423
kaf24@3088 424 /* I/O-port access bitmap. */
kaf24@3088 425 u64 io_bitmap_sel; /* Selector to tell us which part of the IO bitmap are
kaf24@3088 426 * "interesting" (i.e. have clear bits) */
kaf24@3088 427 u8 *io_bitmap; /* Pointer to task's IO bitmap or NULL */
kaf24@3088 428
kaf24@3081 429 /* Trap info. */
kaf24@1518 430 #ifdef __i386__
kaf24@1518 431 int fast_trap_idx;
kaf24@1518 432 struct desc_struct fast_trap_desc;
kaf24@1518 433 #endif
kaf24@1518 434 trap_info_t traps[256];
iap10@3328 435 #ifdef CONFIG_VMX
iap10@3328 436 struct arch_vmx_struct arch_vmx; /* Virtual Machine Extensions */
iap10@3328 437 #endif
kaf24@1490 438 };
kaf24@1490 439
kaf24@1490 440 #define IDT_ENTRIES 256
kaf24@3635 441 extern idt_entry_t idt_table[];
kaf24@3635 442 extern idt_entry_t *idt_tables[];
kaf24@1490 443
kaf24@1518 444 #if defined(__i386__)
kaf24@1518 445
kaf24@1490 446 #define SET_DEFAULT_FAST_TRAP(_p) \
kaf24@1490 447 (_p)->fast_trap_idx = 0x20; \
kaf24@1490 448 (_p)->fast_trap_desc.a = 0; \
kaf24@1490 449 (_p)->fast_trap_desc.b = 0;
kaf24@1490 450
kaf24@1490 451 #define CLEAR_FAST_TRAP(_p) \
kaf24@1490 452 (memset(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
kaf24@1490 453 0, 8))
kaf24@1490 454
kaf24@1490 455 #ifdef XEN_DEBUGGER
kaf24@1490 456 #define SET_FAST_TRAP(_p) \
kaf24@1490 457 (pdb_initialized ? (void *) 0 : \
kaf24@1490 458 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
kaf24@1490 459 &((_p)->fast_trap_desc), 8)))
kaf24@1490 460 #else
kaf24@1490 461 #define SET_FAST_TRAP(_p) \
kaf24@1490 462 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
kaf24@1490 463 &((_p)->fast_trap_desc), 8))
kaf24@1490 464 #endif
kaf24@1490 465
cl349@2957 466 long set_fast_trap(struct exec_domain *p, int idx);
kaf24@1490 467
kaf24@3310 468 #endif
kaf24@1518 469
kaf24@1518 470 #define INIT_THREAD { 0 }
kaf24@1518 471
ach61@2843 472 extern int gpf_emulate_4gb(struct xen_regs *regs);
kaf24@1854 473
kaf24@1490 474 struct mm_struct {
kaf24@1490 475 /*
kaf24@1490 476 * Every domain has a L1 pagetable of its own. Per-domain mappings
kaf24@1490 477 * are put in this table (eg. the current GDT is mapped here).
kaf24@1490 478 */
cl349@3036 479 l1_pgentry_t *perdomain_ptes;
kaf24@1490 480 pagetable_t pagetable;
kaf24@1490 481
kaf24@3333 482 pagetable_t monitor_table;
kaf24@3333 483 l2_pgentry_t *vpagetable; /* virtual address of pagetable */
kaf24@3333 484 l2_pgentry_t *shadow_vtable; /* virtual address of shadow_table */
kaf24@3333 485 l2_pgentry_t *guest_pl2e_cache; /* guest page directory cache */
kaf24@3333 486 unsigned long min_pfn; /* min host physical */
kaf24@3333 487 unsigned long max_pfn; /* max host physical */
iap10@3328 488
kaf24@3443 489 /* Virtual CR2 value. Can be read/written by guest. */
kaf24@3443 490 unsigned long guest_cr2;
kaf24@3443 491
kaf24@1490 492 /* shadow mode status and controls */
kaf24@1490 493 unsigned int shadow_mode; /* flags to control shadow table operation */
kaf24@1490 494 pagetable_t shadow_table;
kaf24@1518 495 spinlock_t shadow_lock;
kaf24@1490 496 unsigned int shadow_max_page_count; // currently unused
kaf24@1490 497
kaf24@1490 498 /* shadow hashtable */
kaf24@1490 499 struct shadow_status *shadow_ht;
kaf24@1490 500 struct shadow_status *shadow_ht_free;
kaf24@1490 501 struct shadow_status *shadow_ht_extras; /* extra allocation units */
kaf24@1490 502 unsigned int shadow_extras_count;
kaf24@1490 503
kaf24@1490 504 /* shadow dirty bitmap */
kaf24@1490 505 unsigned long *shadow_dirty_bitmap;
kaf24@1490 506 unsigned int shadow_dirty_bitmap_size; /* in pages, bit per page */
kaf24@1490 507
kaf24@1490 508 /* shadow mode stats */
kaf24@1490 509 unsigned int shadow_page_count;
kaf24@1490 510 unsigned int shadow_fault_count;
kaf24@1490 511 unsigned int shadow_dirty_count;
iap10@1601 512 unsigned int shadow_dirty_net_count;
iap10@1601 513 unsigned int shadow_dirty_block_count;
kaf24@1490 514
kaf24@1490 515 /* Current LDT details. */
kaf24@1490 516 unsigned long ldt_base, ldt_ents, shadow_ldt_mapcnt;
kaf24@1490 517 /* Next entry is passed to LGDT on domain switch. */
kaf24@1518 518 char gdt[10]; /* NB. 10 bytes needed for x86_64. Use 6 bytes for x86_32. */
kaf24@1490 519 };
kaf24@1490 520
iap10@3328 521 #define SHM_full_32 (8) /* full virtualization for 32-bit */
iap10@3328 522
kaf24@1490 523 static inline void write_ptbase(struct mm_struct *mm)
kaf24@1490 524 {
kaf24@1490 525 unsigned long pa;
kaf24@1490 526
iap10@3328 527 #ifdef CONFIG_VMX
iap10@3328 528 if ( unlikely(mm->shadow_mode) ) {
iap10@3328 529 if (mm->shadow_mode == SHM_full_32)
iap10@3328 530 pa = pagetable_val(mm->monitor_table);
iap10@3328 531 else
iap10@3328 532 pa = pagetable_val(mm->shadow_table);
iap10@3328 533 }
iap10@3328 534 #else
kaf24@1490 535 if ( unlikely(mm->shadow_mode) )
iap10@3328 536 pa = pagetable_val(mm->shadow_table);
iap10@3328 537 #endif
kaf24@1490 538 else
iap10@3328 539 pa = pagetable_val(mm->pagetable);
kaf24@1490 540
kaf24@2790 541 write_cr3(pa);
kaf24@1490 542 }
kaf24@1490 543
kaf24@1490 544 #define IDLE0_MM \
kaf24@1490 545 { \
cl349@3036 546 perdomain_ptes: 0, \
cl349@3036 547 pagetable: mk_pagetable(__pa(idle_pg_table)) \
kaf24@1490 548 }
kaf24@1490 549
kaf24@1490 550 /* Convenient accessor for mm.gdt. */
kaf24@1854 551 #define SET_GDT_ENTRIES(_p, _e) ((*(u16 *)((_p)->mm.gdt + 0)) = (((_e)<<3)-1))
kaf24@1518 552 #define SET_GDT_ADDRESS(_p, _a) ((*(unsigned long *)((_p)->mm.gdt + 2)) = (_a))
kaf24@1854 553 #define GET_GDT_ENTRIES(_p) (((*(u16 *)((_p)->mm.gdt + 0))+1)>>3)
kaf24@1854 554 #define GET_GDT_ADDRESS(_p) (*(unsigned long *)((_p)->mm.gdt + 2))
kaf24@1490 555
cl349@2964 556 void destroy_gdt(struct exec_domain *d);
cl349@2957 557 long set_gdt(struct exec_domain *d,
kaf24@1490 558 unsigned long *frames,
kaf24@1490 559 unsigned int entries);
kaf24@1490 560
cl349@2957 561 long set_debugreg(struct exec_domain *p, int reg, unsigned long value);
kaf24@1490 562
kaf24@3400 563 struct microcode_header {
kaf24@1490 564 unsigned int hdrver;
kaf24@1490 565 unsigned int rev;
kaf24@1490 566 unsigned int date;
kaf24@1490 567 unsigned int sig;
kaf24@1490 568 unsigned int cksum;
kaf24@1490 569 unsigned int ldrver;
kaf24@1490 570 unsigned int pf;
kaf24@3400 571 unsigned int datasize;
kaf24@3400 572 unsigned int totalsize;
kaf24@3400 573 unsigned int reserved[3];
kaf24@3400 574 };
kaf24@3400 575
kaf24@3400 576 struct microcode {
kaf24@3400 577 struct microcode_header hdr;
kaf24@3400 578 unsigned int bits[0];
kaf24@1490 579 };
kaf24@1490 580
kaf24@3400 581 typedef struct microcode microcode_t;
kaf24@3400 582 typedef struct microcode_header microcode_header_t;
kaf24@3400 583
kaf24@3400 584 /* microcode format is extended from prescott processors */
kaf24@3400 585 struct extended_signature {
kaf24@3400 586 unsigned int sig;
kaf24@3400 587 unsigned int pf;
kaf24@3400 588 unsigned int cksum;
kaf24@3400 589 };
kaf24@3400 590
kaf24@3400 591 struct extended_sigtable {
kaf24@3400 592 unsigned int count;
kaf24@3400 593 unsigned int cksum;
kaf24@3400 594 unsigned int reserved[3];
kaf24@3400 595 struct extended_signature sigs[0];
kaf24@3400 596 };
kaf24@1490 597
kaf24@1490 598 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
kaf24@1490 599 static inline void rep_nop(void)
kaf24@1490 600 {
kaf24@1490 601 __asm__ __volatile__("rep;nop");
kaf24@1490 602 }
kaf24@1490 603
kaf24@1490 604 #define cpu_relax() rep_nop()
kaf24@1490 605
kaf24@1490 606 /* Prefetch instructions for Pentium III and AMD Athlon */
kaf24@1490 607 #ifdef CONFIG_MPENTIUMIII
kaf24@1490 608
kaf24@1490 609 #define ARCH_HAS_PREFETCH
kaf24@1490 610 extern inline void prefetch(const void *x)
kaf24@1490 611 {
kaf24@1490 612 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
kaf24@1490 613 }
kaf24@1490 614
kaf24@1490 615 #elif CONFIG_X86_USE_3DNOW
kaf24@1490 616
kaf24@1490 617 #define ARCH_HAS_PREFETCH
kaf24@1490 618 #define ARCH_HAS_PREFETCHW
kaf24@1490 619 #define ARCH_HAS_SPINLOCK_PREFETCH
kaf24@1490 620
kaf24@1490 621 extern inline void prefetch(const void *x)
kaf24@1490 622 {
kaf24@1490 623 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
kaf24@1490 624 }
kaf24@1490 625
kaf24@1490 626 extern inline void prefetchw(const void *x)
kaf24@1490 627 {
kaf24@1490 628 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
kaf24@1490 629 }
kaf24@1490 630 #define spin_lock_prefetch(x) prefetchw(x)
kaf24@1490 631
kaf24@1490 632 #endif
kaf24@1490 633
kaf24@3079 634 void show_guest_stack();
kaf24@3079 635 void show_trace(unsigned long *esp);
kaf24@3079 636 void show_stack(unsigned long *esp);
kaf24@3079 637 void show_registers(struct xen_regs *regs);
kaf24@3127 638 asmlinkage void fatal_trap(int trapnr, struct xen_regs *regs);
kaf24@3079 639
kaf24@3079 640 #endif /* !__ASSEMBLY__ */
kaf24@3079 641
kaf24@1518 642 #endif /* __ASM_X86_PROCESSOR_H */