debuggers.hg

view xen/include/asm-x86/config.h @ 4632:05621922c024

bitkeeper revision 1.1340 (426652e8h-OWfDH7vm_elbT4wtH2cA)

Merge maf46@ssh-relay1.cl.cam.ac.uk:/usr/groups/xeno/BK/xen-unstable.bk
into fleming.research:/scratch/fleming/mafetter/xen-unstable.bk

Signed-off-by: michael.fetterman@cl.cam.ac.uk
author mafetter@fleming.research
date Wed Apr 20 13:02:32 2005 +0000 (2005-04-20)
parents b1cb9f7f34f9 d10fe13887d7
children 4fa88763f2cc
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #define CONFIG_VMX 1
12 #define CONFIG_X86 1
13 #define CONFIG_SHADOW 1
15 #define CONFIG_SMP 1
16 #define CONFIG_X86_LOCAL_APIC 1
17 #define CONFIG_X86_GOOD_APIC 1
18 #define CONFIG_X86_IO_APIC 1
20 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
21 #define CONFIG_X86_L1_CACHE_SHIFT 7
23 #define CONFIG_ACPI 1
24 #define CONFIG_ACPI_BOOT 1
26 #define CONFIG_PCI 1
27 #define CONFIG_PCI_DIRECT 1
28 #if defined(__i386__)
29 #define CONFIG_PCI_BIOS 1
30 #endif
32 #define CONFIG_IDE 1
33 #define CONFIG_BLK_DEV_IDE 1
34 #define CONFIG_BLK_DEV_IDEDMA 1
35 #define CONFIG_BLK_DEV_IDEPCI 1
36 #define CONFIG_IDEDISK_MULTI_MODE 1
37 #define CONFIG_IDEDISK_STROKE 1
38 #define CONFIG_IDEPCI_SHARE_IRQ 1
39 #define CONFIG_BLK_DEV_IDEDMA_PCI 1
40 #define CONFIG_IDEDMA_PCI_AUTO 1
41 #define CONFIG_IDEDMA_AUTO 1
42 #define CONFIG_IDEDMA_ONLYDISK 1
43 #define CONFIG_BLK_DEV_IDE_MODES 1
44 #define CONFIG_BLK_DEV_PIIX 1
46 #define CONFIG_SCSI 1
47 #define CONFIG_SCSI_LOGGING 1
48 #define CONFIG_BLK_DEV_SD 1
49 #define CONFIG_SD_EXTRA_DEVS 40
50 #define CONFIG_SCSI_MULTI_LUN 1
52 #define CONFIG_XEN_ATTENTION_KEY 1
54 #define HZ 100
56 #define OPT_CONSOLE_STR "com1,vga"
58 #define NR_CPUS 16
60 /* Linkage for x86 */
61 #define __ALIGN .align 16,0x90
62 #define __ALIGN_STR ".align 16,0x90"
63 #define SYMBOL_NAME_STR(X) #X
64 #define SYMBOL_NAME(X) X
65 #define SYMBOL_NAME_LABEL(X) X##:
66 #ifdef __ASSEMBLY__
67 #define ALIGN __ALIGN
68 #define ALIGN_STR __ALIGN_STR
69 #define ENTRY(name) \
70 .globl SYMBOL_NAME(name); \
71 ALIGN; \
72 SYMBOL_NAME_LABEL(name)
73 #endif
75 #define barrier() __asm__ __volatile__("": : :"memory")
77 #define NR_hypercalls 32
79 #ifndef NDEBUG
80 #define MEMORY_GUARD
81 #ifdef __x86_64__
82 #define STACK_ORDER 2
83 #endif
84 #endif
86 #ifndef STACK_ORDER
87 #define STACK_ORDER 1
88 #endif
89 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
91 #ifndef __ASSEMBLY__
92 extern unsigned long _end; /* standard ELF symbol */
93 extern void __out_of_line_bug(int line) __attribute__((noreturn));
94 #define out_of_line_bug() __out_of_line_bug(__LINE__)
95 #endif /* __ASSEMBLY__ */
97 #define FORCE_CRASH() __asm__ __volatile__ ( "ud2" )
99 #if defined(__x86_64__)
101 #define asmlinkage
103 #define XENHEAP_DEFAULT_MB (16)
105 #define PML4_ENTRY_BITS 39
106 #ifndef __ASSEMBLY__
107 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
108 #define PML4_ADDR(_slot) \
109 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
110 (_slot ## UL << PML4_ENTRY_BITS))
111 #else
112 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
113 #define PML4_ADDR(_slot) \
114 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
115 #endif
117 /*
118 * Memory layout:
119 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
120 * Guest-defined use.
121 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
122 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
123 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
124 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
125 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
126 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
127 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
128 * Read-only guest linear page table (GUEST ACCESSIBLE).
129 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
130 * Guest linear page table.
131 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
132 * Shadow linear page table.
133 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
134 * Per-domain mappings (e.g., GDT, LDT).
135 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
136 * Machine-to-phys translation table.
137 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
138 * Page-frame information array.
139 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
140 * ioremap()/fixmap area.
141 * 0xffff828c00000000 - 0xffff82ffffffffff [464GB, PML4:261]
142 * Reserved for future use.
143 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
144 * 1:1 direct mapping of all physical memory. Xen and its heap live here.
145 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
146 * Reserved for future use.
147 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
148 * Guest-defined use.
149 */
152 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
153 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
154 #define ROOT_PAGETABLE_XEN_SLOTS \
155 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
157 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
158 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
159 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
160 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
161 #define RO_MPT_VIRT_START (PML4_ADDR(256))
162 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
163 /* Slot 257: read-only guest-accessible linear page table. */
164 #define RO_LINEAR_PT_VIRT_START (PML4_ADDR(257))
165 #define RO_LINEAR_PT_VIRT_END (RO_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
166 /* Slot 258: linear page table (guest table). */
167 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
168 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
169 /* Slot 259: linear page table (shadow table). */
170 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
171 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
172 /* Slot 260: per-domain mappings. */
173 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
174 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + PML4_ENTRY_BYTES)
175 /* Slot 261: machine-to-phys conversion table (16GB). */
176 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
177 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
178 /* Slot 261: page-frame information array (16GB). */
179 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
180 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
181 /* Slot 261: ioremap()/fixmap area (16GB). */
182 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
183 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
184 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
185 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
186 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
188 #define PGT_base_page_table PGT_l4_page_table
190 #define __HYPERVISOR_CS64 0x0810
191 #define __HYPERVISOR_CS32 0x0808
192 #define __HYPERVISOR_CS __HYPERVISOR_CS64
193 #define __HYPERVISOR_DS64 0x0000
194 #define __HYPERVISOR_DS32 0x0818
195 #define __HYPERVISOR_DS __HYPERVISOR_DS64
197 #define __GUEST_CS64 0x0833
198 #define __GUEST_CS32 0x0823
199 #define __GUEST_CS __GUEST_CS64
200 #define __GUEST_DS 0x0000
201 #define __GUEST_SS 0x082b
203 /* For generic assembly code: use macros to define operation/operand sizes. */
204 #define __OS "q" /* Operation Suffix */
205 #define __OP "r" /* Operand Prefix */
206 #define __FIXUP_ALIGN ".align 8"
207 #define __FIXUP_WORD ".quad"
209 #elif defined(__i386__)
211 #define asmlinkage __attribute__((regparm(0)))
213 /*
214 * Memory layout (high to low): SIZE PAE-SIZE
215 * ------ ------
216 * I/O remapping area ( 4MB)
217 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
218 * map_domain_mem cache ( 4MB)
219 * Per-domain mappings ( 4MB)
220 * Shadow linear pagetable ( 4MB) ( 8MB)
221 * Guest linear pagetable ( 4MB) ( 8MB)
222 * Machine-to-physical translation table [writable] ( 4MB)
223 * Frame-info table (24MB) (96MB)
224 * * Start of guest inaccessible area
225 * Machine-to-physical translation table [read-only] ( 4MB)
226 * * Start of guest unmodifiable area
227 */
229 #define IOREMAP_MBYTES 4
230 #define DIRECTMAP_MBYTES 12
231 #define MAPCACHE_MBYTES 4
232 #define PERDOMAIN_MBYTES 4
234 #ifdef CONFIG_X86_PAE
235 # define LINEARPT_MBYTES 8
236 # define MACHPHYS_MBYTES 4 /* KAF: This needs to be bigger */
237 # define FRAMETABLE_MBYTES 96 /* 16 GB mem limit (total) */
238 #else
239 # define LINEARPT_MBYTES 4
240 # define MACHPHYS_MBYTES 4
241 # define FRAMETABLE_MBYTES 24
242 #endif
244 #define IOREMAP_VIRT_END 0UL
245 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
246 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
247 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
248 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
249 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
250 #define PERDOMAIN_VIRT_END MAPCACHE_VIRT_START
251 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
252 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
253 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
254 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
255 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
256 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
257 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
258 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
259 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
260 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
261 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
263 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
264 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
266 /* Maximum linear address accessible via guest memory segments. */
267 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
269 #ifdef CONFIG_X86_PAE
270 /* Hypervisor owns top 144MB of virtual address space. */
271 # define __HYPERVISOR_VIRT_START 0xF7000000
272 # define HYPERVISOR_VIRT_START (0xF7000000UL)
273 #else
274 /* Hypervisor owns top 64MB of virtual address space. */
275 # define __HYPERVISOR_VIRT_START 0xFC000000
276 # define HYPERVISOR_VIRT_START (0xFC000000UL)
277 #endif
279 #define ROOT_PAGETABLE_FIRST_XEN_SLOT \
280 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
281 #define ROOT_PAGETABLE_LAST_XEN_SLOT \
282 (~0UL >> L2_PAGETABLE_SHIFT)
283 #define ROOT_PAGETABLE_XEN_SLOTS \
284 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
286 #define PGT_base_page_table PGT_l2_page_table
288 #define __HYPERVISOR_CS 0x0808
289 #define __HYPERVISOR_DS 0x0810
291 /* For generic assembly code: use macros to define operation/operand sizes. */
292 #define __OS "l" /* Operation Suffix */
293 #define __OP "e" /* Operand Prefix */
294 #define __FIXUP_ALIGN ".align 4"
295 #define __FIXUP_WORD ".long"
297 #endif /* __i386__ */
299 #ifndef __ASSEMBLY__
300 extern unsigned long xenheap_phys_end; /* user-configurable */
301 #endif
303 #define GDT_VIRT_START(ed) (PERDOMAIN_VIRT_START + ((ed)->eid << PDPT_VCPU_VA_SHIFT))
304 #define GDT_VIRT_END(ed) (GDT_VIRT_START(ed) + (64*1024))
305 #define LDT_VIRT_START(ed) (PERDOMAIN_VIRT_START + (64*1024) + ((ed)->eid << PDPT_VCPU_VA_SHIFT))
306 #define LDT_VIRT_END(ed) (LDT_VIRT_START(ed) + (64*1024))
308 #define PDPT_VCPU_SHIFT 5
309 #define PDPT_VCPU_VA_SHIFT (PDPT_VCPU_SHIFT + PAGE_SHIFT)
311 #if defined(__x86_64__)
312 #define ELFSIZE 64
313 #else
314 #define ELFSIZE 32
315 #endif
317 #endif /* __X86_CONFIG_H__ */