debuggers.hg

view tools/ioemu/hw/es1370.c @ 10995:08a11694b109

[qemu] Update ioemu to qemu 0.8.2.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Mon Aug 07 18:25:30 2006 +0100 (2006-08-07)
parents b450f21472a0
children
line source
1 /*
2 * QEMU ES1370 emulation
3 *
4 * Copyright (c) 2005 Vassili Karpov (malc)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 /* #define DEBUG_ES1370 */
26 /* #define VERBOSE_ES1370 */
27 #define SILENT_ES1370
29 #include "vl.h"
31 /* Missing stuff:
32 SCTRL_P[12](END|ST)INC
33 SCTRL_P1SCTRLD
34 SCTRL_P2DACSEN
35 CTRL_DAC_SYNC
36 MIDI
37 non looped mode
38 surely more
39 */
41 /*
42 Following macros and samplerate array were copied verbatim from
43 Linux kernel 2.4.30: drivers/sound/es1370.c
45 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
46 */
48 /* Start blatant GPL violation */
50 #define ES1370_REG_CONTROL 0x00
51 #define ES1370_REG_STATUS 0x04
52 #define ES1370_REG_UART_DATA 0x08
53 #define ES1370_REG_UART_STATUS 0x09
54 #define ES1370_REG_UART_CONTROL 0x09
55 #define ES1370_REG_UART_TEST 0x0a
56 #define ES1370_REG_MEMPAGE 0x0c
57 #define ES1370_REG_CODEC 0x10
58 #define ES1370_REG_SERIAL_CONTROL 0x20
59 #define ES1370_REG_DAC1_SCOUNT 0x24
60 #define ES1370_REG_DAC2_SCOUNT 0x28
61 #define ES1370_REG_ADC_SCOUNT 0x2c
63 #define ES1370_REG_DAC1_FRAMEADR 0xc30
64 #define ES1370_REG_DAC1_FRAMECNT 0xc34
65 #define ES1370_REG_DAC2_FRAMEADR 0xc38
66 #define ES1370_REG_DAC2_FRAMECNT 0xc3c
67 #define ES1370_REG_ADC_FRAMEADR 0xd30
68 #define ES1370_REG_ADC_FRAMECNT 0xd34
69 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38
70 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
72 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
74 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
75 #define DAC2_DIVTOSR(x) (1411200/((x)+2))
77 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
78 #define CTRL_XCTL1 0x40000000 /* electret mic bias */
79 #define CTRL_OPEN 0x20000000 /* no function, can be read and written */
80 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
81 #define CTRL_SH_PCLKDIV 16
82 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
83 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
84 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
85 #define CTRL_SH_WTSRSEL 12
86 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
87 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
88 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
89 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
90 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
91 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
92 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
93 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
94 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
95 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
96 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
97 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
99 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
100 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
101 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */
102 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
103 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
104 #define STAT_SH_VC 5
105 #define STAT_MCCB 0x00000010 /* CCB int pending */
106 #define STAT_UART 0x00000008 /* UART int pending */
107 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
108 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
109 #define STAT_ADC 0x00000001 /* ADC int pending */
111 #define USTAT_RXINT 0x80 /* UART rx int pending */
112 #define USTAT_TXINT 0x04 /* UART tx int pending */
113 #define USTAT_TXRDY 0x02 /* UART tx ready */
114 #define USTAT_RXRDY 0x01 /* UART rx ready */
116 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
117 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
118 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
119 #define UCTRL_CNTRL 0x03 /* control field */
120 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
122 #define SCTRL_P2ENDINC 0x00380000 /* */
123 #define SCTRL_SH_P2ENDINC 19
124 #define SCTRL_P2STINC 0x00070000 /* */
125 #define SCTRL_SH_P2STINC 16
126 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
127 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
128 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
129 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
130 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
131 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
132 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
133 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
134 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
135 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
136 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
137 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
138 #define SCTRL_R1FMT 0x00000030 /* format mask */
139 #define SCTRL_SH_R1FMT 4
140 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
141 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
142 #define SCTRL_P2FMT 0x0000000c /* format mask */
143 #define SCTRL_SH_P2FMT 2
144 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
145 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
146 #define SCTRL_P1FMT 0x00000003 /* format mask */
147 #define SCTRL_SH_P1FMT 0
149 /* End blatant GPL violation */
151 #define NB_CHANNELS 3
152 #define DAC1_CHANNEL 0
153 #define DAC2_CHANNEL 1
154 #define ADC_CHANNEL 2
156 #define IO_READ_PROTO(n) \
157 static uint32_t n (void *opaque, uint32_t addr)
158 #define IO_WRITE_PROTO(n) \
159 static void n (void *opaque, uint32_t addr, uint32_t val)
161 static void es1370_dac1_callback (void *opaque, int free);
162 static void es1370_dac2_callback (void *opaque, int free);
163 static void es1370_adc_callback (void *opaque, int avail);
165 #ifdef DEBUG_ES1370
167 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
169 static void print_ctl (uint32_t val)
170 {
171 char buf[1024];
173 buf[0] = '\0';
174 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
175 a (ADC_STOP);
176 a (XCTL1);
177 a (OPEN);
178 a (MSFMTSEL);
179 a (M_SBB);
180 a (DAC_SYNC);
181 a (CCB_INTRM);
182 a (M_CB);
183 a (XCTL0);
184 a (BREQ);
185 a (DAC1_EN);
186 a (DAC2_EN);
187 a (ADC_EN);
188 a (UART_EN);
189 a (JYSTK_EN);
190 a (CDC_EN);
191 a (SERR_DIS);
192 #undef a
193 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
194 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
195 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
196 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
197 buf);
198 }
200 static void print_sctl (uint32_t val)
201 {
202 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
203 char buf[1024];
205 buf[0] = '\0';
207 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
208 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
209 b (R1LOOPSEL);
210 b (P2LOOPSEL);
211 b (P1LOOPSEL);
212 a (P2PAUSE);
213 a (P1PAUSE);
214 a (R1INTEN);
215 a (P2INTEN);
216 a (P1INTEN);
217 a (P1SCTRLD);
218 a (P2DACSEN);
219 if (buf[0]) {
220 strcat (buf, "\n ");
221 }
222 else {
223 buf[0] = ' ';
224 buf[1] = '\0';
225 }
226 #undef b
227 #undef a
228 AUD_log ("es1370",
229 "%s"
230 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
231 buf,
232 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
233 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
234 fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
235 fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
236 fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
237 );
238 }
239 #else
240 #define ldebug(...)
241 #define print_ctl(...)
242 #define print_sctl(...)
243 #endif
245 #ifdef VERBOSE_ES1370
246 #define dolog(...) AUD_log ("es1370", __VA_ARGS__)
247 #else
248 #define dolog(...)
249 #endif
251 #ifndef SILENT_ES1370
252 #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__)
253 #else
254 #define lwarn(...)
255 #endif
257 struct chan {
258 uint32_t shift;
259 uint32_t leftover;
260 uint32_t scount;
261 uint32_t frame_addr;
262 uint32_t frame_cnt;
263 };
265 typedef struct ES1370State {
266 PCIDevice *pci_dev;
268 QEMUSoundCard card;
269 struct chan chan[NB_CHANNELS];
270 SWVoiceOut *dac_voice[2];
271 SWVoiceIn *adc_voice;
273 uint32_t ctl;
274 uint32_t status;
275 uint32_t mempage;
276 uint32_t codec;
277 uint32_t sctl;
278 } ES1370State;
280 typedef struct PCIES1370State {
281 PCIDevice dev;
282 ES1370State es1370;
283 } PCIES1370State;
285 struct chan_bits {
286 uint32_t ctl_en;
287 uint32_t stat_int;
288 uint32_t sctl_pause;
289 uint32_t sctl_inten;
290 uint32_t sctl_fmt;
291 uint32_t sctl_sh_fmt;
292 uint32_t sctl_loopsel;
293 void (*calc_freq) (ES1370State *s, uint32_t ctl,
294 uint32_t *old_freq, uint32_t *new_freq);
295 };
297 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
298 uint32_t *old_freq, uint32_t *new_freq);
299 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
300 uint32_t *old_freq,
301 uint32_t *new_freq);
303 static const struct chan_bits es1370_chan_bits[] = {
304 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
305 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
306 es1370_dac1_calc_freq},
308 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
309 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
310 es1370_dac2_and_adc_calc_freq},
312 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
313 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
314 es1370_dac2_and_adc_calc_freq}
315 };
317 static void es1370_update_status (ES1370State *s, uint32_t new_status)
318 {
319 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
321 if (level) {
322 s->status = new_status | STAT_INTR;
323 }
324 else {
325 s->status = new_status & ~STAT_INTR;
326 }
327 pci_set_irq (s->pci_dev, 0, !!level);
328 }
330 static void es1370_reset (ES1370State *s)
331 {
332 size_t i;
334 s->ctl = 1;
335 s->status = 0x60;
336 s->mempage = 0;
337 s->codec = 0;
338 s->sctl = 0;
340 for (i = 0; i < NB_CHANNELS; ++i) {
341 struct chan *d = &s->chan[i];
342 d->scount = 0;
343 d->leftover = 0;
344 if (i == ADC_CHANNEL) {
345 AUD_close_in (&s->card, s->adc_voice);
346 s->adc_voice = NULL;
347 }
348 else {
349 AUD_close_out (&s->card, s->dac_voice[i]);
350 s->dac_voice[i] = NULL;
351 }
352 }
353 pci_set_irq (s->pci_dev, 0, 0);
354 }
356 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
357 {
358 uint32_t new_status = s->status;
360 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
361 new_status &= ~STAT_DAC1;
362 }
364 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
365 new_status &= ~STAT_DAC2;
366 }
368 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
369 new_status &= ~STAT_ADC;
370 }
372 if (new_status != s->status) {
373 es1370_update_status (s, new_status);
374 }
375 }
377 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
378 uint32_t *old_freq, uint32_t *new_freq)
380 {
381 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
382 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
383 }
385 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
386 uint32_t *old_freq,
387 uint32_t *new_freq)
389 {
390 uint32_t old_pclkdiv, new_pclkdiv;
392 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
393 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
394 *new_freq = DAC2_DIVTOSR (new_pclkdiv);
395 *old_freq = DAC2_DIVTOSR (old_pclkdiv);
396 }
398 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
399 {
400 size_t i;
401 uint32_t old_freq, new_freq, old_fmt, new_fmt;
403 for (i = 0; i < NB_CHANNELS; ++i) {
404 struct chan *d = &s->chan[i];
405 const struct chan_bits *b = &es1370_chan_bits[i];
407 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
408 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
410 b->calc_freq (s, ctl, &old_freq, &new_freq);
412 if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
413 d->shift = (new_fmt & 1) + (new_fmt >> 1);
414 ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
415 i,
416 new_freq,
417 1 << (new_fmt & 1),
418 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
419 d->shift);
420 if (new_freq) {
421 audsettings_t as;
423 as.freq = new_freq;
424 as.nchannels = 1 << (new_fmt & 1);
425 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
426 as.endianness = 0;
428 if (i == ADC_CHANNEL) {
429 s->adc_voice =
430 AUD_open_in (
431 &s->card,
432 s->adc_voice,
433 "es1370.adc",
434 s,
435 es1370_adc_callback,
436 &as
437 );
438 }
439 else {
440 s->dac_voice[i] =
441 AUD_open_out (
442 &s->card,
443 s->dac_voice[i],
444 i ? "es1370.dac2" : "es1370.dac1",
445 s,
446 i ? es1370_dac2_callback : es1370_dac1_callback,
447 &as
448 );
449 }
450 }
451 }
453 if (((ctl ^ s->ctl) & b->ctl_en)
454 || ((sctl ^ s->sctl) & b->sctl_pause)) {
455 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
457 if (i == ADC_CHANNEL) {
458 AUD_set_active_in (s->adc_voice, on);
459 }
460 else {
461 AUD_set_active_out (s->dac_voice[i], on);
462 }
463 }
464 }
466 s->ctl = ctl;
467 s->sctl = sctl;
468 }
470 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
471 {
472 addr &= 0xff;
473 if (addr >= 0x30 && addr <= 0x3f)
474 addr |= s->mempage << 8;
475 return addr;
476 }
478 IO_WRITE_PROTO (es1370_writeb)
479 {
480 ES1370State *s = opaque;
481 uint32_t shift, mask;
483 addr = es1370_fixup (s, addr);
485 switch (addr) {
486 case ES1370_REG_CONTROL:
487 case ES1370_REG_CONTROL + 1:
488 case ES1370_REG_CONTROL + 2:
489 case ES1370_REG_CONTROL + 3:
490 shift = (addr - ES1370_REG_CONTROL) << 3;
491 mask = 0xff << shift;
492 val = (s->ctl & ~mask) | ((val & 0xff) << shift);
493 es1370_update_voices (s, val, s->sctl);
494 print_ctl (val);
495 break;
496 case ES1370_REG_MEMPAGE:
497 s->mempage = val;
498 break;
499 case ES1370_REG_SERIAL_CONTROL:
500 case ES1370_REG_SERIAL_CONTROL + 1:
501 case ES1370_REG_SERIAL_CONTROL + 2:
502 case ES1370_REG_SERIAL_CONTROL + 3:
503 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
504 mask = 0xff << shift;
505 val = (s->sctl & ~mask) | ((val & 0xff) << shift);
506 es1370_maybe_lower_irq (s, val);
507 es1370_update_voices (s, s->ctl, val);
508 print_sctl (val);
509 break;
510 default:
511 lwarn ("writeb %#x <- %#x\n", addr, val);
512 break;
513 }
514 }
516 IO_WRITE_PROTO (es1370_writew)
517 {
518 ES1370State *s = opaque;
519 addr = es1370_fixup (s, addr);
520 uint32_t shift, mask;
521 struct chan *d = &s->chan[0];
523 switch (addr) {
524 case ES1370_REG_CODEC:
525 dolog ("ignored codec write address %#x, data %#x\n",
526 (val >> 8) & 0xff, val & 0xff);
527 s->codec = val;
528 break;
530 case ES1370_REG_CONTROL:
531 case ES1370_REG_CONTROL + 2:
532 shift = (addr != ES1370_REG_CONTROL) << 4;
533 mask = 0xffff << shift;
534 val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
535 es1370_update_voices (s, val, s->sctl);
536 print_ctl (val);
537 break;
539 case ES1370_REG_ADC_SCOUNT:
540 d++;
541 case ES1370_REG_DAC2_SCOUNT:
542 d++;
543 case ES1370_REG_DAC1_SCOUNT:
544 d->scount = (d->scount & ~0xffff) | (val & 0xffff);
545 break;
547 default:
548 lwarn ("writew %#x <- %#x\n", addr, val);
549 break;
550 }
551 }
553 IO_WRITE_PROTO (es1370_writel)
554 {
555 ES1370State *s = opaque;
556 struct chan *d = &s->chan[0];
558 addr = es1370_fixup (s, addr);
560 switch (addr) {
561 case ES1370_REG_CONTROL:
562 es1370_update_voices (s, val, s->sctl);
563 print_ctl (val);
564 break;
566 case ES1370_REG_MEMPAGE:
567 s->mempage = val & 0xf;
568 break;
570 case ES1370_REG_SERIAL_CONTROL:
571 es1370_maybe_lower_irq (s, val);
572 es1370_update_voices (s, s->ctl, val);
573 print_sctl (val);
574 break;
576 case ES1370_REG_ADC_SCOUNT:
577 d++;
578 case ES1370_REG_DAC2_SCOUNT:
579 d++;
580 case ES1370_REG_DAC1_SCOUNT:
581 d->scount = (val & 0xffff) | (d->scount & ~0xffff);
582 ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
583 d - &s->chan[0], val >> 16, (val & 0xffff));
584 break;
586 case ES1370_REG_ADC_FRAMEADR:
587 d++;
588 case ES1370_REG_DAC2_FRAMEADR:
589 d++;
590 case ES1370_REG_DAC1_FRAMEADR:
591 d->frame_addr = val;
592 ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
593 break;
595 case ES1370_REG_PHANTOM_FRAMECNT:
596 lwarn ("writing to phantom frame count %#x\n", val);
597 break;
598 case ES1370_REG_PHANTOM_FRAMEADR:
599 lwarn ("writing to phantom frame address %#x\n", val);
600 break;
602 case ES1370_REG_ADC_FRAMECNT:
603 d++;
604 case ES1370_REG_DAC2_FRAMECNT:
605 d++;
606 case ES1370_REG_DAC1_FRAMECNT:
607 d->frame_cnt = val;
608 d->leftover = 0;
609 ldebug ("chan %d frame count %d, buffer size %d\n",
610 d - &s->chan[0], val >> 16, val & 0xffff);
611 break;
613 default:
614 lwarn ("writel %#x <- %#x\n", addr, val);
615 break;
616 }
617 }
619 IO_READ_PROTO (es1370_readb)
620 {
621 ES1370State *s = opaque;
622 uint32_t val;
624 addr = es1370_fixup (s, addr);
626 switch (addr) {
627 case 0x1b: /* Legacy */
628 lwarn ("Attempt to read from legacy register\n");
629 val = 5;
630 break;
631 case ES1370_REG_MEMPAGE:
632 val = s->mempage;
633 break;
634 case ES1370_REG_CONTROL + 0:
635 case ES1370_REG_CONTROL + 1:
636 case ES1370_REG_CONTROL + 2:
637 case ES1370_REG_CONTROL + 3:
638 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
639 break;
640 case ES1370_REG_STATUS + 0:
641 case ES1370_REG_STATUS + 1:
642 case ES1370_REG_STATUS + 2:
643 case ES1370_REG_STATUS + 3:
644 val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
645 break;
646 default:
647 val = ~0;
648 lwarn ("readb %#x -> %#x\n", addr, val);
649 break;
650 }
651 return val;
652 }
654 IO_READ_PROTO (es1370_readw)
655 {
656 ES1370State *s = opaque;
657 struct chan *d = &s->chan[0];
658 uint32_t val;
660 addr = es1370_fixup (s, addr);
662 switch (addr) {
663 case ES1370_REG_ADC_SCOUNT + 2:
664 d++;
665 case ES1370_REG_DAC2_SCOUNT + 2:
666 d++;
667 case ES1370_REG_DAC1_SCOUNT + 2:
668 val = d->scount >> 16;
669 break;
671 case ES1370_REG_ADC_FRAMECNT:
672 d++;
673 case ES1370_REG_DAC2_FRAMECNT:
674 d++;
675 case ES1370_REG_DAC1_FRAMECNT:
676 val = d->frame_cnt & 0xffff;
677 break;
679 case ES1370_REG_ADC_FRAMECNT + 2:
680 d++;
681 case ES1370_REG_DAC2_FRAMECNT + 2:
682 d++;
683 case ES1370_REG_DAC1_FRAMECNT + 2:
684 val = d->frame_cnt >> 16;
685 break;
687 default:
688 val = ~0;
689 lwarn ("readw %#x -> %#x\n", addr, val);
690 break;
691 }
693 return val;
694 }
696 IO_READ_PROTO (es1370_readl)
697 {
698 ES1370State *s = opaque;
699 uint32_t val;
700 struct chan *d = &s->chan[0];
702 addr = es1370_fixup (s, addr);
704 switch (addr) {
705 case ES1370_REG_CONTROL:
706 val = s->ctl;
707 break;
708 case ES1370_REG_STATUS:
709 val = s->status;
710 break;
711 case ES1370_REG_MEMPAGE:
712 val = s->mempage;
713 break;
714 case ES1370_REG_CODEC:
715 val = s->codec;
716 break;
717 case ES1370_REG_SERIAL_CONTROL:
718 val = s->sctl;
719 break;
721 case ES1370_REG_ADC_SCOUNT:
722 d++;
723 case ES1370_REG_DAC2_SCOUNT:
724 d++;
725 case ES1370_REG_DAC1_SCOUNT:
726 val = d->scount;
727 #ifdef DEBUG_ES1370
728 {
729 uint32_t curr_count = d->scount >> 16;
730 uint32_t count = d->scount & 0xffff;
732 curr_count <<= d->shift;
733 count <<= d->shift;
734 dolog ("read scount curr %d, total %d\n", curr_count, count);
735 }
736 #endif
737 break;
739 case ES1370_REG_ADC_FRAMECNT:
740 d++;
741 case ES1370_REG_DAC2_FRAMECNT:
742 d++;
743 case ES1370_REG_DAC1_FRAMECNT:
744 val = d->frame_cnt;
745 #ifdef DEBUG_ES1370
746 {
747 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
748 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
749 if (curr > size)
750 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
751 curr > size);
752 }
753 #endif
754 break;
756 case ES1370_REG_ADC_FRAMEADR:
757 d++;
758 case ES1370_REG_DAC2_FRAMEADR:
759 d++;
760 case ES1370_REG_DAC1_FRAMEADR:
761 val = d->frame_addr;
762 break;
764 case ES1370_REG_PHANTOM_FRAMECNT:
765 val = ~0U;
766 lwarn ("reading from phantom frame count\n");
767 break;
768 case ES1370_REG_PHANTOM_FRAMEADR:
769 val = ~0U;
770 lwarn ("reading from phantom frame address\n");
771 break;
773 default:
774 val = ~0U;
775 lwarn ("readl %#x -> %#x\n", addr, val);
776 break;
777 }
778 return val;
779 }
782 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
783 int max, int *irq)
784 {
785 uint8_t tmpbuf[4096];
786 uint32_t addr = d->frame_addr;
787 int sc = d->scount & 0xffff;
788 int csc = d->scount >> 16;
789 int csc_bytes = (csc + 1) << d->shift;
790 int cnt = d->frame_cnt >> 16;
791 int size = d->frame_cnt & 0xffff;
792 int left = ((size - cnt + 1) << 2) + d->leftover;
793 int transfered = 0;
794 int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
795 int index = d - &s->chan[0];
797 addr += (cnt << 2) + d->leftover;
799 if (index == ADC_CHANNEL) {
800 while (temp) {
801 int acquired, to_copy;
803 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
804 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
805 if (!acquired)
806 break;
808 cpu_physical_memory_write (addr, tmpbuf, acquired);
810 temp -= acquired;
811 addr += acquired;
812 transfered += acquired;
813 }
814 }
815 else {
816 SWVoiceOut *voice = s->dac_voice[index];
818 while (temp) {
819 int copied, to_copy;
821 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
822 cpu_physical_memory_read (addr, tmpbuf, to_copy);
823 copied = AUD_write (voice, tmpbuf, to_copy);
824 if (!copied)
825 break;
826 temp -= copied;
827 addr += copied;
828 transfered += copied;
829 }
830 }
832 if (csc_bytes == transfered) {
833 *irq = 1;
834 d->scount = sc | (sc << 16);
835 ldebug ("sc = %d, rate = %f\n",
836 (sc + 1) << d->shift,
837 (sc + 1) / (double) 44100);
838 }
839 else {
840 *irq = 0;
841 d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
842 }
844 cnt += (transfered + d->leftover) >> 2;
846 if (s->sctl & loop_sel) {
847 /* Bah, how stupid is that having a 0 represent true value?
848 i just spent few hours on this shit */
849 AUD_log ("es1370: warning", "non looping mode\n");
850 }
851 else {
852 d->frame_cnt = size;
854 if ((uint32_t) cnt <= d->frame_cnt)
855 d->frame_cnt |= cnt << 16;
856 }
858 d->leftover = (transfered + d->leftover) & 3;
859 }
861 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
862 {
863 uint32_t new_status = s->status;
864 int max_bytes, irq;
865 struct chan *d = &s->chan[chan];
866 const struct chan_bits *b = &es1370_chan_bits[chan];
868 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
869 return;
870 }
872 max_bytes = free_or_avail;
873 max_bytes &= ~((1 << d->shift) - 1);
874 if (!max_bytes) {
875 return;
876 }
878 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
880 if (irq) {
881 if (s->sctl & b->sctl_inten) {
882 new_status |= b->stat_int;
883 }
884 }
886 if (new_status != s->status) {
887 es1370_update_status (s, new_status);
888 }
889 }
891 static void es1370_dac1_callback (void *opaque, int free)
892 {
893 ES1370State *s = opaque;
895 es1370_run_channel (s, DAC1_CHANNEL, free);
896 }
898 static void es1370_dac2_callback (void *opaque, int free)
899 {
900 ES1370State *s = opaque;
902 es1370_run_channel (s, DAC2_CHANNEL, free);
903 }
905 static void es1370_adc_callback (void *opaque, int avail)
906 {
907 ES1370State *s = opaque;
909 es1370_run_channel (s, ADC_CHANNEL, avail);
910 }
912 static void es1370_map (PCIDevice *pci_dev, int region_num,
913 uint32_t addr, uint32_t size, int type)
914 {
915 PCIES1370State *d = (PCIES1370State *) pci_dev;
916 ES1370State *s = &d->es1370;
918 (void) region_num;
919 (void) size;
920 (void) type;
922 register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
923 register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
924 register_ioport_write (addr, 0x40, 4, es1370_writel, s);
926 register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
927 register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
928 register_ioport_read (addr, 0x40, 4, es1370_readl, s);
929 }
931 static void es1370_save (QEMUFile *f, void *opaque)
932 {
933 ES1370State *s = opaque;
934 size_t i;
936 for (i = 0; i < NB_CHANNELS; ++i) {
937 struct chan *d = &s->chan[i];
938 qemu_put_be32s (f, &d->shift);
939 qemu_put_be32s (f, &d->leftover);
940 qemu_put_be32s (f, &d->scount);
941 qemu_put_be32s (f, &d->frame_addr);
942 qemu_put_be32s (f, &d->frame_cnt);
943 }
944 qemu_put_be32s (f, &s->ctl);
945 qemu_put_be32s (f, &s->status);
946 qemu_put_be32s (f, &s->mempage);
947 qemu_put_be32s (f, &s->codec);
948 qemu_put_be32s (f, &s->sctl);
949 }
951 static int es1370_load (QEMUFile *f, void *opaque, int version_id)
952 {
953 uint32_t ctl, sctl;
954 ES1370State *s = opaque;
955 size_t i;
957 if (version_id != 1)
958 return -EINVAL;
960 for (i = 0; i < NB_CHANNELS; ++i) {
961 struct chan *d = &s->chan[i];
962 qemu_get_be32s (f, &d->shift);
963 qemu_get_be32s (f, &d->leftover);
964 qemu_get_be32s (f, &d->scount);
965 qemu_get_be32s (f, &d->frame_addr);
966 qemu_get_be32s (f, &d->frame_cnt);
967 if (i == ADC_CHANNEL) {
968 if (s->adc_voice) {
969 AUD_close_in (&s->card, s->adc_voice);
970 s->adc_voice = NULL;
971 }
972 }
973 else {
974 if (s->dac_voice[i]) {
975 AUD_close_out (&s->card, s->dac_voice[i]);
976 s->dac_voice[i] = NULL;
977 }
978 }
979 }
981 qemu_get_be32s (f, &ctl);
982 qemu_get_be32s (f, &s->status);
983 qemu_get_be32s (f, &s->mempage);
984 qemu_get_be32s (f, &s->codec);
985 qemu_get_be32s (f, &sctl);
987 s->ctl = 0;
988 s->sctl = 0;
989 es1370_update_voices (s, ctl, sctl);
990 return 0;
991 }
993 static void es1370_on_reset (void *opaque)
994 {
995 ES1370State *s = opaque;
996 es1370_reset (s);
997 }
999 int es1370_init (PCIBus *bus, AudioState *audio)
1001 PCIES1370State *d;
1002 ES1370State *s;
1003 uint8_t *c;
1005 if (!bus) {
1006 dolog ("No PCI bus\n");
1007 return -1;
1010 if (!audio) {
1011 dolog ("No audio state\n");
1012 return -1;
1015 d = (PCIES1370State *) pci_register_device (bus, "ES1370",
1016 sizeof (PCIES1370State),
1017 -1, NULL, NULL);
1019 if (!d) {
1020 AUD_log (NULL, "Failed to register PCI device for ES1370\n");
1021 return -1;
1024 c = d->dev.config;
1025 c[0x00] = 0x74;
1026 c[0x01] = 0x12;
1027 c[0x02] = 0x00;
1028 c[0x03] = 0x50;
1029 c[0x07] = 2 << 1;
1030 c[0x0a] = 0x01;
1031 c[0x0b] = 0x04;
1033 #if 1
1034 c[0x2c] = 0x42;
1035 c[0x2d] = 0x49;
1036 c[0x2e] = 0x4c;
1037 c[0x2f] = 0x4c;
1038 #else
1039 c[0x2c] = 0x74;
1040 c[0x2d] = 0x12;
1041 c[0x2e] = 0x71;
1042 c[0x2f] = 0x13;
1043 c[0x34] = 0xdc;
1044 c[0x3c] = 10;
1045 c[0xdc] = 0x00;
1046 #endif
1048 c[0x3d] = 1;
1049 c[0x3e] = 0x0c;
1050 c[0x3f] = 0x80;
1052 s = &d->es1370;
1053 s->pci_dev = &d->dev;
1055 pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
1056 register_savevm ("es1370", 0, 1, es1370_save, es1370_load, s);
1057 qemu_register_reset (es1370_on_reset, s);
1059 AUD_register_card (audio, "es1370", &s->card);
1060 es1370_reset (s);
1061 return 0;