debuggers.hg

view tools/ioemu/hw/i8259.c @ 10995:08a11694b109

[qemu] Update ioemu to qemu 0.8.2.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Mon Aug 07 18:25:30 2006 +0100 (2006-08-07)
parents b450f21472a0
children 00618037d37d
line source
1 /*
2 * QEMU 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 /* debug PIC */
27 //#define DEBUG_PIC
29 //#define DEBUG_IRQ_LATENCY
30 //#define DEBUG_IRQ_COUNT
32 typedef struct PicState {
33 uint8_t last_irr; /* edge detection */
34 uint8_t irr; /* interrupt request register */
35 uint8_t imr; /* interrupt mask register */
36 uint8_t isr; /* interrupt service register */
37 uint8_t priority_add; /* highest irq priority */
38 uint8_t irq_base;
39 uint8_t read_reg_select;
40 uint8_t poll;
41 uint8_t special_mask;
42 uint8_t init_state;
43 uint8_t auto_eoi;
44 uint8_t rotate_on_auto_eoi;
45 uint8_t special_fully_nested_mode;
46 uint8_t init4; /* true if 4 byte init */
47 uint8_t elcr; /* PIIX edge/trigger selection*/
48 uint8_t elcr_mask;
49 PicState2 *pics_state;
50 } PicState;
52 struct PicState2 {
53 /* 0 is master pic, 1 is slave pic */
54 /* XXX: better separation between the two pics */
55 PicState pics[2];
56 IRQRequestFunc *irq_request;
57 void *irq_request_opaque;
58 /* IOAPIC callback support */
59 SetIRQFunc *alt_irq_func;
60 void *alt_irq_opaque;
61 };
63 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
64 static int irq_level[16];
65 #endif
66 #ifdef DEBUG_IRQ_COUNT
67 static uint64_t irq_count[16];
68 #endif
70 /* set irq level. If an edge is detected, then the IRR is set to 1 */
71 static inline void pic_set_irq1(PicState *s, int irq, int level)
72 {
73 int mask;
74 mask = 1 << irq;
75 if (s->elcr & mask) {
76 /* level triggered */
77 if (level) {
78 s->irr |= mask;
79 s->last_irr |= mask;
80 } else {
81 s->irr &= ~mask;
82 s->last_irr &= ~mask;
83 }
84 } else {
85 /* edge triggered */
86 if (level) {
87 if ((s->last_irr & mask) == 0)
88 s->irr |= mask;
89 s->last_irr |= mask;
90 } else {
91 s->last_irr &= ~mask;
92 }
93 }
94 }
96 /* return the highest priority found in mask (highest = smallest
97 number). Return 8 if no irq */
98 static inline int get_priority(PicState *s, int mask)
99 {
100 int priority;
101 if (mask == 0)
102 return 8;
103 priority = 0;
104 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
105 priority++;
106 return priority;
107 }
109 /* return the pic wanted interrupt. return -1 if none */
110 static int pic_get_irq(PicState *s)
111 {
112 int mask, cur_priority, priority;
114 mask = s->irr & ~s->imr;
115 priority = get_priority(s, mask);
116 if (priority == 8)
117 return -1;
118 /* compute current priority. If special fully nested mode on the
119 master, the IRQ coming from the slave is not taken into account
120 for the priority computation. */
121 mask = s->isr;
122 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
123 mask &= ~(1 << 2);
124 cur_priority = get_priority(s, mask);
125 if (priority < cur_priority) {
126 /* higher priority found: an irq should be generated */
127 return (priority + s->priority_add) & 7;
128 } else {
129 return -1;
130 }
131 }
133 /* raise irq to CPU if necessary. must be called every time the active
134 irq may change */
135 /* XXX: should not export it, but it is needed for an APIC kludge */
136 void pic_update_irq(PicState2 *s)
137 {
138 int irq2, irq;
140 /* first look at slave pic */
141 irq2 = pic_get_irq(&s->pics[1]);
142 if (irq2 >= 0) {
143 /* if irq request by slave pic, signal master PIC */
144 pic_set_irq1(&s->pics[0], 2, 1);
145 pic_set_irq1(&s->pics[0], 2, 0);
146 }
147 /* look at requested irq */
148 irq = pic_get_irq(&s->pics[0]);
149 if (irq >= 0) {
150 #if defined(DEBUG_PIC)
151 {
152 int i;
153 for(i = 0; i < 2; i++) {
154 printf("pic%d: imr=%x irr=%x padd=%d\n",
155 i, s->pics[i].imr, s->pics[i].irr,
156 s->pics[i].priority_add);
158 }
159 }
160 printf("pic: cpu_interrupt\n");
161 #endif
162 s->irq_request(s->irq_request_opaque, 1);
163 }
164 }
166 #ifdef DEBUG_IRQ_LATENCY
167 int64_t irq_time[16];
168 #endif
170 void pic_set_irq_new(void *opaque, int irq, int level)
171 {
172 PicState2 *s = opaque;
174 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
175 if (level != irq_level[irq]) {
176 #if defined(DEBUG_PIC)
177 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
178 #endif
179 irq_level[irq] = level;
180 #ifdef DEBUG_IRQ_COUNT
181 if (level == 1)
182 irq_count[irq]++;
183 #endif
184 }
185 #endif
186 #ifdef DEBUG_IRQ_LATENCY
187 if (level) {
188 irq_time[irq] = qemu_get_clock(vm_clock);
189 }
190 #endif
191 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
192 /* used for IOAPIC irqs */
193 if (s->alt_irq_func)
194 s->alt_irq_func(s->alt_irq_opaque, irq, level);
195 pic_update_irq(s);
196 }
198 /* obsolete function */
199 void pic_set_irq(int irq, int level)
200 {
201 pic_set_irq_new(isa_pic, irq, level);
202 }
204 /* acknowledge interrupt 'irq' */
205 static inline void pic_intack(PicState *s, int irq)
206 {
207 if (s->auto_eoi) {
208 if (s->rotate_on_auto_eoi)
209 s->priority_add = (irq + 1) & 7;
210 } else {
211 s->isr |= (1 << irq);
212 }
213 /* We don't clear a level sensitive interrupt here */
214 if (!(s->elcr & (1 << irq)))
215 s->irr &= ~(1 << irq);
216 }
218 int pic_read_irq(PicState2 *s)
219 {
220 int irq, irq2, intno;
222 irq = pic_get_irq(&s->pics[0]);
223 if (irq >= 0) {
224 pic_intack(&s->pics[0], irq);
225 if (irq == 2) {
226 irq2 = pic_get_irq(&s->pics[1]);
227 if (irq2 >= 0) {
228 pic_intack(&s->pics[1], irq2);
229 } else {
230 /* spurious IRQ on slave controller */
231 irq2 = 7;
232 }
233 intno = s->pics[1].irq_base + irq2;
234 irq = irq2 + 8;
235 } else {
236 intno = s->pics[0].irq_base + irq;
237 }
238 } else {
239 /* spurious IRQ on host controller */
240 irq = 7;
241 intno = s->pics[0].irq_base + irq;
242 }
243 pic_update_irq(s);
245 #ifdef DEBUG_IRQ_LATENCY
246 printf("IRQ%d latency=%0.3fus\n",
247 irq,
248 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
249 #endif
250 #if defined(DEBUG_PIC)
251 printf("pic_interrupt: irq=%d\n", irq);
252 #endif
253 return intno;
254 }
256 static void pic_reset(void *opaque)
257 {
258 PicState *s = opaque;
260 s->last_irr = 0;
261 s->irr = 0;
262 s->imr = 0;
263 s->isr = 0;
264 s->priority_add = 0;
265 s->irq_base = 0;
266 s->read_reg_select = 0;
267 s->poll = 0;
268 s->special_mask = 0;
269 s->init_state = 0;
270 s->auto_eoi = 0;
271 s->rotate_on_auto_eoi = 0;
272 s->special_fully_nested_mode = 0;
273 s->init4 = 0;
274 /* Note: ELCR is not reset */
275 }
277 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
278 {
279 PicState *s = opaque;
280 int priority, cmd, irq;
282 #ifdef DEBUG_PIC
283 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
284 #endif
285 addr &= 1;
286 if (addr == 0) {
287 if (val & 0x10) {
288 /* init */
289 pic_reset(s);
290 /* deassert a pending interrupt */
291 s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
292 s->init_state = 1;
293 s->init4 = val & 1;
294 if (val & 0x02)
295 hw_error("single mode not supported");
296 if (val & 0x08)
297 hw_error("level sensitive irq not supported");
298 } else if (val & 0x08) {
299 if (val & 0x04)
300 s->poll = 1;
301 if (val & 0x02)
302 s->read_reg_select = val & 1;
303 if (val & 0x40)
304 s->special_mask = (val >> 5) & 1;
305 } else {
306 cmd = val >> 5;
307 switch(cmd) {
308 case 0:
309 case 4:
310 s->rotate_on_auto_eoi = cmd >> 2;
311 break;
312 case 1: /* end of interrupt */
313 case 5:
314 priority = get_priority(s, s->isr);
315 if (priority != 8) {
316 irq = (priority + s->priority_add) & 7;
317 s->isr &= ~(1 << irq);
318 if (cmd == 5)
319 s->priority_add = (irq + 1) & 7;
320 pic_update_irq(s->pics_state);
321 }
322 break;
323 case 3:
324 irq = val & 7;
325 s->isr &= ~(1 << irq);
326 pic_update_irq(s->pics_state);
327 break;
328 case 6:
329 s->priority_add = (val + 1) & 7;
330 pic_update_irq(s->pics_state);
331 break;
332 case 7:
333 irq = val & 7;
334 s->isr &= ~(1 << irq);
335 s->priority_add = (irq + 1) & 7;
336 pic_update_irq(s->pics_state);
337 break;
338 default:
339 /* no operation */
340 break;
341 }
342 }
343 } else {
344 switch(s->init_state) {
345 case 0:
346 /* normal mode */
347 s->imr = val;
348 pic_update_irq(s->pics_state);
349 break;
350 case 1:
351 s->irq_base = val & 0xf8;
352 s->init_state = 2;
353 break;
354 case 2:
355 if (s->init4) {
356 s->init_state = 3;
357 } else {
358 s->init_state = 0;
359 }
360 break;
361 case 3:
362 s->special_fully_nested_mode = (val >> 4) & 1;
363 s->auto_eoi = (val >> 1) & 1;
364 s->init_state = 0;
365 break;
366 }
367 }
368 }
370 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
371 {
372 int ret;
374 ret = pic_get_irq(s);
375 if (ret >= 0) {
376 if (addr1 >> 7) {
377 s->pics_state->pics[0].isr &= ~(1 << 2);
378 s->pics_state->pics[0].irr &= ~(1 << 2);
379 }
380 s->irr &= ~(1 << ret);
381 s->isr &= ~(1 << ret);
382 if (addr1 >> 7 || ret != 2)
383 pic_update_irq(s->pics_state);
384 } else {
385 ret = 0x07;
386 pic_update_irq(s->pics_state);
387 }
389 return ret;
390 }
392 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
393 {
394 PicState *s = opaque;
395 unsigned int addr;
396 int ret;
398 addr = addr1;
399 addr &= 1;
400 if (s->poll) {
401 ret = pic_poll_read(s, addr1);
402 s->poll = 0;
403 } else {
404 if (addr == 0) {
405 if (s->read_reg_select)
406 ret = s->isr;
407 else
408 ret = s->irr;
409 } else {
410 ret = s->imr;
411 }
412 }
413 #ifdef DEBUG_PIC
414 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
415 #endif
416 return ret;
417 }
419 /* memory mapped interrupt status */
420 /* XXX: may be the same than pic_read_irq() */
421 uint32_t pic_intack_read(PicState2 *s)
422 {
423 int ret;
425 ret = pic_poll_read(&s->pics[0], 0x00);
426 if (ret == 2)
427 ret = pic_poll_read(&s->pics[1], 0x80) + 8;
428 /* Prepare for ISR read */
429 s->pics[0].read_reg_select = 1;
431 return ret;
432 }
434 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
435 {
436 PicState *s = opaque;
437 s->elcr = val & s->elcr_mask;
438 }
440 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
441 {
442 PicState *s = opaque;
443 return s->elcr;
444 }
446 static void pic_save(QEMUFile *f, void *opaque)
447 {
448 PicState *s = opaque;
450 qemu_put_8s(f, &s->last_irr);
451 qemu_put_8s(f, &s->irr);
452 qemu_put_8s(f, &s->imr);
453 qemu_put_8s(f, &s->isr);
454 qemu_put_8s(f, &s->priority_add);
455 qemu_put_8s(f, &s->irq_base);
456 qemu_put_8s(f, &s->read_reg_select);
457 qemu_put_8s(f, &s->poll);
458 qemu_put_8s(f, &s->special_mask);
459 qemu_put_8s(f, &s->init_state);
460 qemu_put_8s(f, &s->auto_eoi);
461 qemu_put_8s(f, &s->rotate_on_auto_eoi);
462 qemu_put_8s(f, &s->special_fully_nested_mode);
463 qemu_put_8s(f, &s->init4);
464 qemu_put_8s(f, &s->elcr);
465 }
467 static int pic_load(QEMUFile *f, void *opaque, int version_id)
468 {
469 PicState *s = opaque;
471 if (version_id != 1)
472 return -EINVAL;
474 qemu_get_8s(f, &s->last_irr);
475 qemu_get_8s(f, &s->irr);
476 qemu_get_8s(f, &s->imr);
477 qemu_get_8s(f, &s->isr);
478 qemu_get_8s(f, &s->priority_add);
479 qemu_get_8s(f, &s->irq_base);
480 qemu_get_8s(f, &s->read_reg_select);
481 qemu_get_8s(f, &s->poll);
482 qemu_get_8s(f, &s->special_mask);
483 qemu_get_8s(f, &s->init_state);
484 qemu_get_8s(f, &s->auto_eoi);
485 qemu_get_8s(f, &s->rotate_on_auto_eoi);
486 qemu_get_8s(f, &s->special_fully_nested_mode);
487 qemu_get_8s(f, &s->init4);
488 qemu_get_8s(f, &s->elcr);
489 return 0;
490 }
492 /* XXX: add generic master/slave system */
493 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
494 {
495 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
496 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
497 if (elcr_addr >= 0) {
498 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
499 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
500 }
501 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
502 qemu_register_reset(pic_reset, s);
503 }
505 void pic_info(void)
506 {
507 int i;
508 PicState *s;
510 if (!isa_pic)
511 return;
513 for(i=0;i<2;i++) {
514 s = &isa_pic->pics[i];
515 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
516 i, s->irr, s->imr, s->isr, s->priority_add,
517 s->irq_base, s->read_reg_select, s->elcr,
518 s->special_fully_nested_mode);
519 }
520 }
522 void irq_info(void)
523 {
524 #ifndef DEBUG_IRQ_COUNT
525 term_printf("irq statistic code not compiled.\n");
526 #else
527 int i;
528 int64_t count;
530 term_printf("IRQ statistics:\n");
531 for (i = 0; i < 16; i++) {
532 count = irq_count[i];
533 if (count > 0)
534 term_printf("%2d: %" PRId64 "\n", i, count);
535 }
536 #endif
537 }
539 PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
540 {
541 PicState2 *s;
542 s = qemu_mallocz(sizeof(PicState2));
543 if (!s)
544 return NULL;
545 pic_init1(0x20, 0x4d0, &s->pics[0]);
546 pic_init1(0xa0, 0x4d1, &s->pics[1]);
547 s->pics[0].elcr_mask = 0xf8;
548 s->pics[1].elcr_mask = 0xde;
549 s->irq_request = irq_request;
550 s->irq_request_opaque = irq_request_opaque;
551 s->pics[0].pics_state = s;
552 s->pics[1].pics_state = s;
553 return s;
554 }
556 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
557 void *alt_irq_opaque)
558 {
559 s->alt_irq_func = alt_irq_func;
560 s->alt_irq_opaque = alt_irq_opaque;
561 }