debuggers.hg

view tools/ioemu/hw/prep_pci.c @ 10995:08a11694b109

[qemu] Update ioemu to qemu 0.8.2.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Mon Aug 07 18:25:30 2006 +0100 (2006-08-07)
parents
children 00618037d37d
line source
1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "vl.h"
26 typedef uint32_t pci_addr_t;
27 #include "pci_host.h"
29 typedef PCIHostState PREPPCIState;
31 static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val)
32 {
33 PREPPCIState *s = opaque;
34 s->config_reg = val;
35 }
37 static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr)
38 {
39 PREPPCIState *s = opaque;
40 return s->config_reg;
41 }
43 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
44 {
45 int i;
47 for(i = 0; i < 11; i++) {
48 if ((addr & (1 << (11 + i))) != 0)
49 break;
50 }
51 return (addr & 0x7ff) | (i << 11);
52 }
54 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
55 {
56 PREPPCIState *s = opaque;
57 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
58 }
60 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
61 {
62 PREPPCIState *s = opaque;
63 #ifdef TARGET_WORDS_BIGENDIAN
64 val = bswap16(val);
65 #endif
66 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
67 }
69 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
70 {
71 PREPPCIState *s = opaque;
72 #ifdef TARGET_WORDS_BIGENDIAN
73 val = bswap32(val);
74 #endif
75 pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
76 }
78 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
79 {
80 PREPPCIState *s = opaque;
81 uint32_t val;
82 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
83 return val;
84 }
86 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
87 {
88 PREPPCIState *s = opaque;
89 uint32_t val;
90 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
91 #ifdef TARGET_WORDS_BIGENDIAN
92 val = bswap16(val);
93 #endif
94 return val;
95 }
97 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
98 {
99 PREPPCIState *s = opaque;
100 uint32_t val;
101 val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
102 #ifdef TARGET_WORDS_BIGENDIAN
103 val = bswap32(val);
104 #endif
105 return val;
106 }
108 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
109 &PPC_PCIIO_writeb,
110 &PPC_PCIIO_writew,
111 &PPC_PCIIO_writel,
112 };
114 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
115 &PPC_PCIIO_readb,
116 &PPC_PCIIO_readw,
117 &PPC_PCIIO_readl,
118 };
120 static void prep_set_irq(PCIDevice *d, void *pic, int irq_num, int level)
121 {
122 /* XXX: we do not simulate the hardware - we rely on the BIOS to
123 set correctly for irq line field */
124 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
125 }
127 PCIBus *pci_prep_init(void)
128 {
129 PREPPCIState *s;
130 PCIDevice *d;
131 int PPC_io_memory;
133 s = qemu_mallocz(sizeof(PREPPCIState));
134 s->bus = pci_register_bus(prep_set_irq, NULL, 0);
136 register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
137 register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
139 register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
140 register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
141 register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
142 register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
143 register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
144 register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
146 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
147 PPC_PCIIO_write, s);
148 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
150 /* PCI host bridge */
151 d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
152 sizeof(PCIDevice), 0, NULL, NULL);
153 d->config[0x00] = 0x57; // vendor_id : Motorola
154 d->config[0x01] = 0x10;
155 d->config[0x02] = 0x01; // device_id : Raven
156 d->config[0x03] = 0x48;
157 d->config[0x08] = 0x00; // revision
158 d->config[0x0A] = 0x00; // class_sub = pci host
159 d->config[0x0B] = 0x06; // class_base = PCI_bridge
160 d->config[0x0C] = 0x08; // cache_line_size
161 d->config[0x0D] = 0x10; // latency_timer
162 d->config[0x0E] = 0x00; // header_type
163 d->config[0x34] = 0x00; // capabilities_pointer
165 return s->bus;
166 }