debuggers.hg

view xen/drivers/char/ns16550.c @ 20955:12fc55dffb6b

Handle bogus serial ports that appear normal, but don't generate
interrupts e.g. the "remote serial console" on Blades.

Authored-by: Gary Grebus <Gary.Grebus@oracle.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Feb 08 08:49:19 2010 +0000 (2010-02-08)
parents 5a224e101cb3
children 8cb6e7eff2ba
line source
1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
11 #include <xen/config.h>
12 #include <xen/console.h>
13 #include <xen/init.h>
14 #include <xen/irq.h>
15 #include <xen/sched.h>
16 #include <xen/serial.h>
17 #include <xen/iocap.h>
18 #include <asm/io.h>
20 /*
21 * Configure serial port with a string:
22 * <baud>[/<clock_hz>][,DPS[,<io-base>[,<irq>]]].
23 * The tail of the string can be omitted if platform defaults are sufficient.
24 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
25 * can be specified in place of a numeric baud rate. Polled mode is specified
26 * by requesting irq 0.
27 */
28 static char __initdata opt_com1[30] = "";
29 static char __initdata opt_com2[30] = "";
30 string_param("com1", opt_com1);
31 string_param("com2", opt_com2);
33 static struct ns16550 {
34 int baud, clock_hz, data_bits, parity, stop_bits, irq;
35 unsigned long io_base; /* I/O port or memory-mapped I/O address. */
36 char *remapped_io_base; /* Remapped virtual address of mmap I/O. */
37 /* UART with IRQ line: interrupt-driven I/O. */
38 struct irqaction irqaction;
39 /* UART with no IRQ line: periodically-polled I/O. */
40 struct timer timer;
41 unsigned int timeout_ms;
42 int probing, intr_works;
43 } ns16550_com[2] = { { 0 } };
45 /* Register offsets */
46 #define RBR 0x00 /* receive buffer */
47 #define THR 0x00 /* transmit holding */
48 #define IER 0x01 /* interrupt enable */
49 #define IIR 0x02 /* interrupt identity */
50 #define FCR 0x02 /* FIFO control */
51 #define LCR 0x03 /* line control */
52 #define MCR 0x04 /* Modem control */
53 #define LSR 0x05 /* line status */
54 #define MSR 0x06 /* Modem status */
55 #define DLL 0x00 /* divisor latch (ls) (DLAB=1) */
56 #define DLM 0x01 /* divisor latch (ms) (DLAB=1) */
58 /* Interrupt Enable Register */
59 #define IER_ERDAI 0x01 /* rx data recv'd */
60 #define IER_ETHREI 0x02 /* tx reg. empty */
61 #define IER_ELSI 0x04 /* rx line status */
62 #define IER_EMSI 0x08 /* MODEM status */
64 /* Interrupt Identification Register */
65 #define IIR_NOINT 0x01 /* no interrupt pending */
66 #define IIR_IMASK 0x06 /* interrupt identity: */
67 #define IIR_LSI 0x06 /* - rx line status */
68 #define IIR_RDAI 0x04 /* - rx data recv'd */
69 #define IIR_THREI 0x02 /* - tx reg. empty */
70 #define IIR_MSI 0x00 /* - MODEM status */
72 /* FIFO Control Register */
73 #define FCR_ENABLE 0x01 /* enable FIFO */
74 #define FCR_CLRX 0x02 /* clear Rx FIFO */
75 #define FCR_CLTX 0x04 /* clear Tx FIFO */
76 #define FCR_DMA 0x10 /* enter DMA mode */
77 #define FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
78 #define FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
79 #define FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
80 #define FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
82 /* Line Control Register */
83 #define LCR_DLAB 0x80 /* Divisor Latch Access */
85 /* Modem Control Register */
86 #define MCR_DTR 0x01 /* Data Terminal Ready */
87 #define MCR_RTS 0x02 /* Request to Send */
88 #define MCR_OUT2 0x08 /* OUT2: interrupt mask */
89 #define MCR_LOOP 0x10 /* Enable loopback test mode */
91 /* Line Status Register */
92 #define LSR_DR 0x01 /* Data ready */
93 #define LSR_OE 0x02 /* Overrun */
94 #define LSR_PE 0x04 /* Parity error */
95 #define LSR_FE 0x08 /* Framing error */
96 #define LSR_BI 0x10 /* Break */
97 #define LSR_THRE 0x20 /* Xmit hold reg empty */
98 #define LSR_TEMT 0x40 /* Xmitter empty */
99 #define LSR_ERR 0x80 /* Error */
101 /* These parity settings can be ORed directly into the LCR. */
102 #define PARITY_NONE (0<<3)
103 #define PARITY_ODD (1<<3)
104 #define PARITY_EVEN (3<<3)
105 #define PARITY_MARK (5<<3)
106 #define PARITY_SPACE (7<<3)
108 /* Frequency of external clock source. This definition assumes PC platform. */
109 #define UART_CLOCK_HZ 1843200
111 static char ns_read_reg(struct ns16550 *uart, int reg)
112 {
113 if ( uart->remapped_io_base == NULL )
114 return inb(uart->io_base + reg);
115 return readb(uart->remapped_io_base + reg);
116 }
118 static void ns_write_reg(struct ns16550 *uart, int reg, char c)
119 {
120 if ( uart->remapped_io_base == NULL )
121 return outb(c, uart->io_base + reg);
122 writeb(c, uart->remapped_io_base + reg);
123 }
125 static void ns16550_interrupt(
126 int irq, void *dev_id, struct cpu_user_regs *regs)
127 {
128 struct serial_port *port = dev_id;
129 struct ns16550 *uart = port->uart;
131 if (uart->intr_works == 0)
132 {
133 uart->probing = 0;
134 uart->intr_works = 1;
135 stop_timer(&uart->timer);
136 }
138 while ( !(ns_read_reg(uart, IIR) & IIR_NOINT) )
139 {
140 char lsr = ns_read_reg(uart, LSR);
141 if ( lsr & LSR_THRE )
142 serial_tx_interrupt(port, regs);
143 if ( lsr & LSR_DR )
144 serial_rx_interrupt(port, regs);
145 }
146 }
148 static void ns16550_poll(void *data)
149 {
150 struct serial_port *port = data;
151 struct ns16550 *uart = port->uart;
152 struct cpu_user_regs *regs = guest_cpu_user_regs();
154 if ( uart->intr_works )
155 return; /* Interrupts work - no more polling */
157 if ( uart->probing ) {
158 uart->probing = 0;
159 if ( (ns_read_reg(uart, LSR) & 0xff) == 0xff )
160 return; /* All bits set - probably no UART present */
161 }
163 while ( ns_read_reg(uart, LSR) & LSR_DR )
164 serial_rx_interrupt(port, regs);
166 if ( ns_read_reg(uart, LSR) & LSR_THRE )
167 serial_tx_interrupt(port, regs);
169 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
170 }
172 static int ns16550_tx_empty(struct serial_port *port)
173 {
174 struct ns16550 *uart = port->uart;
175 return !!(ns_read_reg(uart, LSR) & LSR_THRE);
176 }
178 static void ns16550_putc(struct serial_port *port, char c)
179 {
180 struct ns16550 *uart = port->uart;
181 ns_write_reg(uart, THR, c);
182 }
184 static int ns16550_getc(struct serial_port *port, char *pc)
185 {
186 struct ns16550 *uart = port->uart;
188 if ( !(ns_read_reg(uart, LSR) & LSR_DR) )
189 return 0;
191 *pc = ns_read_reg(uart, RBR);
192 return 1;
193 }
195 static void __devinit ns16550_init_preirq(struct serial_port *port)
196 {
197 struct ns16550 *uart = port->uart;
198 unsigned char lcr;
199 unsigned int divisor;
201 /* I/O ports are distinguished by their size (16 bits). */
202 if ( uart->io_base >= 0x10000 )
203 uart->remapped_io_base = (char *)ioremap(uart->io_base, 8);
205 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
207 /* No interrupts. */
208 ns_write_reg(uart, IER, 0);
210 /* Line control and baud-rate generator. */
211 ns_write_reg(uart, LCR, lcr | LCR_DLAB);
212 if ( uart->baud != BAUD_AUTO )
213 {
214 /* Baud rate specified: program it into the divisor latch. */
215 divisor = uart->clock_hz / (uart->baud << 4);
216 ns_write_reg(uart, DLL, (char)divisor);
217 ns_write_reg(uart, DLM, (char)(divisor >> 8));
218 }
219 else
220 {
221 /* Baud rate already set: read it out from the divisor latch. */
222 divisor = ns_read_reg(uart, DLL);
223 divisor |= ns_read_reg(uart, DLM) << 8;
224 uart->baud = uart->clock_hz / (divisor << 4);
225 }
226 ns_write_reg(uart, LCR, lcr);
228 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
229 ns_write_reg(uart, MCR, MCR_DTR | MCR_RTS);
231 /* Enable and clear the FIFOs. Set a large trigger threshold. */
232 ns_write_reg(uart, FCR, FCR_ENABLE | FCR_CLRX | FCR_CLTX | FCR_TRG14);
234 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
235 if ( ((ns_read_reg(uart, IIR) & 0xc0) == 0xc0) &&
236 ((ns_read_reg(uart, FCR) & FCR_TRG14) == FCR_TRG14) )
237 port->tx_fifo_size = 16;
238 }
240 static void __devinit ns16550_init_postirq(struct serial_port *port)
241 {
242 struct ns16550 *uart = port->uart;
243 int rc, bits;
245 if ( uart->irq < 0 )
246 return;
248 serial_async_transmit(port);
250 init_timer(&uart->timer, ns16550_poll, port, 0);
251 /* Calculate time to fill RX FIFO and/or empty TX FIFO for polling. */
252 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
253 uart->timeout_ms = max_t(
254 unsigned int, 1, (bits * port->tx_fifo_size * 1000) / uart->baud);
256 if ( uart->irq == 0 )
257 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
258 else
259 {
260 uart->irqaction.handler = ns16550_interrupt;
261 uart->irqaction.name = "ns16550";
262 uart->irqaction.dev_id = port;
263 if ( (rc = setup_irq(uart->irq, &uart->irqaction)) != 0 )
264 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
266 /* Master interrupt enable; also keep DTR/RTS asserted. */
267 ns_write_reg(uart, MCR, MCR_OUT2 | MCR_DTR | MCR_RTS);
269 /* Enable receive and transmit interrupts. */
270 ns_write_reg(uart, IER, IER_ERDAI | IER_ETHREI);
272 /* Do a timed write to make sure we are getting interrupts. */
273 uart->probing = 1;
274 uart->intr_works = 0;
275 ns_write_reg(uart, THR, 0xff);
276 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
277 }
278 }
280 #ifdef CONFIG_X86
281 static void __init ns16550_endboot(struct serial_port *port)
282 {
283 struct ns16550 *uart = port->uart;
284 if ( ioports_deny_access(dom0, uart->io_base, uart->io_base + 7) != 0 )
285 BUG();
286 }
287 #else
288 #define ns16550_endboot NULL
289 #endif
291 static int ns16550_irq(struct serial_port *port)
292 {
293 struct ns16550 *uart = port->uart;
294 return ((uart->irq > 0) ? uart->irq : -1);
295 }
297 static struct uart_driver __read_mostly ns16550_driver = {
298 .init_preirq = ns16550_init_preirq,
299 .init_postirq = ns16550_init_postirq,
300 .endboot = ns16550_endboot,
301 .tx_empty = ns16550_tx_empty,
302 .putc = ns16550_putc,
303 .getc = ns16550_getc,
304 .irq = ns16550_irq
305 };
307 static int __init parse_parity_char(int c)
308 {
309 switch ( c )
310 {
311 case 'n':
312 return PARITY_NONE;
313 case 'o':
314 return PARITY_ODD;
315 case 'e':
316 return PARITY_EVEN;
317 case 'm':
318 return PARITY_MARK;
319 case 's':
320 return PARITY_SPACE;
321 }
322 return 0;
323 }
325 static int __init check_existence(struct ns16550 *uart)
326 {
327 unsigned char status, scratch, scratch2, scratch3;
329 /*
330 * We can't poke MMIO UARTs until they get I/O remapped later. Assume that
331 * if we're getting MMIO UARTs, the arch code knows what it's doing.
332 */
333 if ( uart->io_base >= 0x10000 )
334 return 1;
336 /*
337 * Do a simple existence test first; if we fail this,
338 * there's no point trying anything else.
339 */
340 scratch = ns_read_reg(uart, IER);
341 ns_write_reg(uart, IER, 0);
343 /*
344 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
345 * 16C754B) allow only to modify them if an EFR bit is set.
346 */
347 scratch2 = ns_read_reg(uart, IER) & 0x0f;
348 ns_write_reg(uart, IER, 0x0F);
349 scratch3 = ns_read_reg(uart, IER) & 0x0f;
350 ns_write_reg(uart, IER, scratch);
351 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
352 return 0;
354 /*
355 * Check to see if a UART is really there.
356 * Use loopback test mode.
357 */
358 ns_write_reg(uart, MCR, MCR_LOOP | 0x0A);
359 status = ns_read_reg(uart, MSR) & 0xF0;
360 return (status == 0x90);
361 }
363 #define PARSE_ERR(_f, _a...) \
364 do { \
365 printk( "ERROR: " _f "\n" , ## _a ); \
366 return; \
367 } while ( 0 )
369 static void __init ns16550_parse_port_config(
370 struct ns16550 *uart, const char *conf)
371 {
372 int baud;
374 /* No user-specified configuration? */
375 if ( (conf == NULL) || (*conf == '\0') )
376 {
377 /* Some platforms may automatically probe the UART configuartion. */
378 if ( uart->baud != 0 )
379 goto config_parsed;
380 return;
381 }
383 if ( strncmp(conf, "auto", 4) == 0 )
384 {
385 uart->baud = BAUD_AUTO;
386 conf += 4;
387 }
388 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
389 uart->baud = baud;
391 if ( *conf == '/')
392 {
393 conf++;
394 uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4;
395 }
397 if ( *conf != ',' )
398 goto config_parsed;
399 conf++;
401 uart->data_bits = simple_strtoul(conf, &conf, 10);
403 uart->parity = parse_parity_char(*conf);
404 conf++;
406 uart->stop_bits = simple_strtoul(conf, &conf, 10);
408 if ( *conf == ',' )
409 {
410 conf++;
411 uart->io_base = simple_strtoul(conf, &conf, 0);
413 if ( *conf == ',' )
414 {
415 conf++;
416 uart->irq = simple_strtoul(conf, &conf, 10);
417 }
418 }
420 config_parsed:
421 /* Sanity checks. */
422 if ( (uart->baud != BAUD_AUTO) &&
423 ((uart->baud < 1200) || (uart->baud > 115200)) )
424 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
425 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
426 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
427 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
428 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
429 if ( uart->io_base == 0 )
430 PARSE_ERR("I/O base address must be specified.");
431 if ( !check_existence(uart) )
432 PARSE_ERR("16550-compatible serial UART not present");
434 /* Register with generic serial driver. */
435 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
436 }
438 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
439 {
440 struct ns16550 *uart;
442 if ( (index < 0) || (index > 1) )
443 return;
445 uart = &ns16550_com[index];
447 uart->baud = (defaults->baud ? :
448 console_has((index == 0) ? "com1" : "com2")
449 ? BAUD_AUTO : 0);
450 uart->clock_hz = UART_CLOCK_HZ;
451 uart->data_bits = defaults->data_bits;
452 uart->parity = parse_parity_char(defaults->parity);
453 uart->stop_bits = defaults->stop_bits;
454 uart->irq = defaults->irq;
455 uart->io_base = defaults->io_base;
457 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
458 }
460 /*
461 * Local variables:
462 * mode: C
463 * c-set-style: "BSD"
464 * c-basic-offset: 4
465 * tab-width: 4
466 * indent-tabs-mode: nil
467 * End:
468 */