debuggers.hg

view xen/include/asm-x86/amd.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents aa3242c34dda
children
line source
1 /*
2 * amd.h - AMD processor specific definitions
3 */
5 #ifndef __AMD_H__
6 #define __AMD_H__
8 #include <asm/cpufeature.h>
10 /* CPUID masked for use by AMD-V Extended Migration */
12 #define X86_FEATURE_BITPOS(_feature_) ((_feature_) % 32)
13 #define __bit(_x_) (1U << X86_FEATURE_BITPOS(_x_))
15 /* Family 0Fh, Revision C */
16 #define AMD_FEATURES_K8_REV_C_ECX 0
17 #define AMD_FEATURES_K8_REV_C_EDX ( \
18 __bit(X86_FEATURE_FPU) | __bit(X86_FEATURE_VME) | \
19 __bit(X86_FEATURE_DE) | __bit(X86_FEATURE_PSE) | \
20 __bit(X86_FEATURE_TSC) | __bit(X86_FEATURE_MSR) | \
21 __bit(X86_FEATURE_PAE) | __bit(X86_FEATURE_MCE) | \
22 __bit(X86_FEATURE_CX8) | __bit(X86_FEATURE_APIC) | \
23 __bit(X86_FEATURE_SEP) | __bit(X86_FEATURE_MTRR) | \
24 __bit(X86_FEATURE_PGE) | __bit(X86_FEATURE_MCA) | \
25 __bit(X86_FEATURE_CMOV) | __bit(X86_FEATURE_PAT) | \
26 __bit(X86_FEATURE_PSE36) | __bit(X86_FEATURE_CLFLSH)| \
27 __bit(X86_FEATURE_MMX) | __bit(X86_FEATURE_FXSR) | \
28 __bit(X86_FEATURE_XMM) | __bit(X86_FEATURE_XMM2))
29 #define AMD_EXTFEATURES_K8_REV_C_ECX 0
30 #define AMD_EXTFEATURES_K8_REV_C_EDX ( \
31 __bit(X86_FEATURE_FPU) | __bit(X86_FEATURE_VME) | \
32 __bit(X86_FEATURE_DE) | __bit(X86_FEATURE_PSE) | \
33 __bit(X86_FEATURE_TSC) | __bit(X86_FEATURE_MSR) | \
34 __bit(X86_FEATURE_PAE) | __bit(X86_FEATURE_MCE) | \
35 __bit(X86_FEATURE_CX8) | __bit(X86_FEATURE_APIC) | \
36 __bit(X86_FEATURE_SYSCALL) | __bit(X86_FEATURE_MTRR) | \
37 __bit(X86_FEATURE_PGE) | __bit(X86_FEATURE_MCA) | \
38 __bit(X86_FEATURE_CMOV) | __bit(X86_FEATURE_PAT) | \
39 __bit(X86_FEATURE_PSE36) | __bit(X86_FEATURE_NX) | \
40 __bit(X86_FEATURE_MMXEXT) | __bit(X86_FEATURE_MMX) | \
41 __bit(X86_FEATURE_FXSR) | __bit(X86_FEATURE_LM) | \
42 __bit(X86_FEATURE_3DNOWEXT) | __bit(X86_FEATURE_3DNOW))
44 /* Family 0Fh, Revision D */
45 #define AMD_FEATURES_K8_REV_D_ECX AMD_FEATURES_K8_REV_C_ECX
46 #define AMD_FEATURES_K8_REV_D_EDX AMD_FEATURES_K8_REV_C_EDX
47 #define AMD_EXTFEATURES_K8_REV_D_ECX (AMD_EXTFEATURES_K8_REV_C_ECX |\
48 __bit(X86_FEATURE_LAHF_LM))
49 #define AMD_EXTFEATURES_K8_REV_D_EDX (AMD_EXTFEATURES_K8_REV_C_EDX |\
50 __bit(X86_FEATURE_FFXSR))
52 /* Family 0Fh, Revision E */
53 #define AMD_FEATURES_K8_REV_E_ECX (AMD_FEATURES_K8_REV_D_ECX | \
54 __bit(X86_FEATURE_XMM3))
55 #define AMD_FEATURES_K8_REV_E_EDX (AMD_FEATURES_K8_REV_D_EDX | \
56 __bit(X86_FEATURE_HT))
57 #define AMD_EXTFEATURES_K8_REV_E_ECX (AMD_EXTFEATURES_K8_REV_D_ECX |\
58 __bit(X86_FEATURE_CMP_LEGACY))
59 #define AMD_EXTFEATURES_K8_REV_E_EDX AMD_EXTFEATURES_K8_REV_D_EDX
61 /* Family 0Fh, Revision F */
62 #define AMD_FEATURES_K8_REV_F_ECX (AMD_FEATURES_K8_REV_E_ECX | \
63 __bit(X86_FEATURE_CX16))
64 #define AMD_FEATURES_K8_REV_F_EDX AMD_FEATURES_K8_REV_E_EDX
65 #define AMD_EXTFEATURES_K8_REV_F_ECX (AMD_EXTFEATURES_K8_REV_E_ECX |\
66 __bit(X86_FEATURE_SVM) | __bit(X86_FEATURE_EXTAPIC) | \
67 __bit(X86_FEATURE_CR8_LEGACY))
68 #define AMD_EXTFEATURES_K8_REV_F_EDX (AMD_EXTFEATURES_K8_REV_E_EDX |\
69 __bit(X86_FEATURE_RDTSCP))
71 /* Family 0Fh, Revision G */
72 #define AMD_FEATURES_K8_REV_G_ECX AMD_FEATURES_K8_REV_F_ECX
73 #define AMD_FEATURES_K8_REV_G_EDX AMD_FEATURES_K8_REV_F_EDX
74 #define AMD_EXTFEATURES_K8_REV_G_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\
75 __bit(X86_FEATURE_3DNOWPREFETCH))
76 #define AMD_EXTFEATURES_K8_REV_G_EDX AMD_EXTFEATURES_K8_REV_F_EDX
78 /* Family 10h, Revision B */
79 #define AMD_FEATURES_FAM10h_REV_B_ECX (AMD_FEATURES_K8_REV_F_ECX | \
80 __bit(X86_FEATURE_POPCNT) | __bit(X86_FEATURE_MWAIT))
81 #define AMD_FEATURES_FAM10h_REV_B_EDX AMD_FEATURES_K8_REV_F_EDX
82 #define AMD_EXTFEATURES_FAM10h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_F_ECX |\
83 __bit(X86_FEATURE_ABM) | __bit(X86_FEATURE_SSE4A) | \
84 __bit(X86_FEATURE_MISALIGNSSE) | __bit(X86_FEATURE_OSVW) | \
85 __bit(X86_FEATURE_IBS))
86 #define AMD_EXTFEATURES_FAM10h_REV_B_EDX (AMD_EXTFEATURES_K8_REV_F_EDX |\
87 __bit(X86_FEATURE_PAGE1GB))
89 /* Family 10h, Revision C */
90 #define AMD_FEATURES_FAM10h_REV_C_ECX AMD_FEATURES_FAM10h_REV_B_ECX
91 #define AMD_FEATURES_FAM10h_REV_C_EDX AMD_FEATURES_FAM10h_REV_B_EDX
92 #define AMD_EXTFEATURES_FAM10h_REV_C_ECX (AMD_EXTFEATURES_FAM10h_REV_B_ECX |\
93 __bit(X86_FEATURE_SKINIT) | __bit(X86_FEATURE_WDT))
94 #define AMD_EXTFEATURES_FAM10h_REV_C_EDX AMD_EXTFEATURES_FAM10h_REV_B_EDX
96 /* Family 11h, Revision B */
97 #define AMD_FEATURES_FAM11h_REV_B_ECX AMD_FEATURES_K8_REV_G_ECX
98 #define AMD_FEATURES_FAM11h_REV_B_EDX AMD_FEATURES_K8_REV_G_EDX
99 #define AMD_EXTFEATURES_FAM11h_REV_B_ECX (AMD_EXTFEATURES_K8_REV_G_ECX |\
100 __bit(X86_FEATURE_SKINIT))
101 #define AMD_EXTFEATURES_FAM11h_REV_B_EDX AMD_EXTFEATURES_K8_REV_G_EDX
103 /* AMD errata checking
104 *
105 * Errata are defined using the AMD_LEGACY_ERRATUM() or AMD_OSVW_ERRATUM()
106 * macros. The latter is intended for newer errata that have an OSVW id
107 * assigned, which it takes as first argument. Both take a variable number
108 * of family-specific model-stepping ranges created by AMD_MODEL_RANGE().
109 *
110 * Example 1:
111 * #define AMD_ERRATUM_319 \
112 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), \
113 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), \
114 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0))
115 * Example 2:
116 * #define AMD_ERRATUM_400 \
117 * AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), \
118 * AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf))
119 *
120 */
122 #define AMD_LEGACY_ERRATUM(...) 0 /* legacy */, __VA_ARGS__, 0
123 #define AMD_OSVW_ERRATUM(osvw_id, ...) 1 /* osvw */, osvw_id, __VA_ARGS__, 0
124 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
125 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
126 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
127 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
128 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
130 #define AMD_ERRATUM_170 \
131 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x0f, 0x0, 0x0, 0x67, 0xf))
133 #define AMD_ERRATUM_383 \
134 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf), \
135 AMD_MODEL_RANGE(0x12, 0x0, 0x0, 0x1, 0x0))
137 struct cpuinfo_x86;
138 int cpu_has_amd_erratum(const struct cpuinfo_x86 *, int, ...);
140 #ifdef __x86_64__
141 void fam10h_check_enable_mmcfg(void);
142 void check_enable_amd_mmconf_dmi(void);
143 #endif
145 #endif /* __AMD_H__ */