debuggers.hg

view xen/include/asm-x86/apic.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents 2ff199e2842b
children
line source
1 #ifndef __ASM_APIC_H
2 #define __ASM_APIC_H
4 #include <xen/config.h>
5 #include <asm/apicdef.h>
6 #include <asm/fixmap.h>
7 #include <asm/msr.h>
9 #define Dprintk(x...)
11 /*
12 * Debugging macros
13 */
14 #define APIC_QUIET 0
15 #define APIC_VERBOSE 1
16 #define APIC_DEBUG 2
18 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
20 #define IO_APIC_REDIR_VECTOR_MASK 0x000FF
21 #define IO_APIC_REDIR_DEST_LOGICAL 0x00800
22 #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
24 extern int apic_verbosity;
25 extern bool_t x2apic_enabled;
26 extern bool_t directed_eoi_enabled;
28 void check_x2apic_preenabled(void);
29 void x2apic_bsp_setup(void);
30 void x2apic_ap_setup(void);
31 const struct genapic *apic_x2apic_probe(void);
33 /*
34 * Define the default level of output to be very little
35 * This can be turned up by using apic=verbose for more
36 * information and apic=debug for _lots_ of information.
37 * apic_verbosity is defined in apic.c
38 */
39 #define apic_printk(v, s, a...) do { \
40 if ((v) <= apic_verbosity) \
41 printk(s, ##a); \
42 } while (0)
45 #ifdef CONFIG_X86_LOCAL_APIC
47 /*
48 * Basic functions accessing APICs.
49 */
51 static __inline void apic_mem_write(unsigned long reg, u32 v)
52 {
53 *((volatile u32 *)(APIC_BASE+reg)) = v;
54 }
56 static __inline void apic_mem_write_atomic(unsigned long reg, u32 v)
57 {
58 (void)xchg((volatile u32 *)(APIC_BASE+reg), v);
59 }
61 static __inline u32 apic_mem_read(unsigned long reg)
62 {
63 return *((volatile u32 *)(APIC_BASE+reg));
64 }
66 /* NOTE: in x2APIC mode, we should use apic_icr_write()/apic_icr_read() to
67 * access the 64-bit ICR register.
68 */
70 static __inline void apic_wrmsr(unsigned long reg, uint64_t msr_content)
71 {
72 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
73 reg == APIC_LVR)
74 return;
76 wrmsrl(APIC_MSR_BASE + (reg >> 4), msr_content);
77 }
79 static __inline uint64_t apic_rdmsr(unsigned long reg)
80 {
81 uint64_t msr_content;
83 if (reg == APIC_DFR)
84 return -1u;
86 rdmsrl(APIC_MSR_BASE + (reg >> 4), msr_content);
87 return msr_content;
88 }
90 static __inline void apic_write(unsigned long reg, u32 v)
91 {
93 if ( x2apic_enabled )
94 apic_wrmsr(reg, v);
95 else
96 apic_mem_write(reg, v);
97 }
99 static __inline void apic_write_atomic(unsigned long reg, u32 v)
100 {
101 if ( x2apic_enabled )
102 apic_wrmsr(reg, v);
103 else
104 apic_mem_write_atomic(reg, v);
105 }
107 static __inline u32 apic_read(unsigned long reg)
108 {
109 if ( x2apic_enabled )
110 return apic_rdmsr(reg);
111 else
112 return apic_mem_read(reg);
113 }
115 static __inline u64 apic_icr_read(void)
116 {
117 u32 lo, hi;
119 if ( x2apic_enabled )
120 return apic_rdmsr(APIC_ICR);
121 else
122 {
123 lo = apic_mem_read(APIC_ICR);
124 hi = apic_mem_read(APIC_ICR2);
125 }
127 return ((u64)lo) | (((u64)hi) << 32);
128 }
130 static __inline void apic_icr_write(u32 low, u32 dest)
131 {
132 if ( x2apic_enabled )
133 apic_wrmsr(APIC_ICR, low | ((uint64_t)dest << 32));
134 else
135 {
136 apic_mem_write(APIC_ICR2, dest << 24);
137 apic_mem_write(APIC_ICR, low);
138 }
139 }
141 static __inline u32 get_apic_id(void) /* Get the physical APIC id */
142 {
143 u32 id = apic_read(APIC_ID);
144 return x2apic_enabled ? id : GET_xAPIC_ID(id);
145 }
147 static __inline u32 get_logical_apic_id(void)
148 {
149 u32 logical_id = apic_read(APIC_LDR);
150 return x2apic_enabled ? logical_id : GET_xAPIC_LOGICAL_ID(logical_id);
151 }
153 void apic_wait_icr_idle(void);
155 int get_physical_broadcast(void);
157 #ifdef CONFIG_X86_GOOD_APIC
158 # define FORCE_READ_AROUND_WRITE 0
159 # define apic_read_around(x)
160 # define apic_write_around(x,y) apic_write((x),(y))
161 #else
162 # define FORCE_READ_AROUND_WRITE 1
163 # define apic_read_around(x) apic_read(x)
164 # define apic_write_around(x,y) apic_write_atomic((x),(y))
165 #endif
167 static inline void ack_APIC_irq(void)
168 {
169 /*
170 * ack_APIC_irq() actually gets compiled as a single instruction:
171 * - a single rmw on Pentium/82489DX
172 * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
173 * ... yummie.
174 */
176 /* Docs say use 0 for future compatibility */
177 apic_write_around(APIC_EOI, 0);
178 }
180 extern void (*wait_timer_tick)(void);
182 extern int get_maxlvt(void);
183 extern void clear_local_APIC(void);
184 extern void connect_bsp_APIC (void);
185 extern void disconnect_bsp_APIC (int virt_wire_setup);
186 extern void disable_local_APIC (void);
187 extern void lapic_shutdown (void);
188 extern int verify_local_APIC (void);
189 extern void cache_APIC_registers (void);
190 extern void sync_Arb_IDs (void);
191 extern void init_bsp_APIC (void);
192 extern void setup_local_APIC (void);
193 extern void init_apic_mappings (void);
194 extern void smp_local_timer_interrupt (struct cpu_user_regs *regs);
195 extern void setup_boot_APIC_clock (void);
196 extern void setup_secondary_APIC_clock (void);
197 extern void setup_apic_nmi_watchdog (void);
198 extern int reserve_lapic_nmi(void);
199 extern void release_lapic_nmi(void);
200 extern void self_nmi(void);
201 extern void disable_timer_nmi_watchdog(void);
202 extern void enable_timer_nmi_watchdog(void);
203 extern void nmi_watchdog_tick (struct cpu_user_regs *regs);
204 extern int APIC_init_uniprocessor (void);
205 extern void disable_APIC_timer(void);
206 extern void enable_APIC_timer(void);
207 extern int lapic_suspend(void);
208 extern int lapic_resume(void);
210 extern int check_nmi_watchdog (void);
211 extern void enable_NMI_through_LVT0 (void * dummy);
213 extern unsigned int nmi_watchdog;
214 #define NMI_NONE 0
215 #define NMI_IO_APIC 1
216 #define NMI_LOCAL_APIC 2
217 #define NMI_INVALID 3
219 #else /* !CONFIG_X86_LOCAL_APIC */
220 static inline void lapic_shutdown(void) { }
221 static inline int lapic_suspend(void) {return 0;}
222 static inline int lapic_resume(void) {return 0;}
224 #endif /* !CONFIG_X86_LOCAL_APIC */
226 #endif /* __ASM_APIC_H */