debuggers.hg

view xen/include/asm-x86/apicdef.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents 4e93a604dafe
children
line source
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_xAPIC_ID(x) (((x)>>24)&0xFFu)
16 #define SET_xAPIC_ID(x) (((x)<<24))
17 #define APIC_LVR 0x30
18 #define APIC_LVR_MASK 0xFF00FF
19 #define APIC_LVR_DIRECTED_EOI (1 << 24)
20 #define GET_APIC_VERSION(x) ((x)&0xFF)
21 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
22 #define APIC_INTEGRATED(x) ((x)&0xF0)
23 #define APIC_XAPIC(x) ((x) >= 0x14)
24 #define APIC_TASKPRI 0x80
25 #define APIC_TPRI_MASK 0xFF
26 #define APIC_ARBPRI 0x90
27 #define APIC_ARBPRI_MASK 0xFF
28 #define APIC_PROCPRI 0xA0
29 #define APIC_EOI 0xB0
30 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
31 #define APIC_RRR 0xC0
32 #define APIC_LDR 0xD0
33 #define APIC_LDR_MASK (0xFF<<24)
34 #define GET_xAPIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
35 #define SET_xAPIC_LOGICAL_ID(x) (((x)<<24))
36 #define APIC_ALL_CPUS 0xFF
37 #define APIC_DFR 0xE0
38 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
39 #define APIC_DFR_FLAT 0xFFFFFFFFul
40 #define APIC_SPIV 0xF0
41 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
42 #define APIC_SPIV_APIC_ENABLED (1<<8)
43 #define APIC_SPIV_DIRECTED_EOI (1<<12)
44 #define APIC_ISR 0x100
45 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
46 #define APIC_TMR 0x180
47 #define APIC_IRR 0x200
48 #define APIC_ESR 0x280
49 #define APIC_ESR_SEND_CS 0x00001
50 #define APIC_ESR_RECV_CS 0x00002
51 #define APIC_ESR_SEND_ACC 0x00004
52 #define APIC_ESR_RECV_ACC 0x00008
53 #define APIC_ESR_SENDILL 0x00020
54 #define APIC_ESR_RECVILL 0x00040
55 #define APIC_ESR_ILLREGA 0x00080
56 #define APIC_ICR 0x300
57 #define APIC_DEST_SELF 0x40000
58 #define APIC_DEST_ALLINC 0x80000
59 #define APIC_DEST_ALLBUT 0xC0000
60 #define APIC_ICR_RR_MASK 0x30000
61 #define APIC_ICR_RR_INVALID 0x00000
62 #define APIC_ICR_RR_INPROG 0x10000
63 #define APIC_ICR_RR_VALID 0x20000
64 #define APIC_INT_LEVELTRIG 0x08000
65 #define APIC_INT_ASSERT 0x04000
66 #define APIC_ICR_BUSY 0x01000
67 #define APIC_DEST_LOGICAL 0x00800
68 #define APIC_DEST_PHYSICAL 0x00000
69 #define APIC_DM_FIXED 0x00000
70 #define APIC_DM_LOWEST 0x00100
71 #define APIC_DM_SMI 0x00200
72 #define APIC_DM_REMRD 0x00300
73 #define APIC_DM_NMI 0x00400
74 #define APIC_DM_INIT 0x00500
75 #define APIC_DM_STARTUP 0x00600
76 #define APIC_DM_EXTINT 0x00700
77 #define APIC_VECTOR_MASK 0x000FF
78 #define APIC_ICR2 0x310
79 #define GET_xAPIC_DEST_FIELD(x) (((x)>>24)&0xFF)
80 #define SET_xAPIC_DEST_FIELD(x) ((x)<<24)
81 #define APIC_LVTT 0x320
82 #define APIC_LVTTHMR 0x330
83 #define APIC_LVTPC 0x340
84 #define APIC_LVT0 0x350
85 #define APIC_CMCI 0x2F0
87 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
88 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
89 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
90 #define APIC_TIMER_BASE_CLKIN 0x0
91 #define APIC_TIMER_BASE_TMBASE 0x1
92 #define APIC_TIMER_BASE_DIV 0x2
93 #define APIC_TIMER_MODE_MASK (0x3<<17)
94 #define APIC_TIMER_MODE_ONESHOT (0x0<<17)
95 #define APIC_TIMER_MODE_PERIODIC (0x1<<17)
96 #define APIC_TIMER_MODE_TSC_DEADLINE (0x2<<17)
97 #define APIC_LVT_MASKED (1<<16)
98 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
99 #define APIC_LVT_REMOTE_IRR (1<<14)
100 #define APIC_INPUT_POLARITY (1<<13)
101 #define APIC_SEND_PENDING (1<<12)
102 #define APIC_MODE_MASK 0x700
103 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
104 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
105 #define APIC_MODE_FIXED 0x0
106 #define APIC_MODE_NMI 0x4
107 #define APIC_MODE_EXTINT 0x7
108 #define APIC_LVT1 0x360
109 #define APIC_LVTERR 0x370
110 #define APIC_TMICT 0x380
111 #define APIC_TMCCT 0x390
112 #define APIC_TDCR 0x3E0
114 /* Only available in x2APIC mode */
115 #define APIC_SELF_IPI 0x3F0
117 #define APIC_TDR_DIV_TMBASE (1<<2)
118 #define APIC_TDR_DIV_1 0xB
119 #define APIC_TDR_DIV_2 0x0
120 #define APIC_TDR_DIV_4 0x1
121 #define APIC_TDR_DIV_8 0x2
122 #define APIC_TDR_DIV_16 0x3
123 #define APIC_TDR_DIV_32 0x8
124 #define APIC_TDR_DIV_64 0x9
125 #define APIC_TDR_DIV_128 0xA
127 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
129 /* It's only used in x2APIC mode of an x2APIC unit. */
130 #define APIC_MSR_BASE 0x800
132 #ifdef __i386__
133 #define MAX_IO_APICS 64
134 #else
135 #define MAX_IO_APICS 128
136 #endif
138 /*
139 * the local APIC register structure, memory mapped. Not terribly well
140 * tested, but we might eventually use this one in the future - the
141 * problem why we cannot use it right now is the P5 APIC, it has an
142 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
143 */
144 #define u32 unsigned int
146 #define lapic ((volatile struct local_apic *)APIC_BASE)
148 #ifndef __ASSEMBLY__
149 struct local_apic {
151 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
153 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
155 /*020*/ struct { /* APIC ID Register */
156 u32 __reserved_1 : 24,
157 phys_apic_id : 4,
158 __reserved_2 : 4;
159 u32 __reserved[3];
160 } id;
162 /*030*/ const
163 struct { /* APIC Version Register */
164 u32 version : 8,
165 __reserved_1 : 8,
166 max_lvt : 8,
167 __reserved_2 : 8;
168 u32 __reserved[3];
169 } version;
171 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
173 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
175 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
177 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
179 /*080*/ struct { /* Task Priority Register */
180 u32 priority : 8,
181 __reserved_1 : 24;
182 u32 __reserved_2[3];
183 } tpr;
185 /*090*/ const
186 struct { /* Arbitration Priority Register */
187 u32 priority : 8,
188 __reserved_1 : 24;
189 u32 __reserved_2[3];
190 } apr;
192 /*0A0*/ const
193 struct { /* Processor Priority Register */
194 u32 priority : 8,
195 __reserved_1 : 24;
196 u32 __reserved_2[3];
197 } ppr;
199 /*0B0*/ struct { /* End Of Interrupt Register */
200 u32 eoi;
201 u32 __reserved[3];
202 } eoi;
204 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
206 /*0D0*/ struct { /* Logical Destination Register */
207 u32 __reserved_1 : 24,
208 logical_dest : 8;
209 u32 __reserved_2[3];
210 } ldr;
212 /*0E0*/ struct { /* Destination Format Register */
213 u32 __reserved_1 : 28,
214 model : 4;
215 u32 __reserved_2[3];
216 } dfr;
218 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
219 u32 spurious_vector : 8,
220 apic_enabled : 1,
221 focus_cpu : 1,
222 __reserved_2 : 22;
223 u32 __reserved_3[3];
224 } svr;
226 /*100*/ struct { /* In Service Register */
227 /*170*/ u32 bitfield;
228 u32 __reserved[3];
229 } isr [8];
231 /*180*/ struct { /* Trigger Mode Register */
232 /*1F0*/ u32 bitfield;
233 u32 __reserved[3];
234 } tmr [8];
236 /*200*/ struct { /* Interrupt Request Register */
237 /*270*/ u32 bitfield;
238 u32 __reserved[3];
239 } irr [8];
241 /*280*/ union { /* Error Status Register */
242 struct {
243 u32 send_cs_error : 1,
244 receive_cs_error : 1,
245 send_accept_error : 1,
246 receive_accept_error : 1,
247 __reserved_1 : 1,
248 send_illegal_vector : 1,
249 receive_illegal_vector : 1,
250 illegal_register_address : 1,
251 __reserved_2 : 24;
252 u32 __reserved_3[3];
253 } error_bits;
254 struct {
255 u32 errors;
256 u32 __reserved_3[3];
257 } all_errors;
258 } esr;
260 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
262 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
264 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
266 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
268 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
270 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
272 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
274 /*300*/ struct { /* Interrupt Command Register 1 */
275 u32 vector : 8,
276 delivery_mode : 3,
277 destination_mode : 1,
278 delivery_status : 1,
279 __reserved_1 : 1,
280 level : 1,
281 trigger : 1,
282 __reserved_2 : 2,
283 shorthand : 2,
284 __reserved_3 : 12;
285 u32 __reserved_4[3];
286 } icr1;
288 /*310*/ struct { /* Interrupt Command Register 2 */
289 union {
290 u32 __reserved_1 : 24,
291 phys_dest : 4,
292 __reserved_2 : 4;
293 u32 __reserved_3 : 24,
294 logical_dest : 8;
295 } dest;
296 u32 __reserved_4[3];
297 } icr2;
299 /*320*/ struct { /* LVT - Timer */
300 u32 vector : 8,
301 __reserved_1 : 4,
302 delivery_status : 1,
303 __reserved_2 : 3,
304 mask : 1,
305 timer_mode : 1,
306 __reserved_3 : 14;
307 u32 __reserved_4[3];
308 } lvt_timer;
310 /*330*/ struct { /* LVT - Thermal Sensor */
311 u32 vector : 8,
312 delivery_mode : 3,
313 __reserved_1 : 1,
314 delivery_status : 1,
315 __reserved_2 : 3,
316 mask : 1,
317 __reserved_3 : 15;
318 u32 __reserved_4[3];
319 } lvt_thermal;
321 /*340*/ struct { /* LVT - Performance Counter */
322 u32 vector : 8,
323 delivery_mode : 3,
324 __reserved_1 : 1,
325 delivery_status : 1,
326 __reserved_2 : 3,
327 mask : 1,
328 __reserved_3 : 15;
329 u32 __reserved_4[3];
330 } lvt_pc;
332 /*350*/ struct { /* LVT - LINT0 */
333 u32 vector : 8,
334 delivery_mode : 3,
335 __reserved_1 : 1,
336 delivery_status : 1,
337 polarity : 1,
338 remote_irr : 1,
339 trigger : 1,
340 mask : 1,
341 __reserved_2 : 15;
342 u32 __reserved_3[3];
343 } lvt_lint0;
345 /*360*/ struct { /* LVT - LINT1 */
346 u32 vector : 8,
347 delivery_mode : 3,
348 __reserved_1 : 1,
349 delivery_status : 1,
350 polarity : 1,
351 remote_irr : 1,
352 trigger : 1,
353 mask : 1,
354 __reserved_2 : 15;
355 u32 __reserved_3[3];
356 } lvt_lint1;
358 /*370*/ struct { /* LVT - Error */
359 u32 vector : 8,
360 __reserved_1 : 4,
361 delivery_status : 1,
362 __reserved_2 : 3,
363 mask : 1,
364 __reserved_3 : 15;
365 u32 __reserved_4[3];
366 } lvt_error;
368 /*380*/ struct { /* Timer Initial Count Register */
369 u32 initial_count;
370 u32 __reserved_2[3];
371 } timer_icr;
373 /*390*/ const
374 struct { /* Timer Current Count Register */
375 u32 curr_count;
376 u32 __reserved_2[3];
377 } timer_ccr;
379 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
381 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
383 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
385 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
387 /*3E0*/ struct { /* Timer Divide Configuration Register */
388 u32 divisor : 4,
389 __reserved_1 : 28;
390 u32 __reserved_2[3];
391 } timer_dcr;
393 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
395 } __attribute__ ((packed));
396 #endif /* !__ASSEMBLY__ */
398 #undef u32
400 #endif