debuggers.hg

view xen/include/asm-x86/config.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents 2762b6d3149c
children
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #else
13 # define CONFIG_PAGING_LEVELS 3
14 #endif
16 #define CONFIG_X86 1
17 #define CONFIG_X86_HT 1
18 #define CONFIG_PAGING_ASSISTANCE 1
19 #define CONFIG_SMP 1
20 #define CONFIG_X86_LOCAL_APIC 1
21 #define CONFIG_X86_GOOD_APIC 1
22 #define CONFIG_X86_IO_APIC 1
23 #define CONFIG_X86_PM_TIMER 1
24 #define CONFIG_HPET_TIMER 1
25 #define CONFIG_X86_MCE_THERMAL 1
26 #define CONFIG_NUMA 1
27 #define CONFIG_DISCONTIGMEM 1
28 #define CONFIG_NUMA_EMU 1
29 #define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER)
31 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
32 #define CONFIG_X86_L1_CACHE_SHIFT 7
34 #define CONFIG_ACPI 1
35 #define CONFIG_ACPI_BOOT 1
36 #define CONFIG_ACPI_SLEEP 1
37 #define CONFIG_ACPI_NUMA 1
38 #define CONFIG_ACPI_SRAT 1
39 #define CONFIG_ACPI_CSTATE 1
41 #define CONFIG_VGA 1
43 #define CONFIG_HOTPLUG 1
44 #define CONFIG_HOTPLUG_CPU 1
46 #define HZ 100
48 #define OPT_CONSOLE_STR "vga"
50 #ifdef MAX_PHYS_CPUS
51 #define NR_CPUS MAX_PHYS_CPUS
52 #else
53 #define NR_CPUS 128
54 #endif
56 #ifdef __i386__
57 /* Maximum number of virtual CPUs in multi-processor guests. */
58 #define MAX_VIRT_CPUS XEN_LEGACY_MAX_VCPUS
59 #endif
61 /* Maximum we can support with current vLAPIC ID mapping. */
62 #define MAX_HVM_VCPUS 128
64 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
65 # define supervisor_mode_kernel (1)
66 #else
67 # define supervisor_mode_kernel (0)
68 #endif
70 /* Linkage for x86 */
71 #define __ALIGN .align 16,0x90
72 #define __ALIGN_STR ".align 16,0x90"
73 #ifdef __ASSEMBLY__
74 #define ALIGN __ALIGN
75 #define ALIGN_STR __ALIGN_STR
76 #define ENTRY(name) \
77 .globl name; \
78 ALIGN; \
79 name:
80 #endif
82 #define NR_hypercalls 64
84 #ifndef NDEBUG
85 #define MEMORY_GUARD
86 #endif
88 #ifdef __i386__
89 #define STACK_ORDER 2
90 #else
91 #define STACK_ORDER 3
92 #endif
93 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
95 /* Primary stack is restricted to 8kB by guard pages. */
96 #define PRIMARY_STACK_SIZE 8192
98 #define BOOT_TRAMPOLINE 0x7c000
99 #define bootsym_phys(sym) \
100 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
101 #define bootsym(sym) \
102 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
103 BOOT_TRAMPOLINE-__pa(trampoline_start)))
104 #ifndef __ASSEMBLY__
105 extern char trampoline_start[], trampoline_end[];
106 extern char trampoline_realmode_entry[];
107 extern unsigned int trampoline_xen_phys_start;
108 extern unsigned char trampoline_cpu_started;
109 extern char wakeup_start[];
110 extern unsigned int video_mode, video_flags;
111 #endif
113 #if defined(__x86_64__)
115 #define CONFIG_X86_64 1
116 #define CONFIG_COMPAT 1
118 #define asmlinkage
120 #define PML4_ENTRY_BITS 39
121 #ifndef __ASSEMBLY__
122 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
123 #define PML4_ADDR(_slot) \
124 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
125 (_slot ## UL << PML4_ENTRY_BITS))
126 #define GB(_gb) (_gb ## UL << 30)
127 #else
128 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
129 #define PML4_ADDR(_slot) \
130 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
131 #define GB(_gb) (_gb << 30)
132 #endif
134 /*
135 * Memory layout:
136 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
137 * Guest-defined use (see below for compatibility mode guests).
138 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
139 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
140 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
141 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
142 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
143 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
144 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
145 * ioremap for PCI mmconfig space
146 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
147 * Guest linear page table.
148 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
149 * Shadow linear page table.
150 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
151 * Per-domain mappings (e.g., GDT, LDT).
152 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261]
153 * Machine-to-phys translation table.
154 * 0xffff82c000000000 - 0xffff82c3ffffffff [16GB, 2^34 bytes, PML4:261]
155 * ioremap()/fixmap area.
156 * 0xffff82c400000000 - 0xffff82c43fffffff [1GB, 2^30 bytes, PML4:261]
157 * Compatibility machine-to-phys translation table.
158 * 0xffff82c440000000 - 0xffff82c47fffffff [1GB, 2^30 bytes, PML4:261]
159 * High read-only compatibility machine-to-phys translation table.
160 * 0xffff82c480000000 - 0xffff82c4bfffffff [1GB, 2^30 bytes, PML4:261]
161 * Xen text, static data, bss.
162 * 0xffff82c4c0000000 - 0xffff82f5ffffffff [197GB, PML4:261]
163 * Reserved for future use.
164 * 0xffff82f600000000 - 0xffff82ffffffffff [40GB, 2^38 bytes, PML4:261]
165 * Page-frame information array.
166 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271]
167 * 1:1 direct mapping of all physical memory.
168 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
169 * Guest-defined use.
170 *
171 * Compatibility guest area layout:
172 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
173 * Guest-defined use.
174 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
175 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
176 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
177 * Unused.
178 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
179 * Hypercall argument translation area.
180 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
181 * Reserved for future use.
182 */
185 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
186 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
187 #define ROOT_PAGETABLE_XEN_SLOTS \
188 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
190 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
191 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
192 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
193 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
194 #define RO_MPT_VIRT_START (PML4_ADDR(256))
195 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2)
196 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE)
197 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB)
198 * - full 16-bit segment support needs 44 bits
199 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits)
200 */
201 #define PCI_MCFG_VIRT_START (PML4_ADDR(257))
202 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES)
203 /* Slot 258: linear page table (guest table). */
204 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
205 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
206 /* Slot 259: linear page table (shadow table). */
207 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
208 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
209 /* Slot 260: per-domain mappings. */
210 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
211 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
212 #define PERDOMAIN_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER))
213 /* Slot 261: machine-to-phys conversion table (256GB). */
214 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
215 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE)
216 /* Slot 261: ioremap()/fixmap area (16GB). */
217 #define IOREMAP_VIRT_START RDWR_MPT_VIRT_END
218 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + GB(16))
219 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
220 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
221 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1))
222 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
223 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
224 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + GB(1))
225 /* Slot 261: xen text, static data and bss (1GB). */
226 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
227 #define XEN_VIRT_END (XEN_VIRT_START + GB(1))
228 /* Slot 261: superpage information array (20MB). */
229 #define SPAGETABLE_VIRT_END FRAMETABLE_VIRT_START
230 #define SPAGETABLE_SIZE ((DIRECTMAP_SIZE >> SUPERPAGE_SHIFT) * \
231 sizeof(struct spage_info))
232 #define SPAGETABLE_VIRT_START (SPAGETABLE_VIRT_END - SPAGETABLE_SIZE)
233 /* Slot 261: page-frame information array (40GB). */
234 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START
235 #define FRAMETABLE_SIZE ((DIRECTMAP_SIZE >> PAGE_SHIFT) * \
236 sizeof(struct page_info))
237 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
238 /* Slot 262-271: A direct 1:1 mapping of all of physical memory. */
239 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
240 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES*10)
241 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE)
243 #ifndef __ASSEMBLY__
245 /* This is not a fixed value, just a lower limit. */
246 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
247 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
248 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
249 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
250 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
251 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
253 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
254 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
255 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
256 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
257 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
259 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS
261 #endif
263 #define PGT_base_page_table PGT_l4_page_table
265 #define __HYPERVISOR_CS64 0xe008
266 #define __HYPERVISOR_CS32 0xe038
267 #define __HYPERVISOR_CS __HYPERVISOR_CS64
268 #define __HYPERVISOR_DS64 0x0000
269 #define __HYPERVISOR_DS32 0xe010
270 #define __HYPERVISOR_DS __HYPERVISOR_DS64
272 #define SYMBOLS_ORIGIN XEN_VIRT_START
274 /* For generic assembly code: use macros to define operation/operand sizes. */
275 #define __OS "q" /* Operation Suffix */
276 #define __OP "r" /* Operand Prefix */
278 #elif defined(__i386__)
280 #define CONFIG_X86_32 1
281 #define CONFIG_DOMAIN_PAGE 1
283 #define asmlinkage __attribute__((regparm(0)))
285 /*
286 * Memory layout (high to low): PAE-SIZE
287 * ------
288 * I/O remapping area ( 4MB)
289 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
290 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
291 * Shadow linear pagetable ( 8MB)
292 * Guest linear pagetable ( 8MB)
293 * Machine-to-physical translation table [writable] (16MB)
294 * Frame-info table (96MB)
295 * * Start of guest inaccessible area
296 * Machine-to-physical translation table [read-only] (16MB)
297 * * Start of guest unmodifiable area
298 */
300 #define IOREMAP_MBYTES 4
301 #define DIRECTMAP_MBYTES 12
302 #define MAPCACHE_MBYTES 4
303 #define PERDOMAIN_MBYTES 8
305 #define LINEARPT_MBYTES 8
306 #define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
307 #define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
309 #define IOREMAP_VIRT_END 0UL
310 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
311 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
312 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
313 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
314 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
315 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
316 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
317 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
318 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
319 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
320 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
321 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
322 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
323 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
324 #define FRAMETABLE_SIZE (FRAMETABLE_MBYTES<<20)
325 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
326 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
327 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
329 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
331 /* Maximum linear address accessible via guest memory segments. */
332 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
334 /* Hypervisor owns top 168MB of virtual address space. */
335 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
337 #define L2_PAGETABLE_FIRST_XEN_SLOT \
338 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
339 #define L2_PAGETABLE_LAST_XEN_SLOT \
340 (~0UL >> L2_PAGETABLE_SHIFT)
341 #define L2_PAGETABLE_XEN_SLOTS \
342 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
344 #define PGT_base_page_table PGT_l3_page_table
346 #define __HYPERVISOR_CS 0xe008
347 #define __HYPERVISOR_DS 0xe010
349 /* For generic assembly code: use macros to define operation/operand sizes. */
350 #define __OS "l" /* Operation Suffix */
351 #define __OP "e" /* Operand Prefix */
353 #endif /* __i386__ */
355 #ifndef __ASSEMBLY__
356 extern unsigned long xen_phys_start;
357 #if defined(__i386__)
358 extern unsigned long xenheap_phys_end;
359 #endif
360 #endif
362 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
363 #define GDT_LDT_VCPU_SHIFT 5
364 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
365 #ifdef MAX_VIRT_CPUS
366 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
367 #else
368 #define GDT_LDT_MBYTES PERDOMAIN_MBYTES
369 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT))
370 #endif
371 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
372 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
374 /* The address of a particular VCPU's GDT or LDT. */
375 #define GDT_VIRT_START(v) \
376 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
377 #define LDT_VIRT_START(v) \
378 (GDT_VIRT_START(v) + (64*1024))
380 #define PDPT_L1_ENTRIES \
381 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
382 #define PDPT_L2_ENTRIES \
383 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
385 #if defined(__x86_64__)
386 #define ELFSIZE 64
387 #else
388 #define ELFSIZE 32
389 #endif
391 #define ARCH_CRASH_SAVE_VMCOREINFO
393 #ifndef __ASSEMBLY__
394 extern void watchdog_disable(void);
395 extern void watchdog_enable(void);
396 #endif
398 #endif /* __X86_CONFIG_H__ */