debuggers.hg

view xen/include/asm-x86/cpufeature.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents aa3242c34dda
children 6067a17114bc
line source
1 /*
2 * cpufeature.h
3 *
4 * Defines x86 CPU feature bits
5 */
7 #ifndef __ASM_I386_CPUFEATURE_H
8 #define __ASM_I386_CPUFEATURE_H
10 #include <xen/bitops.h>
12 #define NCAPINTS 8 /* N 32-bit words worth of info */
14 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
15 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
16 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
17 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
18 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
19 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
20 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
21 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
22 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
23 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
24 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
25 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
26 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
27 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
28 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
29 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
30 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
31 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
32 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
33 #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
34 #define X86_FEATURE_DS (0*32+21) /* Debug Store */
35 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
36 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
37 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
38 /* of FPU context), and CR4.OSFXSR available */
39 #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
40 #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
41 #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
42 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
43 #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
44 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
45 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
47 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
48 /* Don't duplicate feature flags which are redundant with Intel! */
49 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
50 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */
51 #define X86_FEATURE_NX (1*32+20) /* Execute Disable */
52 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
53 #define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
54 #define X86_FEATURE_PAGE1GB (1*32+26) /* 1Gb large page support */
55 #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
56 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
57 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
58 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
60 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
61 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
62 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
63 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
65 /* Other features, Linux-defined mapping, word 3 */
66 /* This range is used for feature bits which conflict or are synthesized */
67 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
68 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
69 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
70 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
71 /* cpu types for specific tunings: */
72 #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
73 #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
74 #define X86_FEATURE_P3 (3*32+ 6) /* P3 */
75 #define X86_FEATURE_P4 (3*32+ 7) /* P4 */
76 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
77 #define X86_FEATURE_NONSTOP_TSC (3*32+ 9) /* TSC does not stop in C states */
78 #define X86_FEATURE_ARAT (3*32+ 10) /* Always running APIC timer */
79 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
80 #define X86_FEATURE_TSC_RELIABLE (3*32+12) /* TSC is known to be reliable */
81 #define X86_FEATURE_XTOPOLOGY (3*32+13) /* cpu topology enum extensions */
83 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
84 #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
85 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
86 #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
87 #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
88 #define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
89 #define X86_FEATURE_SMXE (4*32+ 6) /* Safer Mode Extensions */
90 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
91 #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
92 #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
93 #define X86_FEATURE_CID (4*32+10) /* Context ID */
94 #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
95 #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
96 #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
97 #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
98 #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
99 #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
100 #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
101 #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
102 #define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */
103 #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
104 #define X86_FEATURE_OSXSAVE (4*32+27) /* OSXSAVE */
105 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
106 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */
108 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
109 #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
110 #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
111 #define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
112 #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
113 #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
114 #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
115 #define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
116 #define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
117 #define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
118 #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
120 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
121 #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
122 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
123 #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
124 #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
125 #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
126 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
127 #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
128 #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
129 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
130 #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
131 #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
132 #define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
133 #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
134 #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
135 #define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
136 #define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
137 #define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
138 #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
139 #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
141 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
142 #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
144 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
145 #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
147 #ifdef __i386__
148 #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
149 #define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
150 #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
151 #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
152 #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
153 #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
154 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
155 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
156 #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
157 #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
158 #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
159 #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
160 #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
161 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
162 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
163 #define cpu_has_syscall boot_cpu_has(X86_FEATURE_SYSCALL)
164 #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
165 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
166 #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
167 #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
168 #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
169 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
170 #define cpu_has_page1gb 0
171 #define cpu_has_efer (boot_cpu_data.x86_capability[1] & 0x20100800)
172 #define cpu_has_fsgsbase 0
173 #else /* __x86_64__ */
174 #define cpu_has_vme 0
175 #define cpu_has_de 1
176 #define cpu_has_pse 1
177 #define cpu_has_tsc 1
178 #define cpu_has_pge 1
179 #define cpu_has_pat 1
180 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
181 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
182 #define cpu_has_mtrr 1
183 #define cpu_has_mmx 1
184 #define cpu_has_fxsr 1
185 #define cpu_has_xmm 1
186 #define cpu_has_xmm2 1
187 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
188 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
189 #define cpu_has_syscall 1
190 #define cpu_has_mp 1
191 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
192 #define cpu_has_k6_mtrr 0
193 #define cpu_has_cyrix_arr 0
194 #define cpu_has_centaur_mcr 0
195 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
196 #define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB)
197 #define cpu_has_efer 1
198 #define cpu_has_fsgsbase boot_cpu_has(X86_FEATURE_FSGSBASE)
199 #endif
201 #define cpu_has_ffxsr ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
202 && boot_cpu_has(X86_FEATURE_FFXSR))
204 #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
206 #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
208 #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
210 #define cpu_has_rdtscp boot_cpu_has(X86_FEATURE_RDTSCP)
212 #endif /* __ASM_I386_CPUFEATURE_H */
214 /*
215 * Local Variables:
216 * mode:c
217 * comment-column:42
218 * End:
219 */