debuggers.hg

view xen/include/asm-x86/msi.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents f12837d7a50e
children
line source
1 #ifndef __ASM_MSI_H
2 #define __ASM_MSI_H
4 #include <xen/cpumask.h>
5 /*
6 * Constants for Intel APIC based MSI messages.
7 */
9 /*
10 * Shifts for MSI data
11 */
13 #define MSI_DATA_VECTOR_SHIFT 0
14 #define MSI_DATA_VECTOR_MASK 0x000000ff
15 #define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & MSI_DATA_VECTOR_MASK)
17 #define MSI_DATA_DELIVERY_MODE_SHIFT 8
18 #define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
19 #define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
21 #define MSI_DATA_LEVEL_SHIFT 14
22 #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
23 #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
25 #define MSI_DATA_TRIGGER_SHIFT 15
26 #define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
27 #define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
29 /*
30 * Shift/mask fields for msi address
31 */
33 #define MSI_ADDR_BASE_HI 0
34 #define MSI_ADDR_BASE_LO 0xfee00000
35 #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO
37 #define MSI_ADDR_DESTMODE_SHIFT 2
38 #define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT)
39 #define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT)
41 #define MSI_ADDR_REDIRECTION_SHIFT 3
42 #define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
43 #define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
45 #define MSI_ADDR_DEST_ID_SHIFT 12
46 #define MSI_ADDR_DEST_ID_MASK 0x00ffff0
47 #define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI_ADDR_DEST_ID_MASK)
49 /* MAX fixed pages reserved for mapping MSIX tables. */
50 #if defined(__x86_64__)
51 #define FIX_MSIX_MAX_PAGES 512
52 #else
53 #define FIX_MSIX_MAX_PAGES 32
54 #endif
56 struct msi_info {
57 int bus;
58 int devfn;
59 int irq;
60 int entry_nr;
61 uint64_t table_base;
62 };
64 struct msi_msg {
65 u32 address_lo; /* low 32 bits of msi message address */
66 u32 address_hi; /* high 32 bits of msi message address */
67 u32 data; /* 16 bits of msi message data */
68 u32 dest32; /* used when Interrupt Remapping with EIM is enabled */
69 };
71 struct msi_desc;
72 /* Helper functions */
73 extern void mask_msi_irq(unsigned int irq);
74 extern void unmask_msi_irq(unsigned int irq);
75 extern void set_msi_affinity(unsigned int vector, cpumask_t mask);
76 extern int pci_enable_msi(struct msi_info *msi, struct msi_desc **desc);
77 extern void pci_disable_msi(struct msi_desc *desc);
78 extern void pci_cleanup_msi(struct pci_dev *pdev);
79 extern int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq);
80 extern void teardown_msi_irq(int irq);
81 extern int msi_free_vector(struct msi_desc *entry);
82 extern int pci_restore_msi_state(struct pci_dev *pdev);
84 extern unsigned int pci_msix_get_table_len(struct pci_dev *pdev);
86 struct msi_desc {
87 struct {
88 __u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
89 __u8 maskbit : 1; /* mask-pending bit supported ? */
90 __u8 masked : 1;
91 __u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
92 __u8 pos; /* Location of the msi capability */
93 __u16 entry_nr; /* specific enabled entry */
94 }msi_attrib;
96 struct list_head list;
98 void __iomem *mask_base; /* va for the entry in mask table */
99 struct pci_dev *dev;
100 int irq;
102 struct msi_msg msg; /* Last set MSI message */
104 int remap_index; /* index in interrupt remapping table */
105 };
107 int msi_maskable_irq(const struct msi_desc *);
108 int msi_free_irq(struct msi_desc *entry);
110 /*
111 * Assume the maximum number of hot plug slots supported by the system is about
112 * ten. The worstcase is that each of these slots is hot-added with a device,
113 * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
114 * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
115 * as below to ensure at least one message is assigned to each detected MSI/
116 * MSI-X device function.
117 */
118 #define NR_HP_RESERVED_VECTORS 20
120 extern const struct hw_interrupt_type pci_msi_type;
122 #define PCI_MSIX_ENTRY_SIZE 16
123 #define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
124 #define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
125 #define PCI_MSIX_ENTRY_DATA_OFFSET 8
126 #define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
128 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
129 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
130 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
131 #define msi_data_reg(base, is64bit) \
132 ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
133 #define msi_mask_bits_reg(base, is64bit) \
134 ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
135 #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
136 #define multi_msi_capable(control) \
137 (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
138 #define multi_msi_enable(control, num) \
139 control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
140 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
141 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
142 #define msi_enable(control, num) multi_msi_enable(control, num); \
143 control |= PCI_MSI_FLAGS_ENABLE
145 #define msix_control_reg(base) (base + PCI_MSIX_FLAGS)
146 #define msix_table_offset_reg(base) (base + PCI_MSIX_TABLE)
147 #define msix_pba_offset_reg(base) (base + PCI_MSIX_PBA)
148 #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
149 #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
150 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
151 #define multi_msix_capable msix_table_size
152 #define msix_unmask(address) (address & ~PCI_MSIX_VECTOR_BITMASK)
153 #define msix_mask(address) (address | PCI_MSIX_VECTOR_BITMASK)
155 /*
156 * MSI Defined Data Structures
157 */
158 #define MSI_ADDRESS_HEADER 0xfee
159 #define MSI_ADDRESS_HEADER_SHIFT 12
160 #define MSI_ADDRESS_HEADER_MASK 0xfff000
161 #define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
162 #define MSI_TARGET_CPU_MASK 0xff
163 #define MSI_TARGET_CPU_SHIFT 12
164 #define MSI_DELIVERY_MODE 0
165 #define MSI_LEVEL_MODE 1 /* Edge always assert */
166 #define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
167 #define MSI_PHYSICAL_MODE 0
168 #define MSI_LOGICAL_MODE 1
169 #define MSI_REDIRECTION_HINT_MODE 0
171 #define __LITTLE_ENDIAN_BITFIELD 1
173 struct msg_data {
174 #if defined(__LITTLE_ENDIAN_BITFIELD)
175 __u32 vector : 8;
176 __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
177 __u32 reserved_1 : 3;
178 __u32 level : 1; /* 0: deassert | 1: assert */
179 __u32 trigger : 1; /* 0: edge | 1: level */
180 __u32 reserved_2 : 16;
181 #elif defined(__BIG_ENDIAN_BITFIELD)
182 __u32 reserved_2 : 16;
183 __u32 trigger : 1; /* 0: edge | 1: level */
184 __u32 level : 1; /* 0: deassert | 1: assert */
185 __u32 reserved_1 : 3;
186 __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
187 __u32 vector : 8;
188 #else
189 #error "Bitfield endianness not defined! Check your byteorder.h"
190 #endif
191 } __attribute__ ((packed));
193 struct msg_address {
194 union {
195 struct {
196 #if defined(__LITTLE_ENDIAN_BITFIELD)
197 __u32 reserved_1 : 2;
198 __u32 dest_mode : 1; /*0:physic | 1:logic */
199 __u32 redirection_hint: 1; /*0: dedicated CPU
200 1: lowest priority */
201 __u32 reserved_2 : 4;
202 __u32 dest_id : 24; /* Destination ID */
203 #elif defined(__BIG_ENDIAN_BITFIELD)
204 __u32 dest_id : 24; /* Destination ID */
205 __u32 reserved_2 : 4;
206 __u32 redirection_hint: 1; /*0: dedicated CPU
207 1: lowest priority */
208 __u32 dest_mode : 1; /*0:physic | 1:logic */
209 __u32 reserved_1 : 2;
210 #else
211 #error "Bitfield endianness not defined! Check your byteorder.h"
212 #endif
213 }u;
214 __u32 value;
215 }lo_address;
216 __u32 hi_address;
217 } __attribute__ ((packed));
219 void msi_compose_msg(struct pci_dev *pdev, int irq,
220 struct msi_msg *msg);
221 #endif /* __ASM_MSI_H */