debuggers.hg

view xen/include/asm-x86/msr-index.h @ 22855:1d1eec7e1fb4

xl: Perform minimal validation of virtual disk file while parsing config file

This patch performs some very basic validation on the virtual disk
file passed through the config file. This validation ensures that we
don't go too far with the initialization like spawn qemu and more
while there could be some potentially fundamental issues.

[ Patch fixed up to work with PHYSTYPE_EMPTY 22808:6ec61438713a -iwj ]

Signed-off-by: Kamala Narasimhan <kamala.narasimhan@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
author Kamala Narasimhan <kamala.narasimhan@gmail.com>
date Tue Jan 25 18:09:49 2011 +0000 (2011-01-25)
parents 852d87e0480b
children
line source
1 #ifndef __ASM_MSR_INDEX_H
2 #define __ASM_MSR_INDEX_H
4 /* CPU model specific register (MSR) numbers */
6 /* x86-64 specific MSRs */
7 #define MSR_EFER 0xc0000080 /* extended feature register */
8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
17 /* EFER bits: */
18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
19 #define _EFER_LME 8 /* Long mode enable */
20 #define _EFER_LMA 10 /* Long mode active (read-only) */
21 #define _EFER_NX 11 /* No execute enable */
22 #define _EFER_SVME 12 /* AMD: SVM enable */
23 #define _EFER_LMSLE 13 /* AMD: Long-mode segment limit enable */
24 #define _EFER_FFXSE 14 /* AMD: Fast FXSAVE/FXRSTOR enable */
26 #define EFER_SCE (1<<_EFER_SCE)
27 #define EFER_LME (1<<_EFER_LME)
28 #define EFER_LMA (1<<_EFER_LMA)
29 #define EFER_NX (1<<_EFER_NX)
30 #define EFER_SVME (1<<_EFER_SVME)
31 #define EFER_LMSLE (1<<_EFER_LMSLE)
32 #define EFER_FFXSE (1<<_EFER_FFXSE)
34 /* Intel MSRs. Some also available on other CPUs */
35 #define MSR_IA32_PERFCTR0 0x000000c1
36 #define MSR_IA32_PERFCTR1 0x000000c2
37 #define MSR_FSB_FREQ 0x000000cd
39 #define MSR_MTRRcap 0x000000fe
40 #define MSR_IA32_BBL_CR_CTL 0x00000119
42 #define MSR_IA32_SYSENTER_CS 0x00000174
43 #define MSR_IA32_SYSENTER_ESP 0x00000175
44 #define MSR_IA32_SYSENTER_EIP 0x00000176
46 #define MSR_IA32_MCG_CAP 0x00000179
47 #define MSR_IA32_MCG_STATUS 0x0000017a
48 #define MSR_IA32_MCG_CTL 0x0000017b
50 #define MSR_IA32_PEBS_ENABLE 0x000003f1
51 #define MSR_IA32_DS_AREA 0x00000600
52 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
54 #define MSR_MTRRfix64K_00000 0x00000250
55 #define MSR_MTRRfix16K_80000 0x00000258
56 #define MSR_MTRRfix16K_A0000 0x00000259
57 #define MSR_MTRRfix4K_C0000 0x00000268
58 #define MSR_MTRRfix4K_C8000 0x00000269
59 #define MSR_MTRRfix4K_D0000 0x0000026a
60 #define MSR_MTRRfix4K_D8000 0x0000026b
61 #define MSR_MTRRfix4K_E0000 0x0000026c
62 #define MSR_MTRRfix4K_E8000 0x0000026d
63 #define MSR_MTRRfix4K_F0000 0x0000026e
64 #define MSR_MTRRfix4K_F8000 0x0000026f
65 #define MSR_MTRRdefType 0x000002ff
67 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
68 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
69 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
70 #define MSR_IA32_LASTINTFROMIP 0x000001dd
71 #define MSR_IA32_LASTINTTOIP 0x000001de
73 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
74 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
75 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
76 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
77 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
78 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
79 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
80 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
81 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
82 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
83 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020a
84 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020b
85 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020c
86 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020d
87 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020e
88 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020f
90 #define MSR_IA32_CR_PAT 0x00000277
91 #define MSR_IA32_CR_PAT_RESET 0x0007040600070406ULL
93 #define MSR_IA32_MC0_CTL 0x00000400
94 #define MSR_IA32_MC0_STATUS 0x00000401
95 #define MSR_IA32_MC0_ADDR 0x00000402
96 #define MSR_IA32_MC0_MISC 0x00000403
97 #define MSR_IA32_MC0_CTL2 0x00000280
98 #define CMCI_EN (1UL<<30)
99 #define CMCI_THRESHOLD_MASK 0x7FFF
101 #define MSR_IA32_MC1_CTL 0x00000404
102 #define MSR_IA32_MC1_CTL2 0x00000281
103 #define MSR_IA32_MC1_STATUS 0x00000405
104 #define MSR_IA32_MC1_ADDR 0x00000406
105 #define MSR_IA32_MC1_MISC 0x00000407
107 #define MSR_IA32_MC2_CTL 0x00000408
108 #define MSR_IA32_MC2_CTL2 0x00000282
109 #define MSR_IA32_MC2_STATUS 0x00000409
110 #define MSR_IA32_MC2_ADDR 0x0000040A
111 #define MSR_IA32_MC2_MISC 0x0000040B
113 #define MSR_IA32_MC3_CTL2 0x00000283
114 #define MSR_IA32_MC3_CTL 0x0000040C
115 #define MSR_IA32_MC3_STATUS 0x0000040D
116 #define MSR_IA32_MC3_ADDR 0x0000040E
117 #define MSR_IA32_MC3_MISC 0x0000040F
119 #define MSR_IA32_MC4_CTL2 0x00000284
120 #define MSR_IA32_MC4_CTL 0x00000410
121 #define MSR_IA32_MC4_STATUS 0x00000411
122 #define MSR_IA32_MC4_ADDR 0x00000412
123 #define MSR_IA32_MC4_MISC 0x00000413
125 #define MSR_IA32_MC5_CTL2 0x00000285
126 #define MSR_IA32_MC5_CTL 0x00000414
127 #define MSR_IA32_MC5_STATUS 0x00000415
128 #define MSR_IA32_MC5_ADDR 0x00000416
129 #define MSR_IA32_MC5_MISC 0x00000417
131 #define MSR_IA32_MC6_CTL2 0x00000286
132 #define MSR_IA32_MC6_CTL 0x00000418
133 #define MSR_IA32_MC6_STATUS 0x00000419
134 #define MSR_IA32_MC6_ADDR 0x0000041A
135 #define MSR_IA32_MC6_MISC 0x0000041B
137 #define MSR_IA32_MC7_CTL2 0x00000287
138 #define MSR_IA32_MC7_CTL 0x0000041C
139 #define MSR_IA32_MC7_STATUS 0x0000041D
140 #define MSR_IA32_MC7_ADDR 0x0000041E
141 #define MSR_IA32_MC7_MISC 0x0000041F
143 #define MSR_IA32_MC8_CTL2 0x00000288
144 #define MSR_IA32_MC8_CTL 0x00000420
145 #define MSR_IA32_MC8_STATUS 0x00000421
146 #define MSR_IA32_MC8_ADDR 0x00000422
147 #define MSR_IA32_MC8_MISC 0x00000423
149 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
150 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
151 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
152 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
154 #define MSR_P6_PERFCTR0 0x000000c1
155 #define MSR_P6_PERFCTR1 0x000000c2
156 #define MSR_P6_EVNTSEL0 0x00000186
157 #define MSR_P6_EVNTSEL1 0x00000187
159 /* MSRs for Intel cpuid feature mask */
160 #define MSR_INTEL_CPUID_FEATURE_MASK 0x00000478
161 #define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130
162 #define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
164 /* MSRs & bits used for VMX enabling */
165 #define MSR_IA32_VMX_BASIC 0x480
166 #define MSR_IA32_VMX_PINBASED_CTLS 0x481
167 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
168 #define MSR_IA32_VMX_EXIT_CTLS 0x483
169 #define MSR_IA32_VMX_ENTRY_CTLS 0x484
170 #define MSR_IA32_VMX_MISC 0x485
171 #define MSR_IA32_VMX_CR0_FIXED0 0x486
172 #define MSR_IA32_VMX_CR0_FIXED1 0x487
173 #define MSR_IA32_VMX_CR4_FIXED0 0x488
174 #define MSR_IA32_VMX_CR4_FIXED1 0x489
175 #define MSR_IA32_VMX_VMCS_ENUM 0x48a
176 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
177 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c
178 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d
179 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e
180 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f
181 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
182 #define IA32_FEATURE_CONTROL_MSR 0x3a
183 #define IA32_FEATURE_CONTROL_MSR_LOCK 0x0001
184 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX 0x0002
185 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
186 #define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL 0x7f00
187 #define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER 0x8000
189 /* K7/K8 MSRs. Not complete. See the architecture manual for a more
190 complete list. */
191 #define MSR_K7_EVNTSEL0 0xc0010000
192 #define MSR_K7_PERFCTR0 0xc0010004
193 #define MSR_K7_EVNTSEL1 0xc0010001
194 #define MSR_K7_PERFCTR1 0xc0010005
195 #define MSR_K7_EVNTSEL2 0xc0010002
196 #define MSR_K7_PERFCTR2 0xc0010006
197 #define MSR_K7_EVNTSEL3 0xc0010003
198 #define MSR_K7_PERFCTR3 0xc0010007
199 #define MSR_K8_TOP_MEM1 0xc001001a
200 #define MSR_K7_CLK_CTL 0xc001001b
201 #define MSR_K8_TOP_MEM2 0xc001001d
202 #define MSR_K8_SYSCFG 0xc0010010
204 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
205 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
206 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
208 #define MSR_K7_HWCR 0xc0010015
209 #define MSR_K8_HWCR 0xc0010015
210 #define MSR_K7_FID_VID_CTL 0xc0010041
211 #define MSR_K7_FID_VID_STATUS 0xc0010042
212 #define MSR_K8_PSTATE_LIMIT 0xc0010061
213 #define MSR_K8_PSTATE_CTRL 0xc0010062
214 #define MSR_K8_PSTATE_STATUS 0xc0010063
215 #define MSR_K8_PSTATE0 0xc0010064
216 #define MSR_K8_PSTATE1 0xc0010065
217 #define MSR_K8_PSTATE2 0xc0010066
218 #define MSR_K8_PSTATE3 0xc0010067
219 #define MSR_K8_PSTATE4 0xc0010068
220 #define MSR_K8_PSTATE5 0xc0010069
221 #define MSR_K8_PSTATE6 0xc001006A
222 #define MSR_K8_PSTATE7 0xc001006B
223 #define MSR_K8_ENABLE_C1E 0xc0010055
224 #define MSR_K8_VM_CR 0xc0010114
225 #define MSR_K8_VM_HSAVE_PA 0xc0010117
227 #define MSR_K8_FEATURE_MASK 0xc0011004
228 #define MSR_K8_EXT_FEATURE_MASK 0xc0011005
230 /* MSR_K8_VM_CR bits: */
231 #define _K8_VMCR_SVME_DISABLE 4
232 #define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE)
234 /* AMD64 MSRs */
235 #define MSR_AMD64_NB_CFG 0xc001001f
236 #define MSR_AMD64_DC_CFG 0xc0011022
237 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
239 /* AMD Family10h machine check MSRs */
240 #define MSR_F10_MC4_MISC1 0xc0000408
241 #define MSR_F10_MC4_MISC2 0xc0000409
242 #define MSR_F10_MC4_MISC3 0xc000040A
244 /* Other AMD Fam10h MSRs */
245 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
246 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
247 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
248 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
249 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
250 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
252 /* AMD Microcode MSRs */
253 #define MSR_AMD_PATCHLEVEL 0x0000008b
254 #define MSR_AMD_PATCHLOADER 0xc0010020
256 /* AMD OS Visible Workaround MSRs */
257 #define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
258 #define MSR_AMD_OSVW_STATUS 0xc0010141
260 /* K6 MSRs */
261 #define MSR_K6_EFER 0xc0000080
262 #define MSR_K6_STAR 0xc0000081
263 #define MSR_K6_WHCR 0xc0000082
264 #define MSR_K6_UWCCR 0xc0000085
265 #define MSR_K6_EPMR 0xc0000086
266 #define MSR_K6_PSOR 0xc0000087
267 #define MSR_K6_PFIR 0xc0000088
269 /* Centaur-Hauls/IDT defined MSRs. */
270 #define MSR_IDT_FCR1 0x00000107
271 #define MSR_IDT_FCR2 0x00000108
272 #define MSR_IDT_FCR3 0x00000109
273 #define MSR_IDT_FCR4 0x0000010a
275 #define MSR_IDT_MCR0 0x00000110
276 #define MSR_IDT_MCR1 0x00000111
277 #define MSR_IDT_MCR2 0x00000112
278 #define MSR_IDT_MCR3 0x00000113
279 #define MSR_IDT_MCR4 0x00000114
280 #define MSR_IDT_MCR5 0x00000115
281 #define MSR_IDT_MCR6 0x00000116
282 #define MSR_IDT_MCR7 0x00000117
283 #define MSR_IDT_MCR_CTRL 0x00000120
285 /* VIA Cyrix defined MSRs*/
286 #define MSR_VIA_FCR 0x00001107
287 #define MSR_VIA_LONGHAUL 0x0000110a
288 #define MSR_VIA_RNG 0x0000110b
289 #define MSR_VIA_BCR2 0x00001147
291 /* Transmeta defined MSRs */
292 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
293 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
294 #define MSR_TMTA_LRTI_READOUT 0x80868018
295 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
297 /* Intel defined MSRs. */
298 #define MSR_IA32_P5_MC_ADDR 0x00000000
299 #define MSR_IA32_P5_MC_TYPE 0x00000001
300 #define MSR_IA32_TSC 0x00000010
301 #define MSR_IA32_PLATFORM_ID 0x00000017
302 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
303 #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c
305 #define MSR_IA32_APICBASE 0x0000001b
306 #define MSR_IA32_APICBASE_BSP (1<<8)
307 #define MSR_IA32_APICBASE_EXTD (1<<10)
308 #define MSR_IA32_APICBASE_ENABLE (1<<11)
309 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
310 #define MSR_IA32_APICBASE_MSR 0x800
312 #define MSR_IA32_UCODE_WRITE 0x00000079
313 #define MSR_IA32_UCODE_REV 0x0000008b
315 #define MSR_IA32_PERF_STATUS 0x00000198
316 #define MSR_IA32_PERF_CTL 0x00000199
318 #define MSR_IA32_MPERF 0x000000e7
319 #define MSR_IA32_APERF 0x000000e8
321 #define MSR_IA32_THERM_CONTROL 0x0000019a
322 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
323 #define MSR_IA32_THERM_STATUS 0x0000019c
324 #define MSR_IA32_MISC_ENABLE 0x000001a0
325 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
326 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
327 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
328 #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
329 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22)
330 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
332 #define MSR_IA32_TSC_DEADLINE 0x000006E0
333 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
335 /* Intel Model 6 */
336 #define MSR_P6_EVNTSEL0 0x00000186
337 #define MSR_P6_EVNTSEL1 0x00000187
339 /* P4/Xeon+ specific */
340 #define MSR_IA32_MCG_EAX 0x00000180
341 #define MSR_IA32_MCG_EBX 0x00000181
342 #define MSR_IA32_MCG_ECX 0x00000182
343 #define MSR_IA32_MCG_EDX 0x00000183
344 #define MSR_IA32_MCG_ESI 0x00000184
345 #define MSR_IA32_MCG_EDI 0x00000185
346 #define MSR_IA32_MCG_EBP 0x00000186
347 #define MSR_IA32_MCG_ESP 0x00000187
348 #define MSR_IA32_MCG_EFLAGS 0x00000188
349 #define MSR_IA32_MCG_EIP 0x00000189
350 #define MSR_IA32_MCG_MISC 0x0000018a
351 #define MSR_IA32_MCG_R8 0x00000190
352 #define MSR_IA32_MCG_R9 0x00000191
353 #define MSR_IA32_MCG_R10 0x00000192
354 #define MSR_IA32_MCG_R11 0x00000193
355 #define MSR_IA32_MCG_R12 0x00000194
356 #define MSR_IA32_MCG_R13 0x00000195
357 #define MSR_IA32_MCG_R14 0x00000196
358 #define MSR_IA32_MCG_R15 0x00000197
360 /* Pentium IV performance counter MSRs */
361 #define MSR_P4_BPU_PERFCTR0 0x00000300
362 #define MSR_P4_BPU_PERFCTR1 0x00000301
363 #define MSR_P4_BPU_PERFCTR2 0x00000302
364 #define MSR_P4_BPU_PERFCTR3 0x00000303
365 #define MSR_P4_MS_PERFCTR0 0x00000304
366 #define MSR_P4_MS_PERFCTR1 0x00000305
367 #define MSR_P4_MS_PERFCTR2 0x00000306
368 #define MSR_P4_MS_PERFCTR3 0x00000307
369 #define MSR_P4_FLAME_PERFCTR0 0x00000308
370 #define MSR_P4_FLAME_PERFCTR1 0x00000309
371 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
372 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
373 #define MSR_P4_IQ_PERFCTR0 0x0000030c
374 #define MSR_P4_IQ_PERFCTR1 0x0000030d
375 #define MSR_P4_IQ_PERFCTR2 0x0000030e
376 #define MSR_P4_IQ_PERFCTR3 0x0000030f
377 #define MSR_P4_IQ_PERFCTR4 0x00000310
378 #define MSR_P4_IQ_PERFCTR5 0x00000311
379 #define MSR_P4_BPU_CCCR0 0x00000360
380 #define MSR_P4_BPU_CCCR1 0x00000361
381 #define MSR_P4_BPU_CCCR2 0x00000362
382 #define MSR_P4_BPU_CCCR3 0x00000363
383 #define MSR_P4_MS_CCCR0 0x00000364
384 #define MSR_P4_MS_CCCR1 0x00000365
385 #define MSR_P4_MS_CCCR2 0x00000366
386 #define MSR_P4_MS_CCCR3 0x00000367
387 #define MSR_P4_FLAME_CCCR0 0x00000368
388 #define MSR_P4_FLAME_CCCR1 0x00000369
389 #define MSR_P4_FLAME_CCCR2 0x0000036a
390 #define MSR_P4_FLAME_CCCR3 0x0000036b
391 #define MSR_P4_IQ_CCCR0 0x0000036c
392 #define MSR_P4_IQ_CCCR1 0x0000036d
393 #define MSR_P4_IQ_CCCR2 0x0000036e
394 #define MSR_P4_IQ_CCCR3 0x0000036f
395 #define MSR_P4_IQ_CCCR4 0x00000370
396 #define MSR_P4_IQ_CCCR5 0x00000371
397 #define MSR_P4_ALF_ESCR0 0x000003ca
398 #define MSR_P4_ALF_ESCR1 0x000003cb
399 #define MSR_P4_BPU_ESCR0 0x000003b2
400 #define MSR_P4_BPU_ESCR1 0x000003b3
401 #define MSR_P4_BSU_ESCR0 0x000003a0
402 #define MSR_P4_BSU_ESCR1 0x000003a1
403 #define MSR_P4_CRU_ESCR0 0x000003b8
404 #define MSR_P4_CRU_ESCR1 0x000003b9
405 #define MSR_P4_CRU_ESCR2 0x000003cc
406 #define MSR_P4_CRU_ESCR3 0x000003cd
407 #define MSR_P4_CRU_ESCR4 0x000003e0
408 #define MSR_P4_CRU_ESCR5 0x000003e1
409 #define MSR_P4_DAC_ESCR0 0x000003a8
410 #define MSR_P4_DAC_ESCR1 0x000003a9
411 #define MSR_P4_FIRM_ESCR0 0x000003a4
412 #define MSR_P4_FIRM_ESCR1 0x000003a5
413 #define MSR_P4_FLAME_ESCR0 0x000003a6
414 #define MSR_P4_FLAME_ESCR1 0x000003a7
415 #define MSR_P4_FSB_ESCR0 0x000003a2
416 #define MSR_P4_FSB_ESCR1 0x000003a3
417 #define MSR_P4_IQ_ESCR0 0x000003ba
418 #define MSR_P4_IQ_ESCR1 0x000003bb
419 #define MSR_P4_IS_ESCR0 0x000003b4
420 #define MSR_P4_IS_ESCR1 0x000003b5
421 #define MSR_P4_ITLB_ESCR0 0x000003b6
422 #define MSR_P4_ITLB_ESCR1 0x000003b7
423 #define MSR_P4_IX_ESCR0 0x000003c8
424 #define MSR_P4_IX_ESCR1 0x000003c9
425 #define MSR_P4_MOB_ESCR0 0x000003aa
426 #define MSR_P4_MOB_ESCR1 0x000003ab
427 #define MSR_P4_MS_ESCR0 0x000003c0
428 #define MSR_P4_MS_ESCR1 0x000003c1
429 #define MSR_P4_PMH_ESCR0 0x000003ac
430 #define MSR_P4_PMH_ESCR1 0x000003ad
431 #define MSR_P4_RAT_ESCR0 0x000003bc
432 #define MSR_P4_RAT_ESCR1 0x000003bd
433 #define MSR_P4_SAAT_ESCR0 0x000003ae
434 #define MSR_P4_SAAT_ESCR1 0x000003af
435 #define MSR_P4_SSU_ESCR0 0x000003be
436 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
438 #define MSR_P4_TBPU_ESCR0 0x000003c2
439 #define MSR_P4_TBPU_ESCR1 0x000003c3
440 #define MSR_P4_TC_ESCR0 0x000003c4
441 #define MSR_P4_TC_ESCR1 0x000003c5
442 #define MSR_P4_U2L_ESCR0 0x000003b0
443 #define MSR_P4_U2L_ESCR1 0x000003b1
445 /* Netburst (P4) last-branch recording */
446 #define MSR_P4_LER_FROM_LIP 0x000001d7
447 #define MSR_P4_LER_TO_LIP 0x000001d8
448 #define MSR_P4_LASTBRANCH_TOS 0x000001da
449 #define MSR_P4_LASTBRANCH_0 0x000001db
450 #define NUM_MSR_P4_LASTBRANCH 4
451 #define MSR_P4_LASTBRANCH_0_FROM_LIP 0x00000680
452 #define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0
453 #define NUM_MSR_P4_LASTBRANCH_FROM_TO 16
455 /* Pentium M (and Core) last-branch recording */
456 #define MSR_PM_LASTBRANCH_TOS 0x000001c9
457 #define MSR_PM_LASTBRANCH_0 0x00000040
458 #define NUM_MSR_PM_LASTBRANCH 8
460 /* Core 2 last-branch recording */
461 #define MSR_C2_LASTBRANCH_TOS 0x000001c9
462 #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
463 #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060
464 #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
466 /* Intel Core-based CPU performance counters */
467 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
468 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
469 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
470 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
471 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
472 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
473 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
475 /* Geode defined MSRs */
476 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
478 #endif /* __ASM_MSR_INDEX_H */