debuggers.hg

view xen/arch/x86/smpboot.c @ 19965:2dbabefe62dc

Move cpu_{sibling,core}_map into per-CPU space

These cpu maps get read from all CPUs, so apart from addressing the
square(nr_cpus) growth of these objects, they also get moved into the
previously introduced read-mostly sub-section of the per-CPU section,
in order to not need to waste a full cacheline in order to align (and
properly pad) them, which would be undue overhead on systems with low
NR_CPUS.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Jul 13 11:45:31 2009 +0100 (2009-07-13)
parents bcee82a0e9d6
children 323ae92f774b
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <xen/config.h>
37 #include <xen/init.h>
38 #include <xen/kernel.h>
39 #include <xen/mm.h>
40 #include <xen/domain.h>
41 #include <xen/sched.h>
42 #include <xen/irq.h>
43 #include <xen/delay.h>
44 #include <xen/softirq.h>
45 #include <xen/serial.h>
46 #include <xen/numa.h>
47 #include <asm/current.h>
48 #include <asm/mc146818rtc.h>
49 #include <asm/desc.h>
50 #include <asm/div64.h>
51 #include <asm/flushtlb.h>
52 #include <asm/msr.h>
53 #include <asm/mtrr.h>
54 #include <mach_apic.h>
55 #include <mach_wakecpu.h>
56 #include <smpboot_hooks.h>
57 #include <xen/stop_machine.h>
58 #include <acpi/cpufreq/processor_perf.h>
60 #define set_kernel_exec(x, y) (0)
61 #define setup_trampoline() (bootsym_phys(trampoline_realmode_entry))
63 /* Set if we find a B stepping CPU */
64 static int __devinitdata smp_b_stepping;
66 /* Package ID of each logical CPU */
67 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
69 /* Core ID of each logical CPU */
70 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
72 /* representing HT siblings of each logical CPU */
73 DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_sibling_map);
74 /* representing HT and core siblings of each logical CPU */
75 DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_core_map);
77 /* bitmap of online cpus */
78 cpumask_t cpu_online_map __read_mostly;
79 EXPORT_SYMBOL(cpu_online_map);
81 cpumask_t cpu_callin_map;
82 cpumask_t cpu_callout_map;
83 EXPORT_SYMBOL(cpu_callout_map);
84 cpumask_t cpu_possible_map;
85 EXPORT_SYMBOL(cpu_possible_map);
86 static cpumask_t smp_commenced_mask;
88 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
89 * is no way to resync one AP against BP. TBD: for prescott and above, we
90 * should use IA64's algorithm
91 */
92 static int __devinitdata tsc_sync_disabled;
94 /* Per CPU bogomips and other parameters */
95 struct cpuinfo_x86 cpu_data[NR_CPUS];
96 EXPORT_SYMBOL(cpu_data);
98 u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
99 { [0 ... NR_CPUS-1] = -1U };
100 EXPORT_SYMBOL(x86_cpu_to_apicid);
102 static void map_cpu_to_logical_apicid(void);
103 /* State of each CPU. */
104 DEFINE_PER_CPU(int, cpu_state) = { 0 };
106 static void *stack_base[NR_CPUS];
107 static DEFINE_SPINLOCK(cpu_add_remove_lock);
109 /*
110 * The bootstrap kernel entry code has set these up. Save them for
111 * a given CPU
112 */
114 static void __devinit smp_store_cpu_info(int id)
115 {
116 struct cpuinfo_x86 *c = cpu_data + id;
118 *c = boot_cpu_data;
119 if (id!=0)
120 identify_cpu(c);
121 /*
122 * Mask B, Pentium, but not Pentium MMX
123 */
124 if (c->x86_vendor == X86_VENDOR_INTEL &&
125 c->x86 == 5 &&
126 c->x86_mask >= 1 && c->x86_mask <= 4 &&
127 c->x86_model <= 3)
128 /*
129 * Remember we have B step Pentia with bugs
130 */
131 smp_b_stepping = 1;
133 /*
134 * Certain Athlons might work (for various values of 'work') in SMP
135 * but they are not certified as MP capable.
136 */
137 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
139 /* Athlon 660/661 is valid. */
140 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
141 goto valid_k7;
143 /* Duron 670 is valid */
144 if ((c->x86_model==7) && (c->x86_mask==0))
145 goto valid_k7;
147 /*
148 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
149 * It's worth noting that the A5 stepping (662) of some Athlon XP's
150 * have the MP bit set.
151 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
152 */
153 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
154 ((c->x86_model==7) && (c->x86_mask>=1)) ||
155 (c->x86_model> 7))
156 if (cpu_has_mp)
157 goto valid_k7;
159 /* If we get here, it's not a certified SMP capable AMD system. */
160 add_taint(TAINT_UNSAFE_SMP);
161 }
163 valid_k7:
164 ;
165 }
167 /*
168 * TSC synchronization.
169 *
170 * We first check whether all CPUs have their TSC's synchronized,
171 * then we print a warning if not, and always resync.
172 */
174 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
175 static atomic_t tsc_count_start = ATOMIC_INIT(0);
176 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
177 static unsigned long long tsc_values[NR_CPUS];
179 #define NR_LOOPS 5
181 static void __init synchronize_tsc_bp (void)
182 {
183 int i;
184 unsigned long long t0;
185 unsigned long long sum, avg;
186 long long delta;
187 unsigned int one_usec;
188 int buggy = 0;
190 printk("checking TSC synchronization across %u CPUs: ", num_booting_cpus());
192 /* convert from kcyc/sec to cyc/usec */
193 one_usec = cpu_khz / 1000;
195 atomic_set(&tsc_start_flag, 1);
196 wmb();
198 /*
199 * We loop a few times to get a primed instruction cache,
200 * then the last pass is more or less synchronized and
201 * the BP and APs set their cycle counters to zero all at
202 * once. This reduces the chance of having random offsets
203 * between the processors, and guarantees that the maximum
204 * delay between the cycle counters is never bigger than
205 * the latency of information-passing (cachelines) between
206 * two CPUs.
207 */
208 for (i = 0; i < NR_LOOPS; i++) {
209 /*
210 * all APs synchronize but they loop on '== num_cpus'
211 */
212 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
213 mb();
214 atomic_set(&tsc_count_stop, 0);
215 wmb();
216 /*
217 * this lets the APs save their current TSC:
218 */
219 atomic_inc(&tsc_count_start);
221 rdtscll(tsc_values[smp_processor_id()]);
222 /*
223 * We clear the TSC in the last loop:
224 */
225 if (i == NR_LOOPS-1)
226 write_tsc(0, 0);
228 /*
229 * Wait for all APs to leave the synchronization point:
230 */
231 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
232 mb();
233 atomic_set(&tsc_count_start, 0);
234 wmb();
235 atomic_inc(&tsc_count_stop);
236 }
238 sum = 0;
239 for (i = 0; i < NR_CPUS; i++) {
240 if (cpu_isset(i, cpu_callout_map)) {
241 t0 = tsc_values[i];
242 sum += t0;
243 }
244 }
245 avg = sum;
246 do_div(avg, num_booting_cpus());
248 sum = 0;
249 for (i = 0; i < NR_CPUS; i++) {
250 if (!cpu_isset(i, cpu_callout_map))
251 continue;
252 delta = tsc_values[i] - avg;
253 if (delta < 0)
254 delta = -delta;
255 /*
256 * We report bigger than 2 microseconds clock differences.
257 */
258 if (delta > 2*one_usec) {
259 long realdelta;
260 if (!buggy) {
261 buggy = 1;
262 printk("\n");
263 }
264 realdelta = delta;
265 do_div(realdelta, one_usec);
266 if (tsc_values[i] < avg)
267 realdelta = -realdelta;
269 printk("CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
270 }
272 sum += delta;
273 }
274 if (!buggy)
275 printk("passed.\n");
276 }
278 static void __init synchronize_tsc_ap (void)
279 {
280 int i;
282 /*
283 * Not every cpu is online at the time
284 * this gets called, so we first wait for the BP to
285 * finish SMP initialization:
286 */
287 while (!atomic_read(&tsc_start_flag)) mb();
289 for (i = 0; i < NR_LOOPS; i++) {
290 atomic_inc(&tsc_count_start);
291 while (atomic_read(&tsc_count_start) != num_booting_cpus())
292 mb();
294 rdtscll(tsc_values[smp_processor_id()]);
295 if (i == NR_LOOPS-1)
296 write_tsc(0, 0);
298 atomic_inc(&tsc_count_stop);
299 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
300 }
301 }
302 #undef NR_LOOPS
304 extern void calibrate_delay(void);
306 static atomic_t init_deasserted;
308 void __devinit smp_callin(void)
309 {
310 int cpuid, phys_id, i;
312 /*
313 * If waken up by an INIT in an 82489DX configuration
314 * we may get here before an INIT-deassert IPI reaches
315 * our local APIC. We have to wait for the IPI or we'll
316 * lock up on an APIC access.
317 */
318 wait_for_init_deassert(&init_deasserted);
320 if ( x2apic_enabled )
321 enable_x2apic();
323 /*
324 * (This works even if the APIC is not enabled.)
325 */
326 phys_id = get_apic_id();
327 cpuid = smp_processor_id();
328 if (cpu_isset(cpuid, cpu_callin_map)) {
329 printk("huh, phys CPU#%d, CPU#%d already present??\n",
330 phys_id, cpuid);
331 BUG();
332 }
333 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
335 /*
336 * STARTUP IPIs are fragile beasts as they might sometimes
337 * trigger some glue motherboard logic. Complete APIC bus
338 * silence for 1 second, this overestimates the time the
339 * boot CPU is spending to send the up to 2 STARTUP IPIs
340 * by a factor of two. This should be enough.
341 */
343 /*
344 * Waiting 2s total for startup
345 */
346 for (i = 0; i < 200; i++) {
347 /*
348 * Has the boot CPU finished it's STARTUP sequence?
349 */
350 if (cpu_isset(cpuid, cpu_callout_map))
351 break;
352 rep_nop();
353 mdelay(10);
354 }
356 if (!cpu_isset(cpuid, cpu_callout_map)) {
357 printk("BUG: CPU%d started up but did not get a callout!\n",
358 cpuid);
359 BUG();
360 }
362 /*
363 * the boot CPU has finished the init stage and is spinning
364 * on callin_map until we finish. We are free to set up this
365 * CPU, first the APIC. (this is probably redundant on most
366 * boards)
367 */
369 Dprintk("CALLIN, before setup_local_APIC().\n");
370 smp_callin_clear_local_apic();
371 setup_local_APIC();
372 map_cpu_to_logical_apicid();
374 #if 0
375 /*
376 * Get our bogomips.
377 */
378 calibrate_delay();
379 Dprintk("Stack at about %p\n",&cpuid);
380 #endif
382 /*
383 * Save our processor parameters
384 */
385 smp_store_cpu_info(cpuid);
387 /*
388 * Allow the master to continue.
389 */
390 cpu_set(cpuid, cpu_callin_map);
392 /*
393 * Synchronize the TSC with the BP
394 */
395 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) {
396 synchronize_tsc_ap();
397 /* No sync for same reason as above */
398 calibrate_tsc_ap();
399 }
400 }
402 static int cpucount, booting_cpu;
404 /* representing cpus for which sibling maps can be computed */
405 static cpumask_t cpu_sibling_setup_map;
407 static inline void
408 set_cpu_sibling_map(int cpu)
409 {
410 int i;
411 struct cpuinfo_x86 *c = cpu_data;
413 cpu_set(cpu, cpu_sibling_setup_map);
415 if (c[cpu].x86_num_siblings > 1) {
416 for_each_cpu_mask(i, cpu_sibling_setup_map) {
417 if (phys_proc_id[cpu] == phys_proc_id[i] &&
418 cpu_core_id[cpu] == cpu_core_id[i]) {
419 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
420 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
421 cpu_set(i, per_cpu(cpu_core_map, cpu));
422 cpu_set(cpu, per_cpu(cpu_core_map, i));
423 }
424 }
425 } else {
426 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
427 }
429 if (c[cpu].x86_max_cores == 1) {
430 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
431 c[cpu].booted_cores = 1;
432 return;
433 }
435 for_each_cpu_mask(i, cpu_sibling_setup_map) {
436 if (phys_proc_id[cpu] == phys_proc_id[i]) {
437 cpu_set(i, per_cpu(cpu_core_map, cpu));
438 cpu_set(cpu, per_cpu(cpu_core_map, i));
439 /*
440 * Does this new cpu bringup a new core?
441 */
442 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
443 /*
444 * for each core in package, increment
445 * the booted_cores for this new cpu
446 */
447 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
448 c[cpu].booted_cores++;
449 /*
450 * increment the core count for all
451 * the other cpus in this package
452 */
453 if (i != cpu)
454 c[i].booted_cores++;
455 } else if (i != cpu && !c[cpu].booted_cores)
456 c[cpu].booted_cores = c[i].booted_cores;
457 }
458 }
459 }
461 static void construct_percpu_idt(unsigned int cpu)
462 {
463 unsigned char idt_load[10];
465 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
466 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
467 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
468 }
470 /*
471 * Activate a secondary processor.
472 */
473 void __devinit start_secondary(void *unused)
474 {
475 /*
476 * Dont put anything before smp_callin(), SMP
477 * booting is too fragile that we want to limit the
478 * things done here to the most necessary things.
479 */
480 unsigned int cpu = booting_cpu;
482 set_processor_id(cpu);
483 set_current(idle_vcpu[cpu]);
484 this_cpu(curr_vcpu) = idle_vcpu[cpu];
485 if ( cpu_has_efer )
486 rdmsrl(MSR_EFER, this_cpu(efer));
487 asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
489 percpu_traps_init();
491 cpu_init();
492 /*preempt_disable();*/
493 smp_callin();
494 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
495 rep_nop();
497 /*
498 * At this point, boot CPU has fully initialised the IDT. It is
499 * now safe to make ourselves a private copy.
500 */
501 construct_percpu_idt(cpu);
503 setup_secondary_APIC_clock();
504 enable_APIC_timer();
505 /*
506 * low-memory mappings have been cleared, flush them from
507 * the local TLBs too.
508 */
509 flush_tlb_local();
511 /* This must be done before setting cpu_online_map */
512 set_cpu_sibling_map(raw_smp_processor_id());
513 wmb();
515 cpu_set(smp_processor_id(), cpu_online_map);
516 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
518 init_percpu_time();
520 /* We can take interrupts now: we're officially "up". */
521 local_irq_enable();
523 microcode_resume_cpu(cpu);
525 wmb();
526 startup_cpu_idle_loop();
527 }
529 extern struct {
530 void * esp;
531 unsigned short ss;
532 } stack_start;
534 u32 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
536 static void map_cpu_to_logical_apicid(void)
537 {
538 int cpu = smp_processor_id();
539 int apicid = logical_smp_processor_id();
541 cpu_2_logical_apicid[cpu] = apicid;
542 }
544 static void unmap_cpu_to_logical_apicid(int cpu)
545 {
546 cpu_2_logical_apicid[cpu] = BAD_APICID;
547 }
549 #if APIC_DEBUG
550 static inline void __inquire_remote_apic(int apicid)
551 {
552 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
553 char *names[] = { "ID", "VERSION", "SPIV" };
554 int timeout, status;
556 printk("Inquiring remote APIC #%d...\n", apicid);
558 for (i = 0; i < ARRAY_SIZE(regs); i++) {
559 printk("... APIC #%d %s: ", apicid, names[i]);
561 /*
562 * Wait for idle.
563 */
564 apic_wait_icr_idle();
566 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
568 timeout = 0;
569 do {
570 udelay(100);
571 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
572 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
574 switch (status) {
575 case APIC_ICR_RR_VALID:
576 status = apic_read(APIC_RRR);
577 printk("%08x\n", status);
578 break;
579 default:
580 printk("failed\n");
581 }
582 }
583 }
584 #endif
586 #ifdef WAKE_SECONDARY_VIA_NMI
588 static int logical_apicid_to_cpu(int logical_apicid)
589 {
590 int i;
592 for ( i = 0; i < sizeof(cpu_2_logical_apicid); i++ )
593 if ( cpu_2_logical_apicid[i] == logical_apicid )
594 break;
596 if ( i == sizeof(cpu_2_logical_apicid) );
597 i = -1; /* not found */
599 return i;
600 }
602 /*
603 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
604 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
605 * won't ... remember to clear down the APIC, etc later.
606 */
607 static int __devinit
608 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
609 {
610 unsigned long send_status = 0, accept_status = 0;
611 int timeout, maxlvt;
612 int dest_cpu;
613 u32 dest;
615 dest_cpu = logical_apicid_to_cpu(logical_apicid);
616 BUG_ON(dest_cpu == -1);
618 dest = cpu_physical_id(dest_cpu);
620 /* Boot on the stack */
621 apic_icr_write(APIC_DM_NMI | APIC_DEST_PHYSICAL, dest_cpu);
623 Dprintk("Waiting for send to finish...\n");
624 timeout = 0;
625 do {
626 Dprintk("+");
627 udelay(100);
628 if ( !x2apic_enabled )
629 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
630 else
631 send_status = 0; /* We go out of the loop directly. */
632 } while (send_status && (timeout++ < 1000));
634 /*
635 * Give the other CPU some time to accept the IPI.
636 */
637 udelay(200);
638 /*
639 * Due to the Pentium erratum 3AP.
640 */
641 maxlvt = get_maxlvt();
642 if (maxlvt > 3) {
643 apic_read_around(APIC_SPIV);
644 apic_write(APIC_ESR, 0);
645 }
646 accept_status = (apic_read(APIC_ESR) & 0xEF);
647 Dprintk("NMI sent.\n");
649 if (send_status)
650 printk("APIC never delivered???\n");
651 if (accept_status)
652 printk("APIC delivery error (%lx).\n", accept_status);
654 return (send_status | accept_status);
655 }
656 #endif /* WAKE_SECONDARY_VIA_NMI */
658 #ifdef WAKE_SECONDARY_VIA_INIT
659 static int __devinit
660 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
661 {
662 unsigned long send_status = 0, accept_status = 0;
663 int maxlvt, timeout, num_starts, j;
665 /*
666 * Be paranoid about clearing APIC errors.
667 */
668 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
669 apic_read_around(APIC_SPIV);
670 apic_write(APIC_ESR, 0);
671 apic_read(APIC_ESR);
672 }
674 Dprintk("Asserting INIT.\n");
676 /*
677 * Turn INIT on target chip via IPI
678 */
679 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
680 phys_apicid);
682 Dprintk("Waiting for send to finish...\n");
683 timeout = 0;
684 do {
685 Dprintk("+");
686 udelay(100);
687 if ( !x2apic_enabled )
688 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
689 else
690 send_status = 0; /* We go out of the loop dirctly. */
691 } while (send_status && (timeout++ < 1000));
693 mdelay(10);
695 Dprintk("Deasserting INIT.\n");
697 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
699 Dprintk("Waiting for send to finish...\n");
700 timeout = 0;
701 do {
702 Dprintk("+");
703 udelay(100);
704 if ( !x2apic_enabled )
705 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
706 else
707 send_status = 0; /* We go out of the loop dirctly. */
708 } while (send_status && (timeout++ < 1000));
710 atomic_set(&init_deasserted, 1);
712 /*
713 * Should we send STARTUP IPIs ?
714 *
715 * Determine this based on the APIC version.
716 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
717 */
718 if (APIC_INTEGRATED(apic_version[phys_apicid]))
719 num_starts = 2;
720 else
721 num_starts = 0;
723 /*
724 * Run STARTUP IPI loop.
725 */
726 Dprintk("#startup loops: %d.\n", num_starts);
728 maxlvt = get_maxlvt();
730 for (j = 1; j <= num_starts; j++) {
731 Dprintk("Sending STARTUP #%d.\n",j);
732 apic_read_around(APIC_SPIV);
733 apic_write(APIC_ESR, 0);
734 apic_read(APIC_ESR);
735 Dprintk("After apic_write.\n");
737 /*
738 * STARTUP IPI
739 * Boot on the stack
740 */
741 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
743 /*
744 * Give the other CPU some time to accept the IPI.
745 */
746 udelay(300);
748 Dprintk("Startup point 1.\n");
750 Dprintk("Waiting for send to finish...\n");
751 timeout = 0;
752 do {
753 Dprintk("+");
754 udelay(100);
755 if ( !x2apic_enabled )
756 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
757 else
758 send_status = 0; /* We go out of the loop dirctly. */
759 } while (send_status && (timeout++ < 1000));
761 /*
762 * Give the other CPU some time to accept the IPI.
763 */
764 udelay(200);
765 /*
766 * Due to the Pentium erratum 3AP.
767 */
768 if (maxlvt > 3) {
769 apic_read_around(APIC_SPIV);
770 apic_write(APIC_ESR, 0);
771 }
772 accept_status = (apic_read(APIC_ESR) & 0xEF);
773 if (send_status || accept_status)
774 break;
775 }
776 Dprintk("After Startup.\n");
778 if (send_status)
779 printk("APIC never delivered???\n");
780 if (accept_status)
781 printk("APIC delivery error (%lx).\n", accept_status);
783 return (send_status | accept_status);
784 }
785 #endif /* WAKE_SECONDARY_VIA_INIT */
787 extern cpumask_t cpu_initialized;
788 static inline int alloc_cpu_id(void)
789 {
790 cpumask_t tmp_map;
791 int cpu;
792 cpus_complement(tmp_map, cpu_present_map);
793 cpu = first_cpu(tmp_map);
794 if (cpu >= NR_CPUS)
795 return -ENODEV;
796 return cpu;
797 }
799 static void *prepare_idle_stack(unsigned int cpu)
800 {
801 if (!stack_base[cpu])
802 stack_base[cpu] = alloc_xenheap_pages(STACK_ORDER, 0);
804 return stack_base[cpu];
805 }
807 static int __devinit do_boot_cpu(int apicid, int cpu)
808 /*
809 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
810 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
811 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
812 */
813 {
814 unsigned long boot_error;
815 unsigned int order;
816 int timeout;
817 unsigned long start_eip;
818 unsigned short nmi_high = 0, nmi_low = 0;
819 struct vcpu *v;
820 struct desc_struct *gdt;
821 #ifdef __x86_64__
822 struct page_info *page;
823 #endif
825 /*
826 * Save current MTRR state in case it was changed since early boot
827 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
828 */
829 mtrr_save_state();
831 ++cpucount;
833 booting_cpu = cpu;
835 v = alloc_idle_vcpu(cpu);
836 BUG_ON(v == NULL);
838 /* start_eip had better be page-aligned! */
839 start_eip = setup_trampoline();
841 /* So we see what's up */
842 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
844 stack_start.esp = prepare_idle_stack(cpu);
846 /* Debug build: detect stack overflow by setting up a guard page. */
847 memguard_guard_stack(stack_start.esp);
849 gdt = per_cpu(gdt_table, cpu);
850 if (gdt == boot_cpu_gdt_table) {
851 order = get_order_from_pages(NR_RESERVED_GDT_PAGES);
852 #ifdef __x86_64__
853 #ifdef CONFIG_COMPAT
854 page = alloc_domheap_pages(NULL, order,
855 MEMF_node(cpu_to_node(cpu)));
856 per_cpu(compat_gdt_table, cpu) = gdt = page_to_virt(page);
857 memcpy(gdt, boot_cpu_compat_gdt_table,
858 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
859 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
860 #endif
861 page = alloc_domheap_pages(NULL, order,
862 MEMF_node(cpu_to_node(cpu)));
863 per_cpu(gdt_table, cpu) = gdt = page_to_virt(page);
864 #else
865 per_cpu(gdt_table, cpu) = gdt = alloc_xenheap_pages(order, 0);
866 #endif
867 memcpy(gdt, boot_cpu_gdt_table,
868 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
869 BUILD_BUG_ON(NR_CPUS > 0x10000);
870 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
871 }
873 #ifdef __i386__
874 if (!per_cpu(doublefault_tss, cpu)) {
875 per_cpu(doublefault_tss, cpu) = alloc_xenheap_page();
876 memset(per_cpu(doublefault_tss, cpu), 0, PAGE_SIZE);
877 }
878 #else
879 if (!per_cpu(compat_arg_xlat, cpu))
880 setup_compat_arg_xlat(cpu, apicid_to_node[apicid]);
881 #endif
883 if (!idt_tables[cpu]) {
884 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
885 memcpy(idt_tables[cpu], idt_table,
886 IDT_ENTRIES*sizeof(idt_entry_t));
887 }
889 /*
890 * This grunge runs the startup process for
891 * the targeted processor.
892 */
894 atomic_set(&init_deasserted, 0);
896 Dprintk("Setting warm reset code and vector.\n");
898 store_NMI_vector(&nmi_high, &nmi_low);
900 smpboot_setup_warm_reset_vector(start_eip);
902 /*
903 * Starting actual IPI sequence...
904 */
905 boot_error = wakeup_secondary_cpu(apicid, start_eip);
907 if (!boot_error) {
908 /*
909 * allow APs to start initializing.
910 */
911 Dprintk("Before Callout %d.\n", cpu);
912 cpu_set(cpu, cpu_callout_map);
913 Dprintk("After Callout %d.\n", cpu);
915 /*
916 * Wait 5s total for a response
917 */
918 for (timeout = 0; timeout < 50000; timeout++) {
919 if (cpu_isset(cpu, cpu_callin_map))
920 break; /* It has booted */
921 udelay(100);
922 }
924 if (cpu_isset(cpu, cpu_callin_map)) {
925 /* number CPUs logically, starting from 1 (BSP is 0) */
926 Dprintk("OK.\n");
927 printk("CPU%d: ", cpu);
928 print_cpu_info(&cpu_data[cpu]);
929 Dprintk("CPU has booted.\n");
930 } else {
931 boot_error = 1;
932 mb();
933 if (bootsym(trampoline_cpu_started) == 0xA5)
934 /* trampoline started but...? */
935 printk("Stuck ??\n");
936 else
937 /* trampoline code not run */
938 printk("Not responding.\n");
939 inquire_remote_apic(apicid);
940 }
941 }
943 if (boot_error) {
944 /* Try to put things back the way they were before ... */
945 unmap_cpu_to_logical_apicid(cpu);
946 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
947 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
948 cpucount--;
949 } else {
950 x86_cpu_to_apicid[cpu] = apicid;
951 cpu_set(cpu, cpu_present_map);
952 }
954 /* mark "stuck" area as not stuck */
955 bootsym(trampoline_cpu_started) = 0;
956 mb();
958 return boot_error;
959 }
961 #ifdef CONFIG_HOTPLUG_CPU
962 static void idle_task_exit(void)
963 {
964 /* Give up lazy state borrowed by this idle vcpu */
965 __sync_lazy_execstate();
966 }
968 void cpu_exit_clear(void)
969 {
970 int cpu = raw_smp_processor_id();
972 idle_task_exit();
974 cpucount --;
975 cpu_uninit();
977 cpu_clear(cpu, cpu_callout_map);
978 cpu_clear(cpu, cpu_callin_map);
980 cpu_clear(cpu, smp_commenced_mask);
981 unmap_cpu_to_logical_apicid(cpu);
982 }
984 static int __cpuinit __smp_prepare_cpu(int cpu)
985 {
986 int apicid, ret;
988 apicid = x86_cpu_to_apicid[cpu];
989 if (apicid == BAD_APICID) {
990 ret = -ENODEV;
991 goto exit;
992 }
994 tsc_sync_disabled = 1;
996 do_boot_cpu(apicid, cpu);
998 tsc_sync_disabled = 0;
1000 ret = 0;
1001 exit:
1002 return ret;
1004 #endif
1006 /*
1007 * Cycle through the processors sending APIC IPIs to boot each.
1008 */
1010 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1011 void *xquad_portio;
1012 #ifdef CONFIG_X86_NUMAQ
1013 EXPORT_SYMBOL(xquad_portio);
1014 #endif
1016 static void __init smp_boot_cpus(unsigned int max_cpus)
1018 int apicid, cpu, bit, kicked;
1019 #ifdef BOGOMIPS
1020 unsigned long bogosum = 0;
1021 #endif
1023 /*
1024 * Setup boot CPU information
1025 */
1026 smp_store_cpu_info(0); /* Final full version of the data */
1027 printk("CPU%d: ", 0);
1028 print_cpu_info(&cpu_data[0]);
1030 boot_cpu_physical_apicid = get_apic_id();
1031 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1033 stack_base[0] = stack_start.esp;
1035 /*current_thread_info()->cpu = 0;*/
1036 /*smp_tune_scheduling();*/
1038 set_cpu_sibling_map(0);
1040 /*
1041 * If we couldn't find an SMP configuration at boot time,
1042 * get out of here now!
1043 */
1044 if (!smp_found_config && !acpi_lapic) {
1045 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1046 init_uniprocessor:
1047 phys_cpu_present_map = physid_mask_of_physid(0);
1048 if (APIC_init_uniprocessor())
1049 printk(KERN_NOTICE "Local APIC not detected."
1050 " Using dummy APIC emulation.\n");
1051 map_cpu_to_logical_apicid();
1052 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1053 cpu_set(0, per_cpu(cpu_core_map, 0));
1054 return;
1057 /*
1058 * Should not be necessary because the MP table should list the boot
1059 * CPU too, but we do it for the sake of robustness anyway.
1060 * Makes no sense to do this check in clustered apic mode, so skip it
1061 */
1062 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1063 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1064 boot_cpu_physical_apicid);
1065 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1068 /*
1069 * If we couldn't find a local APIC, then get out of here now!
1070 */
1071 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1072 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1073 boot_cpu_physical_apicid);
1074 goto init_uniprocessor;
1077 verify_local_APIC();
1079 /*
1080 * If SMP should be disabled, then really disable it!
1081 */
1082 if (!max_cpus)
1083 goto init_uniprocessor;
1085 connect_bsp_APIC();
1086 setup_local_APIC();
1087 map_cpu_to_logical_apicid();
1090 setup_portio_remap();
1092 /*
1093 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1095 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1096 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1097 * clustered apic ID.
1098 */
1099 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1101 kicked = 1;
1102 for (bit = 0; kicked < NR_CPUS && bit < NR_CPUS; bit++) {
1103 apicid = cpu_present_to_apicid(bit);
1104 /*
1105 * Don't even attempt to start the boot CPU!
1106 */
1107 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1108 continue;
1110 if (!check_apicid_present(apicid))
1111 continue;
1112 if (max_cpus <= cpucount+1)
1113 continue;
1115 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1116 printk("CPU #%d not responding - cannot use it.\n",
1117 apicid);
1118 else
1119 ++kicked;
1122 /*
1123 * Cleanup possible dangling ends...
1124 */
1125 smpboot_restore_warm_reset_vector();
1127 #ifdef BOGOMIPS
1128 /*
1129 * Allow the user to impress friends.
1130 */
1131 Dprintk("Before bogomips.\n");
1132 for (cpu = 0; cpu < NR_CPUS; cpu++)
1133 if (cpu_isset(cpu, cpu_callout_map))
1134 bogosum += cpu_data[cpu].loops_per_jiffy;
1135 printk(KERN_INFO
1136 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1137 cpucount+1,
1138 bogosum/(500000/HZ),
1139 (bogosum/(5000/HZ))%100);
1140 #else
1141 printk("Total of %d processors activated.\n", cpucount+1);
1142 #endif
1144 Dprintk("Before bogocount - setting activated=1.\n");
1146 if (smp_b_stepping)
1147 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1149 /*
1150 * Don't taint if we are running SMP kernel on a single non-MP
1151 * approved Athlon
1152 */
1153 if (tainted & TAINT_UNSAFE_SMP) {
1154 if (cpucount)
1155 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1156 else
1157 tainted &= ~TAINT_UNSAFE_SMP;
1160 Dprintk("Boot done.\n");
1162 /*
1163 * construct cpu_sibling_map, so that we can tell sibling CPUs
1164 * efficiently.
1165 */
1166 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1167 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1168 cpus_clear(per_cpu(cpu_core_map, cpu));
1171 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1172 cpu_set(0, per_cpu(cpu_core_map, 0));
1174 if (nmi_watchdog == NMI_LOCAL_APIC)
1175 check_nmi_watchdog();
1177 smpboot_setup_io_apic();
1179 setup_boot_APIC_clock();
1181 /*
1182 * Synchronize the TSC with the AP
1183 */
1184 if (cpu_has_tsc && cpucount && cpu_khz)
1185 synchronize_tsc_bp();
1186 calibrate_tsc_bp();
1189 /* These are wrappers to interface to the new boot process. Someone
1190 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1191 void __init smp_prepare_cpus(unsigned int max_cpus)
1193 smp_commenced_mask = cpumask_of_cpu(0);
1194 cpu_callin_map = cpumask_of_cpu(0);
1195 mb();
1196 smp_boot_cpus(max_cpus);
1199 void __devinit smp_prepare_boot_cpu(void)
1201 cpu_set(smp_processor_id(), cpu_online_map);
1202 cpu_set(smp_processor_id(), cpu_callout_map);
1203 cpu_set(smp_processor_id(), cpu_present_map);
1204 cpu_set(smp_processor_id(), cpu_possible_map);
1205 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1208 #ifdef CONFIG_HOTPLUG_CPU
1209 static void
1210 remove_siblinginfo(int cpu)
1212 int sibling;
1213 struct cpuinfo_x86 *c = cpu_data;
1215 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1216 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1217 /*
1218 * last thread sibling in this cpu core going down
1219 */
1220 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1221 c[sibling].booted_cores--;
1224 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1225 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1226 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1227 cpus_clear(per_cpu(cpu_core_map, cpu));
1228 phys_proc_id[cpu] = BAD_APICID;
1229 cpu_core_id[cpu] = BAD_APICID;
1230 cpu_clear(cpu, cpu_sibling_setup_map);
1233 extern void fixup_irqs(cpumask_t map);
1234 int __cpu_disable(void)
1236 cpumask_t map = cpu_online_map;
1237 int cpu = smp_processor_id();
1239 /*
1240 * Perhaps use cpufreq to drop frequency, but that could go
1241 * into generic code.
1243 * We won't take down the boot processor on i386 due to some
1244 * interrupts only being able to be serviced by the BSP.
1245 * Especially so if we're not using an IOAPIC -zwane
1246 */
1247 if (cpu == 0)
1248 return -EBUSY;
1250 local_irq_disable();
1251 clear_local_APIC();
1252 /* Allow any queued timer interrupts to get serviced */
1253 local_irq_enable();
1254 mdelay(1);
1255 local_irq_disable();
1257 time_suspend();
1259 cpu_mcheck_disable();
1261 remove_siblinginfo(cpu);
1263 cpu_clear(cpu, map);
1264 fixup_irqs(map);
1265 /* It's now safe to remove this processor from the online map */
1266 cpu_clear(cpu, cpu_online_map);
1268 cpu_disable_scheduler();
1270 return 0;
1273 void __cpu_die(unsigned int cpu)
1275 /* We don't do anything here: idle task is faking death itself. */
1276 unsigned int i = 0;
1278 for (;;) {
1279 /* They ack this in play_dead by setting CPU_DEAD */
1280 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1281 printk ("CPU %u is now offline\n", cpu);
1282 return;
1284 mdelay(100);
1285 mb();
1286 process_pending_timers();
1287 if ((++i % 10) == 0)
1288 printk(KERN_ERR "CPU %u still not dead...\n", cpu);
1292 static int take_cpu_down(void *unused)
1294 return __cpu_disable();
1297 int cpu_down(unsigned int cpu)
1299 int err = 0;
1301 spin_lock(&cpu_add_remove_lock);
1302 if (num_online_cpus() == 1) {
1303 err = -EBUSY;
1304 goto out;
1307 /* Can not offline BSP */
1308 if (cpu == 0) {
1309 err = -EINVAL;
1310 goto out;
1313 if (!cpu_online(cpu)) {
1314 err = -EINVAL;
1315 goto out;
1318 printk("Prepare to bring CPU%d down...\n", cpu);
1320 cpufreq_del_cpu(cpu);
1322 err = stop_machine_run(take_cpu_down, NULL, cpu);
1323 if (err < 0)
1324 goto out;
1326 __cpu_die(cpu);
1328 BUG_ON(cpu_online(cpu));
1330 cpu_mcheck_distribute_cmci();
1332 out:
1333 spin_unlock(&cpu_add_remove_lock);
1334 return err;
1337 int cpu_up(unsigned int cpu)
1339 int err = 0;
1341 spin_lock(&cpu_add_remove_lock);
1342 if (cpu_online(cpu)) {
1343 printk("Bring up a online cpu. Bogus!\n");
1344 err = -EBUSY;
1345 goto out;
1348 err = __cpu_up(cpu);
1349 if (err < 0)
1350 goto out;
1352 out:
1353 spin_unlock(&cpu_add_remove_lock);
1354 return err;
1357 /* From kernel/power/main.c */
1358 /* This is protected by pm_sem semaphore */
1359 static cpumask_t frozen_cpus;
1361 void disable_nonboot_cpus(void)
1363 int cpu, error;
1365 error = 0;
1366 cpus_clear(frozen_cpus);
1367 printk("Freezing cpus ...\n");
1368 for_each_online_cpu(cpu) {
1369 if (cpu == 0)
1370 continue;
1371 error = cpu_down(cpu);
1372 if (!error) {
1373 cpu_set(cpu, frozen_cpus);
1374 printk("CPU%d is down\n", cpu);
1375 continue;
1377 printk("Error taking cpu %d down: %d\n", cpu, error);
1379 BUG_ON(raw_smp_processor_id() != 0);
1380 if (error)
1381 panic("cpus not sleeping");
1384 void enable_nonboot_cpus(void)
1386 int cpu, error;
1388 printk("Thawing cpus ...\n");
1389 for_each_cpu_mask(cpu, frozen_cpus) {
1390 error = cpu_up(cpu);
1391 if (!error) {
1392 printk("CPU%d is up\n", cpu);
1393 continue;
1395 printk("Error taking cpu %d up: %d\n", cpu, error);
1396 panic("Not enough cpus");
1398 cpus_clear(frozen_cpus);
1400 /*
1401 * Cleanup possible dangling ends after sleep...
1402 */
1403 smpboot_restore_warm_reset_vector();
1405 #else /* ... !CONFIG_HOTPLUG_CPU */
1406 int __cpu_disable(void)
1408 return -ENOSYS;
1411 void __cpu_die(unsigned int cpu)
1413 /* We said "no" in __cpu_disable */
1414 BUG();
1416 #endif /* CONFIG_HOTPLUG_CPU */
1418 int __devinit __cpu_up(unsigned int cpu)
1420 #ifdef CONFIG_HOTPLUG_CPU
1421 int ret=0;
1423 /*
1424 * We do warm boot only on cpus that had booted earlier
1425 * Otherwise cold boot is all handled from smp_boot_cpus().
1426 * cpu_callin_map is set during AP kickstart process. Its reset
1427 * when a cpu is taken offline from cpu_exit_clear().
1428 */
1429 if (!cpu_isset(cpu, cpu_callin_map)) {
1430 ret = __smp_prepare_cpu(cpu);
1431 smpboot_restore_warm_reset_vector();
1434 if (ret)
1435 return -EIO;
1436 #endif
1438 /* In case one didn't come up */
1439 if (!cpu_isset(cpu, cpu_callin_map)) {
1440 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1441 local_irq_enable();
1442 return -EIO;
1445 local_irq_enable();
1446 /*per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;*/
1447 /* Unleash the CPU! */
1448 cpu_set(cpu, smp_commenced_mask);
1449 while (!cpu_isset(cpu, cpu_online_map)) {
1450 mb();
1451 process_pending_timers();
1454 cpufreq_add_cpu(cpu);
1455 return 0;
1459 void __init smp_cpus_done(unsigned int max_cpus)
1461 #ifdef CONFIG_X86_IO_APIC
1462 setup_ioapic_dest();
1463 #endif
1464 #ifndef CONFIG_HOTPLUG_CPU
1465 /*
1466 * Disable executability of the SMP trampoline:
1467 */
1468 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1469 #endif
1472 void __init smp_intr_init(void)
1474 int irq, seridx;
1476 /*
1477 * IRQ0 must be given a fixed assignment and initialized,
1478 * because it's used before the IO-APIC is set up.
1479 */
1480 irq_vector[0] = FIRST_HIPRIORITY_VECTOR;
1481 vector_irq[FIRST_HIPRIORITY_VECTOR] = 0;
1483 /*
1484 * Also ensure serial interrupts are high priority. We do not
1485 * want them to be blocked by unacknowledged guest-bound interrupts.
1486 */
1487 for (seridx = 0; seridx < 2; seridx++) {
1488 if ((irq = serial_irq(seridx)) < 0)
1489 continue;
1490 irq_vector[irq] = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1491 vector_irq[FIRST_HIPRIORITY_VECTOR + seridx + 1] = irq;
1494 /* IPI for event checking. */
1495 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1497 /* IPI for invalidation */
1498 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1500 /* IPI for generic function call */
1501 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);