debuggers.hg

view xen/drivers/net/8139too.c @ 618:4480b471191c

bitkeeper revision 1.259.2.7 (3f0c428fGYxQAV_56B2hOOjYs1PF0A)

Port a bunch of network drivers for low-quality NICS (which will incur extra copying overheads within Xen). But will allow us to work on a wider range of systems at least.
author kaf24@scramble.cl.cam.ac.uk
date Wed Jul 09 16:27:59 2003 +0000 (2003-07-09)
parents
children 125f43340354
line source
1 /*
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
12 -----<snip>-----
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
36 -----<snip>-----
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
41 Contributors:
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
46 Tigran Aivazian - bug fixes, skbuff free cleanup
48 Martin Mares - suggestions for PCI cleanup
50 David S. Miller - PCI DMA and softnet updates
52 Ernst Gill - fixes ported from BSD driver
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
57 Gerard Sharp - bug fix, testing and feedback
59 David Ford - Rx ring wrap fix
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
67 Santiago Garcia Mantinan - testing and feedback
69 Jens David - 2.2.x kernel backports
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
74 Jean-Jacques Michel - bug fix
76 Tobias Ringström - Rx interrupt status checking suggestion
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
83 Robert Kuebel - Save kernel thread from dying on any signal.
85 Submitting bug reports:
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
90 See 8139too.txt for more details.
92 */
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.26"
97 #include <linux/config.h>
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/lib.h>
101 #include <linux/timer.h>
102 #include <linux/pci.h>
103 #include <linux/init.h>
104 #include <linux/ioport.h>
105 #include <linux/netdevice.h>
106 #include <linux/etherdevice.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/crc32.h>
111 #include <asm/io.h>
112 #include <asm/uaccess.h>
114 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
115 static int next_tick = 3 * HZ;
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
118 #define PFX DRV_NAME ": "
121 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
122 #ifdef CONFIG_8139TOO_PIO
123 #define USE_IO_OPS 1
124 #endif
126 /* define to 1 to enable copious debugging info */
127 #undef RTL8139_DEBUG
129 /* define to 1 to disable lightweight runtime debugging checks */
130 #undef RTL8139_NDEBUG
133 #ifdef RTL8139_DEBUG
134 /* note: prints function name for you */
135 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
136 #else
137 # define DPRINTK(fmt, args...)
138 #endif
140 #ifdef RTL8139_NDEBUG
141 # define assert(expr) do {} while (0)
142 #else
143 # define assert(expr) \
144 if(!(expr)) { \
145 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
146 #expr,__FILE__,__FUNCTION__,__LINE__); \
147 }
148 #endif
151 /* A few user-configurable values. */
152 /* media options */
153 #define MAX_UNITS 8
154 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
155 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
158 static int max_interrupt_work = 20;
160 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
161 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
162 static int multicast_filter_limit = 32;
164 #if 0
165 /* bitmapped message enable number */
166 static int debug = -1;
167 #endif
169 /* Size of the in-memory receive ring. */
170 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
171 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
172 #define RX_BUF_PAD 16
173 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
174 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
176 /* Number of Tx descriptor registers. */
177 #define NUM_TX_DESC 4
179 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
180 #define MAX_ETH_FRAME_SIZE 1536
182 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
183 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
184 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
186 /* PCI Tuning Parameters
187 Threshold is bytes transferred to chip before transmission starts. */
188 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
190 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
191 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
192 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
193 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
194 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
196 /* Operational parameters that usually are not changed. */
197 /* Time in jiffies before concluding the transmitter is hung. */
198 #define TX_TIMEOUT (6*HZ)
201 enum {
202 HAS_MII_XCVR = 0x010000,
203 HAS_CHIP_XCVR = 0x020000,
204 HAS_LNK_CHNG = 0x040000,
205 };
207 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
208 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
209 #define RTL_MIN_IO_SIZE 0x80
210 #define RTL8139B_IO_SIZE 256
212 #define RTL8129_CAPS HAS_MII_XCVR
213 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
215 typedef enum {
216 RTL8139 = 0,
217 RTL8139_CB,
218 SMC1211TX,
219 /*MPX5030,*/
220 DELTA8139,
221 ADDTRON8139,
222 DFE538TX,
223 DFE690TXD,
224 FE2000VX,
225 ALLIED8139,
226 RTL8129,
227 FNW3603TX,
228 FNW3800TX,
229 } board_t;
232 /* indexed by board_t, above */
233 static struct {
234 const char *name;
235 u32 hw_flags;
236 } board_info[] __devinitdata = {
237 { "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },
238 { "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
239 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
240 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
241 { "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
242 { "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
243 { "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
244 { "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },
245 { "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },
246 { "Allied Telesyn 8139 CardBus", RTL8139_CAPS },
247 { "RealTek RTL8129", RTL8129_CAPS },
248 { "Planex FNW-3603-TX 10/100 CardBus", RTL8139_CAPS },
249 { "Planex FNW-3800-TX 10/100 CardBus", RTL8139_CAPS },
250 };
253 static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
254 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },
256 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
257 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
258 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
259 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
260 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
261 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },
262 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },
263 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },
264 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3603TX },
265 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3800TX },
267 #ifdef CONFIG_8139TOO_8129
268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
269 #endif
271 /* some crazy cards report invalid vendor ids like
272 * 0x0001 here. The other ids are valid and constant,
273 * so we simply don't match on the main vendor id.
274 */
275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },
277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, FE2000VX },
279 {0,}
280 };
281 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
283 #if 0
284 static struct {
285 const char str[ETH_GSTRING_LEN];
286 } ethtool_stats_keys[] = {
287 { "early_rx" },
288 { "tx_buf_mapped" },
289 { "tx_timeouts" },
290 { "rx_lost_in_ring" },
291 };
292 #endif
294 /* The rest of these values should never change. */
296 /* Symbolic offsets to registers. */
297 enum RTL8139_registers {
298 MAC0 = 0, /* Ethernet hardware address. */
299 MAR0 = 8, /* Multicast filter. */
300 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
301 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
302 RxBuf = 0x30,
303 ChipCmd = 0x37,
304 RxBufPtr = 0x38,
305 RxBufAddr = 0x3A,
306 IntrMask = 0x3C,
307 IntrStatus = 0x3E,
308 TxConfig = 0x40,
309 ChipVersion = 0x43,
310 RxConfig = 0x44,
311 Timer = 0x48, /* A general-purpose counter. */
312 RxMissed = 0x4C, /* 24 bits valid, write clears. */
313 Cfg9346 = 0x50,
314 Config0 = 0x51,
315 Config1 = 0x52,
316 FlashReg = 0x54,
317 MediaStatus = 0x58,
318 Config3 = 0x59,
319 Config4 = 0x5A, /* absent on RTL-8139A */
320 HltClk = 0x5B,
321 MultiIntr = 0x5C,
322 TxSummary = 0x60,
323 BasicModeCtrl = 0x62,
324 BasicModeStatus = 0x64,
325 NWayAdvert = 0x66,
326 NWayLPAR = 0x68,
327 NWayExpansion = 0x6A,
328 /* Undocumented registers, but required for proper operation. */
329 FIFOTMS = 0x70, /* FIFO Control and test. */
330 CSCR = 0x74, /* Chip Status and Configuration Register. */
331 PARA78 = 0x78,
332 PARA7c = 0x7c, /* Magic transceiver parameter register. */
333 Config5 = 0xD8, /* absent on RTL-8139A */
334 };
336 enum ClearBitMasks {
337 MultiIntrClear = 0xF000,
338 ChipCmdClear = 0xE2,
339 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
340 };
342 enum ChipCmdBits {
343 CmdReset = 0x10,
344 CmdRxEnb = 0x08,
345 CmdTxEnb = 0x04,
346 RxBufEmpty = 0x01,
347 };
349 /* Interrupt register bits, using my own meaningful names. */
350 enum IntrStatusBits {
351 PCIErr = 0x8000,
352 PCSTimeout = 0x4000,
353 RxFIFOOver = 0x40,
354 RxUnderrun = 0x20,
355 RxOverflow = 0x10,
356 TxErr = 0x08,
357 TxOK = 0x04,
358 RxErr = 0x02,
359 RxOK = 0x01,
361 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
362 };
364 enum TxStatusBits {
365 TxHostOwns = 0x2000,
366 TxUnderrun = 0x4000,
367 TxStatOK = 0x8000,
368 TxOutOfWindow = 0x20000000,
369 TxAborted = 0x40000000,
370 TxCarrierLost = 0x80000000,
371 };
372 enum RxStatusBits {
373 RxMulticast = 0x8000,
374 RxPhysical = 0x4000,
375 RxBroadcast = 0x2000,
376 RxBadSymbol = 0x0020,
377 RxRunt = 0x0010,
378 RxTooLong = 0x0008,
379 RxCRCErr = 0x0004,
380 RxBadAlign = 0x0002,
381 RxStatusOK = 0x0001,
382 };
384 /* Bits in RxConfig. */
385 enum rx_mode_bits {
386 AcceptErr = 0x20,
387 AcceptRunt = 0x10,
388 AcceptBroadcast = 0x08,
389 AcceptMulticast = 0x04,
390 AcceptMyPhys = 0x02,
391 AcceptAllPhys = 0x01,
392 };
394 /* Bits in TxConfig. */
395 enum tx_config_bits {
396 TxIFG1 = (1 << 25), /* Interframe Gap Time */
397 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
398 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
399 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
400 TxClearAbt = (1 << 0), /* Clear abort (WO) */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
402 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
404 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
405 };
407 /* Bits in Config1 */
408 enum Config1Bits {
409 Cfg1_PM_Enable = 0x01,
410 Cfg1_VPD_Enable = 0x02,
411 Cfg1_PIO = 0x04,
412 Cfg1_MMIO = 0x08,
413 LWAKE = 0x10, /* not on 8139, 8139A */
414 Cfg1_Driver_Load = 0x20,
415 Cfg1_LED0 = 0x40,
416 Cfg1_LED1 = 0x80,
417 SLEEP = (1 << 1), /* only on 8139, 8139A */
418 PWRDN = (1 << 0), /* only on 8139, 8139A */
419 };
421 /* Bits in Config3 */
422 enum Config3Bits {
423 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
424 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
425 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
426 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
427 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
428 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
429 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
430 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
431 };
433 /* Bits in Config4 */
434 enum Config4Bits {
435 LWPTN = (1 << 2), /* not on 8139, 8139A */
436 };
438 /* Bits in Config5 */
439 enum Config5Bits {
440 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
441 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
442 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
443 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
444 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
445 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
446 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 };
449 enum RxConfigBits {
450 /* rx fifo threshold */
451 RxCfgFIFOShift = 13,
452 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454 /* Max DMA burst */
455 RxCfgDMAShift = 8,
456 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458 /* rx ring buffer length */
459 RxCfgRcv8K = 0,
460 RxCfgRcv16K = (1 << 11),
461 RxCfgRcv32K = (1 << 12),
462 RxCfgRcv64K = (1 << 11) | (1 << 12),
464 /* Disable packet wrap at end of Rx buffer */
465 RxNoWrap = (1 << 7),
466 };
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
480 enum Cfg9346Bits {
481 Cfg9346_Lock = 0x00,
482 Cfg9346_Unlock = 0xC0,
483 };
485 #ifdef CONFIG_8139TOO_TUNE_TWISTER
487 enum TwisterParamVals {
488 PARA78_default = 0x78fa8388,
489 PARA7c_default = 0xcb38de43, /* param[0][3] */
490 PARA7c_xxx = 0xcb38de43,
491 };
493 static const unsigned long param[4][4] = {
494 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
495 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
496 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
497 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
498 };
500 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
502 typedef enum {
503 CH_8139 = 0,
504 CH_8139_K,
505 CH_8139A,
506 CH_8139B,
507 CH_8130,
508 CH_8139C,
509 } chip_t;
511 enum chip_flags {
512 HasHltClk = (1 << 0),
513 HasLWake = (1 << 1),
514 };
517 /* directly indexed by chip_t, above */
518 const static struct {
519 const char *name;
520 u8 version; /* from RTL8139C docs */
521 u32 RxConfigMask; /* should clear the bits supported by this chip */
522 u32 flags;
523 } rtl_chip_info[] = {
524 { "RTL-8139",
525 0x40,
526 0xf0fe0040, /* XXX copied from RTL8139A, verify */
527 HasHltClk,
528 },
530 { "RTL-8139 rev K",
531 0x60,
532 0xf0fe0040,
533 HasHltClk,
534 },
536 { "RTL-8139A",
537 0x70,
538 0xf0fe0040,
539 HasHltClk, /* XXX undocumented? */
540 },
542 { "RTL-8139B",
543 0x78,
544 0xf0fc0040,
545 HasLWake,
546 },
548 { "RTL-8130",
549 0x7C,
550 0xf0fe0040, /* XXX copied from RTL8139A, verify */
551 HasLWake,
552 },
554 { "RTL-8139C",
555 0x74,
556 0xf0fc0040, /* XXX copied from RTL8139B, verify */
557 HasLWake,
558 },
560 };
562 struct rtl_extra_stats {
563 unsigned long early_rx;
564 unsigned long tx_buf_mapped;
565 unsigned long tx_timeouts;
566 unsigned long rx_lost_in_ring;
567 };
569 struct rtl8139_private {
570 void *mmio_addr;
571 int drv_flags;
572 struct pci_dev *pci_dev;
573 struct net_device_stats stats;
574 unsigned char *rx_ring;
575 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
576 unsigned int tx_flag;
577 unsigned long cur_tx;
578 unsigned long dirty_tx;
579 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
580 unsigned char *tx_bufs; /* Tx bounce buffer region. */
581 dma_addr_t rx_ring_dma;
582 dma_addr_t tx_bufs_dma;
583 signed char phys[4]; /* MII device addresses. */
584 char twistie, twist_row, twist_col; /* Twister tune state. */
585 unsigned int default_port:4; /* Last dev->if_port value. */
586 spinlock_t lock;
587 chip_t chipset;
588 #if 0
589 pid_t thr_pid;
590 wait_queue_head_t thr_wait;
591 struct completion thr_exited;
592 #else
593 struct timer_list timer;
594 #endif
595 u32 rx_config;
596 struct rtl_extra_stats xstats;
597 int time_to_die;
598 struct mii_if_info mii;
599 unsigned int regs_len;
600 };
602 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
603 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
604 MODULE_LICENSE("GPL");
606 MODULE_PARM (multicast_filter_limit, "i");
607 MODULE_PARM (max_interrupt_work, "i");
608 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
609 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
610 MODULE_PARM (debug, "i");
611 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
612 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
613 MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
614 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
615 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
617 static int read_eeprom (void *ioaddr, int location, int addr_len);
618 static int rtl8139_open (struct net_device *dev);
619 static int mdio_read (struct net_device *dev, int phy_id, int location);
620 static void mdio_write (struct net_device *dev, int phy_id, int location,
621 int val);
622 #if 0
623 static int rtl8139_thread (void *data);
624 #else
625 static void rtl8139_timer (unsigned long arg);
626 #endif
627 static void rtl8139_tx_timeout (struct net_device *dev);
628 static void rtl8139_init_ring (struct net_device *dev);
629 static int rtl8139_start_xmit (struct sk_buff *skb,
630 struct net_device *dev);
631 static void rtl8139_interrupt (int irq, void *dev_instance,
632 struct pt_regs *regs);
633 static int rtl8139_close (struct net_device *dev);
634 #if 0
635 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
636 #endif
637 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
638 static void rtl8139_set_rx_mode (struct net_device *dev);
639 static void __set_rx_mode (struct net_device *dev);
640 static void rtl8139_hw_start (struct net_device *dev);
642 #ifdef USE_IO_OPS
644 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
645 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
646 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
647 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
648 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
649 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
650 #define RTL_W8_F RTL_W8
651 #define RTL_W16_F RTL_W16
652 #define RTL_W32_F RTL_W32
653 #undef readb
654 #undef readw
655 #undef readl
656 #undef writeb
657 #undef writew
658 #undef writel
659 #define readb(addr) inb((unsigned long)(addr))
660 #define readw(addr) inw((unsigned long)(addr))
661 #define readl(addr) inl((unsigned long)(addr))
662 #define writeb(val,addr) outb((val),(unsigned long)(addr))
663 #define writew(val,addr) outw((val),(unsigned long)(addr))
664 #define writel(val,addr) outl((val),(unsigned long)(addr))
666 #else
668 /* write MMIO register, with flush */
669 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
670 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
671 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
672 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
675 #define MMIO_FLUSH_AUDIT_COMPLETE 1
676 #if MMIO_FLUSH_AUDIT_COMPLETE
678 /* write MMIO register */
679 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
680 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
681 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
683 #else
685 /* write MMIO register, then flush */
686 #define RTL_W8 RTL_W8_F
687 #define RTL_W16 RTL_W16_F
688 #define RTL_W32 RTL_W32_F
690 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
692 /* read MMIO register */
693 #define RTL_R8(reg) readb (ioaddr + (reg))
694 #define RTL_R16(reg) readw (ioaddr + (reg))
695 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
697 #endif /* USE_IO_OPS */
700 static const u16 rtl8139_intr_mask =
701 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
702 TxErr | TxOK | RxErr | RxOK;
704 static const unsigned int rtl8139_rx_config =
705 RxCfgRcv32K | RxNoWrap |
706 (RX_FIFO_THRESH << RxCfgFIFOShift) |
707 (RX_DMA_BURST << RxCfgDMAShift);
709 static const unsigned int rtl8139_tx_config =
710 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
712 static void __rtl8139_cleanup_dev (struct net_device *dev)
713 {
714 struct rtl8139_private *tp;
715 struct pci_dev *pdev;
717 assert (dev != NULL);
718 assert (dev->priv != NULL);
720 tp = dev->priv;
721 assert (tp->pci_dev != NULL);
722 pdev = tp->pci_dev;
724 #ifndef USE_IO_OPS
725 if (tp->mmio_addr)
726 iounmap (tp->mmio_addr);
727 #endif /* !USE_IO_OPS */
729 /* it's ok to call this even if we have no regions to free */
730 pci_release_regions (pdev);
732 #ifndef RTL8139_NDEBUG
733 /* poison memory before freeing */
734 memset (dev, 0xBC,
735 sizeof (struct net_device) +
736 sizeof (struct rtl8139_private));
737 #endif /* RTL8139_NDEBUG */
739 kfree (dev);
741 pci_set_drvdata (pdev, NULL);
742 }
745 static void rtl8139_chip_reset (void *ioaddr)
746 {
747 int i;
749 /* Soft reset the chip. */
750 RTL_W8 (ChipCmd, CmdReset);
752 /* Check that the chip has finished the reset. */
753 for (i = 1000; i > 0; i--) {
754 barrier();
755 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
756 break;
757 udelay (10);
758 }
759 }
762 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
763 struct net_device **dev_out)
764 {
765 void *ioaddr;
766 struct net_device *dev;
767 struct rtl8139_private *tp;
768 u8 tmp8;
769 int rc;
770 unsigned int i;
771 u32 pio_start, pio_end, pio_flags, pio_len;
772 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
773 u32 tmp;
775 assert (pdev != NULL);
777 *dev_out = NULL;
779 /* dev and dev->priv zeroed in alloc_etherdev */
780 dev = alloc_etherdev (sizeof (*tp));
781 if (dev == NULL) {
782 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);
783 return -ENOMEM;
784 }
785 SET_MODULE_OWNER(dev);
786 tp = dev->priv;
787 tp->pci_dev = pdev;
789 /* enable device (incl. PCI PM wakeup and hotplug setup) */
790 rc = pci_enable_device (pdev);
791 if (rc)
792 goto err_out;
794 pio_start = pci_resource_start (pdev, 0);
795 pio_end = pci_resource_end (pdev, 0);
796 pio_flags = pci_resource_flags (pdev, 0);
797 pio_len = pci_resource_len (pdev, 0);
799 mmio_start = pci_resource_start (pdev, 1);
800 mmio_end = pci_resource_end (pdev, 1);
801 mmio_flags = pci_resource_flags (pdev, 1);
802 mmio_len = pci_resource_len (pdev, 1);
804 /* set this immediately, we need to know before
805 * we talk to the chip directly */
806 DPRINTK("PIO region size == 0x%02X\n", pio_len);
807 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
809 #ifdef USE_IO_OPS
810 /* make sure PCI base addr 0 is PIO */
811 if (!(pio_flags & IORESOURCE_IO)) {
812 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);
813 rc = -ENODEV;
814 goto err_out;
815 }
816 /* check for weird/broken PCI region reporting */
817 if (pio_len < RTL_MIN_IO_SIZE) {
818 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);
819 rc = -ENODEV;
820 goto err_out;
821 }
822 #else
823 /* make sure PCI base addr 1 is MMIO */
824 if (!(mmio_flags & IORESOURCE_MEM)) {
825 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);
826 rc = -ENODEV;
827 goto err_out;
828 }
829 if (mmio_len < RTL_MIN_IO_SIZE) {
830 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);
831 rc = -ENODEV;
832 goto err_out;
833 }
834 #endif
836 rc = pci_request_regions (pdev, "8139too");
837 if (rc)
838 goto err_out;
840 /* enable PCI bus-mastering */
841 pci_set_master (pdev);
843 #ifdef USE_IO_OPS
844 ioaddr = (void *) pio_start;
845 dev->base_addr = pio_start;
846 tp->mmio_addr = ioaddr;
847 tp->regs_len = pio_len;
848 #else
849 /* ioremap MMIO region */
850 ioaddr = ioremap (mmio_start, mmio_len);
851 if (ioaddr == NULL) {
852 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);
853 rc = -EIO;
854 goto err_out;
855 }
856 dev->base_addr = (long) ioaddr;
857 tp->mmio_addr = ioaddr;
858 tp->regs_len = mmio_len;
859 #endif /* USE_IO_OPS */
861 /* Bring old chips out of low-power mode. */
862 RTL_W8 (HltClk, 'R');
864 /* check for missing/broken hardware */
865 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
866 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
867 pdev->slot_name);
868 rc = -EIO;
869 goto err_out;
870 }
872 /* identify chip attached to board */
873 tmp = RTL_R8 (ChipVersion);
874 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
875 if (tmp == rtl_chip_info[i].version) {
876 tp->chipset = i;
877 goto match;
878 }
880 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
881 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
882 pdev->slot_name);
883 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));
884 tp->chipset = 0;
886 match:
887 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
888 tmp,
889 tp->chipset,
890 rtl_chip_info[tp->chipset].name);
892 if (tp->chipset >= CH_8139B) {
893 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
894 DPRINTK("PCI PM wakeup\n");
895 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
896 (tmp8 & LWAKE))
897 new_tmp8 &= ~LWAKE;
898 new_tmp8 |= Cfg1_PM_Enable;
899 if (new_tmp8 != tmp8) {
900 RTL_W8 (Cfg9346, Cfg9346_Unlock);
901 RTL_W8 (Config1, tmp8);
902 RTL_W8 (Cfg9346, Cfg9346_Lock);
903 }
904 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
905 tmp8 = RTL_R8 (Config4);
906 if (tmp8 & LWPTN)
907 RTL_W8 (Config4, tmp8 & ~LWPTN);
908 }
909 } else {
910 DPRINTK("Old chip wakeup\n");
911 tmp8 = RTL_R8 (Config1);
912 tmp8 &= ~(SLEEP | PWRDN);
913 RTL_W8 (Config1, tmp8);
914 }
916 rtl8139_chip_reset (ioaddr);
918 *dev_out = dev;
919 return 0;
921 err_out:
922 __rtl8139_cleanup_dev (dev);
923 return rc;
924 }
927 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
928 const struct pci_device_id *ent)
929 {
930 struct net_device *dev = NULL;
931 struct rtl8139_private *tp;
932 int i, addr_len, option;
933 void *ioaddr;
934 static int board_idx = -1;
935 u8 pci_rev;
937 assert (pdev != NULL);
938 assert (ent != NULL);
940 board_idx++;
942 /* when we're built into the kernel, the driver version message
943 * is only printed if at least one 8139 board has been found
944 */
945 #ifndef MODULE
946 {
947 static int printed_version;
948 if (!printed_version++)
949 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
950 }
951 #endif
953 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
955 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
956 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
957 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
958 pdev->slot_name, pdev->vendor, pdev->device, pci_rev);
959 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
960 }
962 i = rtl8139_init_board (pdev, &dev);
963 if (i < 0)
964 return i;
966 tp = dev->priv;
967 ioaddr = tp->mmio_addr;
969 assert (ioaddr != NULL);
970 assert (dev != NULL);
971 assert (tp != NULL);
973 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
974 for (i = 0; i < 3; i++)
975 ((u16 *) (dev->dev_addr))[i] =
976 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
978 /* The Rtl8139-specific entries in the device structure. */
979 dev->open = rtl8139_open;
980 dev->hard_start_xmit = rtl8139_start_xmit;
981 dev->stop = rtl8139_close;
982 dev->get_stats = rtl8139_get_stats;
983 dev->set_multicast_list = rtl8139_set_rx_mode;
984 #if 0
985 dev->do_ioctl = netdev_ioctl;
986 #endif
987 dev->tx_timeout = rtl8139_tx_timeout;
988 dev->watchdog_timeo = TX_TIMEOUT;
990 /* note: the hardware is not capable of sg/csum/highdma, however
991 * through the use of skb_copy_and_csum_dev we enable these
992 * features
993 */
994 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
996 dev->irq = pdev->irq;
998 /* dev->priv/tp zeroed and aligned in init_etherdev */
999 tp = dev->priv;
1001 /* note: tp->chipset set in rtl8139_init_board */
1002 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1003 tp->mmio_addr = ioaddr;
1004 spin_lock_init (&tp->lock);
1005 #if 0
1006 init_waitqueue_head (&tp->thr_wait);
1007 init_completion (&tp->thr_exited);
1008 #endif
1009 tp->mii.dev = dev;
1010 tp->mii.mdio_read = mdio_read;
1011 tp->mii.mdio_write = mdio_write;
1012 tp->mii.phy_id_mask = 0x3f;
1013 tp->mii.reg_num_mask = 0x1f;
1015 /* dev is fully set up and ready to use now */
1016 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1017 i = register_netdev (dev);
1018 if (i) goto err_out;
1020 pci_set_drvdata (pdev, dev);
1022 printk (KERN_INFO "%s: %s at 0x%lx, "
1023 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1024 "IRQ %d\n",
1025 dev->name,
1026 board_info[ent->driver_data].name,
1027 dev->base_addr,
1028 dev->dev_addr[0], dev->dev_addr[1],
1029 dev->dev_addr[2], dev->dev_addr[3],
1030 dev->dev_addr[4], dev->dev_addr[5],
1031 dev->irq);
1033 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1034 dev->name, rtl_chip_info[tp->chipset].name);
1036 /* Find the connected MII xcvrs.
1037 Doing this in open() would allow detecting external xcvrs later, but
1038 takes too much time. */
1039 #ifdef CONFIG_8139TOO_8129
1040 if (tp->drv_flags & HAS_MII_XCVR) {
1041 int phy, phy_idx = 0;
1042 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1043 int mii_status = mdio_read(dev, phy, 1);
1044 if (mii_status != 0xffff && mii_status != 0x0000) {
1045 u16 advertising = mdio_read(dev, phy, 4);
1046 tp->phys[phy_idx++] = phy;
1047 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1048 "advertising %4.4x.\n",
1049 dev->name, phy, mii_status, advertising);
1052 if (phy_idx == 0) {
1053 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1054 "transceiver.\n",
1055 dev->name);
1056 tp->phys[0] = 32;
1058 } else
1059 #endif
1060 tp->phys[0] = 32;
1061 tp->mii.phy_id = tp->phys[0];
1063 /* The lower four bits are the media type. */
1064 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1065 if (option > 0) {
1066 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1067 tp->default_port = option & 0xFF;
1068 if (tp->default_port)
1069 tp->mii.force_media = 1;
1071 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1072 tp->mii.full_duplex = full_duplex[board_idx];
1073 if (tp->mii.full_duplex) {
1074 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1075 /* Changing the MII-advertised media because might prevent
1076 re-connection. */
1077 tp->mii.force_media = 1;
1079 if (tp->default_port) {
1080 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1081 (option & 0x20 ? 100 : 10),
1082 (option & 0x10 ? "full" : "half"));
1083 mdio_write(dev, tp->phys[0], 0,
1084 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1085 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1088 /* Put the chip into low-power mode. */
1089 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1090 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1092 alert_slow_netdevice(dev, (char *)board_info[ent->driver_data].name);
1094 return 0;
1096 err_out:
1097 __rtl8139_cleanup_dev (dev);
1098 return i;
1102 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1104 struct net_device *dev = pci_get_drvdata (pdev);
1105 struct rtl8139_private *np;
1107 assert (dev != NULL);
1108 np = dev->priv;
1109 assert (np != NULL);
1111 unregister_netdev (dev);
1113 __rtl8139_cleanup_dev (dev);
1117 /* Serial EEPROM section. */
1119 /* EEPROM_Ctrl bits. */
1120 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1121 #define EE_CS 0x08 /* EEPROM chip select. */
1122 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1123 #define EE_WRITE_0 0x00
1124 #define EE_WRITE_1 0x02
1125 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1126 #define EE_ENB (0x80 | EE_CS)
1128 /* Delay between EEPROM clock transitions.
1129 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1130 */
1132 #define eeprom_delay() readl(ee_addr)
1134 /* The EEPROM commands include the alway-set leading bit. */
1135 #define EE_WRITE_CMD (5)
1136 #define EE_READ_CMD (6)
1137 #define EE_ERASE_CMD (7)
1139 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1141 int i;
1142 unsigned retval = 0;
1143 void *ee_addr = ioaddr + Cfg9346;
1144 int read_cmd = location | (EE_READ_CMD << addr_len);
1146 writeb (EE_ENB & ~EE_CS, ee_addr);
1147 writeb (EE_ENB, ee_addr);
1148 eeprom_delay ();
1150 /* Shift the read command bits out. */
1151 for (i = 4 + addr_len; i >= 0; i--) {
1152 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1153 writeb (EE_ENB | dataval, ee_addr);
1154 eeprom_delay ();
1155 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1156 eeprom_delay ();
1158 writeb (EE_ENB, ee_addr);
1159 eeprom_delay ();
1161 for (i = 16; i > 0; i--) {
1162 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1163 eeprom_delay ();
1164 retval =
1165 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1166 0);
1167 writeb (EE_ENB, ee_addr);
1168 eeprom_delay ();
1171 /* Terminate the EEPROM access. */
1172 writeb (~EE_CS, ee_addr);
1173 eeprom_delay ();
1175 return retval;
1178 /* MII serial management: mostly bogus for now. */
1179 /* Read and write the MII management registers using software-generated
1180 serial MDIO protocol.
1181 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1182 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1183 "overclocking" issues. */
1184 #define MDIO_DIR 0x80
1185 #define MDIO_DATA_OUT 0x04
1186 #define MDIO_DATA_IN 0x02
1187 #define MDIO_CLK 0x01
1188 #define MDIO_WRITE0 (MDIO_DIR)
1189 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1191 #define mdio_delay(mdio_addr) readb(mdio_addr)
1194 static char mii_2_8139_map[8] = {
1195 BasicModeCtrl,
1196 BasicModeStatus,
1197 0,
1198 0,
1199 NWayAdvert,
1200 NWayLPAR,
1201 NWayExpansion,
1203 };
1206 #ifdef CONFIG_8139TOO_8129
1207 /* Syncronize the MII management interface by shifting 32 one bits out. */
1208 static void mdio_sync (void *mdio_addr)
1210 int i;
1212 for (i = 32; i >= 0; i--) {
1213 writeb (MDIO_WRITE1, mdio_addr);
1214 mdio_delay (mdio_addr);
1215 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1216 mdio_delay (mdio_addr);
1219 #endif
1221 static int mdio_read (struct net_device *dev, int phy_id, int location)
1223 struct rtl8139_private *tp = dev->priv;
1224 int retval = 0;
1225 #ifdef CONFIG_8139TOO_8129
1226 void *mdio_addr = tp->mmio_addr + Config4;
1227 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1228 int i;
1229 #endif
1231 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1232 return location < 8 && mii_2_8139_map[location] ?
1233 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1236 #ifdef CONFIG_8139TOO_8129
1237 mdio_sync (mdio_addr);
1238 /* Shift the read command bits out. */
1239 for (i = 15; i >= 0; i--) {
1240 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1242 writeb (MDIO_DIR | dataval, mdio_addr);
1243 mdio_delay (mdio_addr);
1244 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1245 mdio_delay (mdio_addr);
1248 /* Read the two transition, 16 data, and wire-idle bits. */
1249 for (i = 19; i > 0; i--) {
1250 writeb (0, mdio_addr);
1251 mdio_delay (mdio_addr);
1252 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1253 writeb (MDIO_CLK, mdio_addr);
1254 mdio_delay (mdio_addr);
1256 #endif
1258 return (retval >> 1) & 0xffff;
1262 static void mdio_write (struct net_device *dev, int phy_id, int location,
1263 int value)
1265 struct rtl8139_private *tp = dev->priv;
1266 #ifdef CONFIG_8139TOO_8129
1267 void *mdio_addr = tp->mmio_addr + Config4;
1268 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1269 int i;
1270 #endif
1272 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1273 void *ioaddr = tp->mmio_addr;
1274 if (location == 0) {
1275 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1276 RTL_W16 (BasicModeCtrl, value);
1277 RTL_W8 (Cfg9346, Cfg9346_Lock);
1278 } else if (location < 8 && mii_2_8139_map[location])
1279 RTL_W16 (mii_2_8139_map[location], value);
1280 return;
1283 #ifdef CONFIG_8139TOO_8129
1284 mdio_sync (mdio_addr);
1286 /* Shift the command bits out. */
1287 for (i = 31; i >= 0; i--) {
1288 int dataval =
1289 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1290 writeb (dataval, mdio_addr);
1291 mdio_delay (mdio_addr);
1292 writeb (dataval | MDIO_CLK, mdio_addr);
1293 mdio_delay (mdio_addr);
1295 /* Clear out extra bits. */
1296 for (i = 2; i > 0; i--) {
1297 writeb (0, mdio_addr);
1298 mdio_delay (mdio_addr);
1299 writeb (MDIO_CLK, mdio_addr);
1300 mdio_delay (mdio_addr);
1302 #endif
1306 static int rtl8139_open (struct net_device *dev)
1308 struct rtl8139_private *tp = dev->priv;
1309 int retval;
1310 #ifdef RTL8139_DEBUG
1311 void *ioaddr = tp->mmio_addr;
1312 #endif
1314 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1315 if (retval)
1316 return retval;
1318 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1319 &tp->tx_bufs_dma);
1320 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1321 &tp->rx_ring_dma);
1322 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1323 free_irq(dev->irq, dev);
1325 if (tp->tx_bufs)
1326 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1327 tp->tx_bufs, tp->tx_bufs_dma);
1328 if (tp->rx_ring)
1329 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1330 tp->rx_ring, tp->rx_ring_dma);
1332 return -ENOMEM;
1336 tp->mii.full_duplex = tp->mii.force_media;
1337 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1338 tp->twistie = (tp->chipset == CH_8139_K) ? 1 : 0;
1339 tp->time_to_die = 0;
1341 rtl8139_init_ring (dev);
1342 rtl8139_hw_start (dev);
1344 DPRINTK ("%s: rtl8139_open() ioaddr %#lx IRQ %d"
1345 " GP Pins %2.2x %s-duplex.\n",
1346 dev->name, pci_resource_start (tp->pci_dev, 1),
1347 dev->irq, RTL_R8 (MediaStatus),
1348 tp->mii.full_duplex ? "full" : "half");
1350 #if 0
1351 tp->thr_pid = kernel_thread (rtl8139_thread, dev, CLONE_FS | CLONE_FILES);
1352 if (tp->thr_pid < 0)
1353 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1354 dev->name);
1355 #else
1356 init_timer(&tp->timer);
1357 tp->timer.expires = jiffies + next_tick;
1358 tp->timer.data = (unsigned long)dev;
1359 tp->timer.function = rtl8139_timer;
1360 add_timer(&tp->timer);
1361 #endif
1363 return 0;
1367 static void rtl_check_media (struct net_device *dev)
1369 struct rtl8139_private *tp = dev->priv;
1371 if (tp->phys[0] >= 0) {
1372 u16 mii_lpa = mdio_read(dev, tp->phys[0], MII_LPA);
1373 if (mii_lpa == 0xffff)
1374 ; /* Not there */
1375 else if ((mii_lpa & LPA_100FULL) == LPA_100FULL
1376 || (mii_lpa & 0x00C0) == LPA_10FULL)
1377 tp->mii.full_duplex = 1;
1379 printk (KERN_INFO"%s: Setting %s%s-duplex based on"
1380 " auto-negotiated partner ability %4.4x.\n",
1381 dev->name, mii_lpa == 0 ? "" :
1382 (mii_lpa & 0x0180) ? "100mbps " : "10mbps ",
1383 tp->mii.full_duplex ? "full" : "half", mii_lpa);
1387 /* Start the hardware at open or resume. */
1388 static void rtl8139_hw_start (struct net_device *dev)
1390 struct rtl8139_private *tp = dev->priv;
1391 void *ioaddr = tp->mmio_addr;
1392 u32 i;
1393 u8 tmp;
1395 /* Bring old chips out of low-power mode. */
1396 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1397 RTL_W8 (HltClk, 'R');
1399 rtl8139_chip_reset (ioaddr);
1401 /* unlock Config[01234] and BMCR register writes */
1402 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1403 /* Restore our idea of the MAC address. */
1404 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1405 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1407 /* Must enable Tx/Rx before setting transfer thresholds! */
1408 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1410 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1411 RTL_W32 (RxConfig, tp->rx_config);
1413 /* Check this value: the documentation for IFG contradicts ifself. */
1414 RTL_W32 (TxConfig, rtl8139_tx_config);
1416 tp->cur_rx = 0;
1418 rtl_check_media (dev);
1420 if (tp->chipset >= CH_8139B) {
1421 /* Disable magic packet scanning, which is enabled
1422 * when PM is enabled in Config1. It can be reenabled
1423 * via ETHTOOL_SWOL if desired. */
1424 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1427 DPRINTK("init buffer addresses\n");
1429 /* Lock Config[01234] and BMCR register writes */
1430 RTL_W8 (Cfg9346, Cfg9346_Lock);
1432 /* init Rx ring buffer DMA address */
1433 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1435 /* init Tx buffer DMA addresses */
1436 for (i = 0; i < NUM_TX_DESC; i++)
1437 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1439 RTL_W32 (RxMissed, 0);
1441 rtl8139_set_rx_mode (dev);
1443 /* no early-rx interrupts */
1444 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1446 /* make sure RxTx has started */
1447 tmp = RTL_R8 (ChipCmd);
1448 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1449 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1451 /* Enable all known interrupts by setting the interrupt mask. */
1452 RTL_W16 (IntrMask, rtl8139_intr_mask);
1454 netif_start_queue (dev);
1458 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1459 static void rtl8139_init_ring (struct net_device *dev)
1461 struct rtl8139_private *tp = dev->priv;
1462 int i;
1464 tp->cur_rx = 0;
1465 tp->cur_tx = 0;
1466 tp->dirty_tx = 0;
1468 for (i = 0; i < NUM_TX_DESC; i++)
1469 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1473 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1474 static inline void rtl8139_tune_twister (struct net_device *dev,
1475 struct rtl8139_private *tp) {}
1476 #else
1477 static void rtl8139_tune_twister (struct net_device *dev,
1478 struct rtl8139_private *tp)
1480 int linkcase;
1481 void *ioaddr = tp->mmio_addr;
1483 /* This is a complicated state machine to configure the "twister" for
1484 impedance/echos based on the cable length.
1485 All of this is magic and undocumented.
1486 */
1487 switch (tp->twistie) {
1488 case 1:
1489 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1490 /* We have link beat, let us tune the twister. */
1491 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1492 tp->twistie = 2; /* Change to state 2. */
1493 next_tick = HZ / 10;
1494 } else {
1495 /* Just put in some reasonable defaults for when beat returns. */
1496 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1497 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1498 RTL_W32 (PARA78, PARA78_default);
1499 RTL_W32 (PARA7c, PARA7c_default);
1500 tp->twistie = 0; /* Bail from future actions. */
1502 break;
1503 case 2:
1504 /* Read how long it took to hear the echo. */
1505 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1506 if (linkcase == 0x7000)
1507 tp->twist_row = 3;
1508 else if (linkcase == 0x3000)
1509 tp->twist_row = 2;
1510 else if (linkcase == 0x1000)
1511 tp->twist_row = 1;
1512 else
1513 tp->twist_row = 0;
1514 tp->twist_col = 0;
1515 tp->twistie = 3; /* Change to state 2. */
1516 next_tick = HZ / 10;
1517 break;
1518 case 3:
1519 /* Put out four tuning parameters, one per 100msec. */
1520 if (tp->twist_col == 0)
1521 RTL_W16 (FIFOTMS, 0);
1522 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1523 [(int) tp->twist_col]);
1524 next_tick = HZ / 10;
1525 if (++tp->twist_col >= 4) {
1526 /* For short cables we are done.
1527 For long cables (row == 3) check for mistune. */
1528 tp->twistie =
1529 (tp->twist_row == 3) ? 4 : 0;
1531 break;
1532 case 4:
1533 /* Special case for long cables: check for mistune. */
1534 if ((RTL_R16 (CSCR) &
1535 CSCR_LinkStatusBits) == 0x7000) {
1536 tp->twistie = 0;
1537 break;
1538 } else {
1539 RTL_W32 (PARA7c, 0xfb38de03);
1540 tp->twistie = 5;
1541 next_tick = HZ / 10;
1543 break;
1544 case 5:
1545 /* Retune for shorter cable (column 2). */
1546 RTL_W32 (FIFOTMS, 0x20);
1547 RTL_W32 (PARA78, PARA78_default);
1548 RTL_W32 (PARA7c, PARA7c_default);
1549 RTL_W32 (FIFOTMS, 0x00);
1550 tp->twist_row = 2;
1551 tp->twist_col = 0;
1552 tp->twistie = 3;
1553 next_tick = HZ / 10;
1554 break;
1556 default:
1557 /* do nothing */
1558 break;
1561 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1564 static inline void rtl8139_thread_iter (struct net_device *dev,
1565 struct rtl8139_private *tp,
1566 void *ioaddr)
1568 int mii_lpa;
1570 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1572 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1573 int duplex = (mii_lpa & LPA_100FULL)
1574 || (mii_lpa & 0x01C0) == 0x0040;
1575 if (tp->mii.full_duplex != duplex) {
1576 tp->mii.full_duplex = duplex;
1578 if (mii_lpa) {
1579 printk (KERN_INFO
1580 "%s: Setting %s-duplex based on MII #%d link"
1581 " partner ability of %4.4x.\n",
1582 dev->name,
1583 tp->mii.full_duplex ? "full" : "half",
1584 tp->phys[0], mii_lpa);
1585 } else {
1586 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1587 dev->name);
1589 #if 0
1590 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1591 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1592 RTL_W8 (Cfg9346, Cfg9346_Lock);
1593 #endif
1597 next_tick = HZ * 60;
1599 rtl8139_tune_twister (dev, tp);
1601 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1602 dev->name, RTL_R16 (NWayLPAR));
1603 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1604 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1605 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1606 dev->name, RTL_R8 (Config0),
1607 RTL_R8 (Config1));
1611 #if 0
1612 static int rtl8139_thread (void *data)
1614 struct net_device *dev = data;
1615 struct rtl8139_private *tp = dev->priv;
1616 unsigned long timeout;
1618 daemonize ();
1619 reparent_to_init();
1620 spin_lock_irq(&current->sigmask_lock);
1621 sigemptyset(&current->blocked);
1622 recalc_sigpending(current);
1623 spin_unlock_irq(&current->sigmask_lock);
1625 strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
1626 current->comm[sizeof(current->comm) - 1] = '\0';
1628 while (1) {
1629 timeout = next_tick;
1630 do {
1631 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1632 } while (!signal_pending (current) && (timeout > 0));
1634 if (signal_pending (current)) {
1635 spin_lock_irq(&current->sigmask_lock);
1636 flush_signals(current);
1637 spin_unlock_irq(&current->sigmask_lock);
1640 if (tp->time_to_die)
1641 break;
1643 rtnl_lock ();
1644 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1645 rtnl_unlock ();
1648 complete_and_exit (&tp->thr_exited, 0);
1650 #else
1651 static void rtl8139_timer(unsigned long arg)
1653 struct net_device *dev = (struct net_device *)arg;
1654 struct rtl8139_private *tp = dev->priv;
1655 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1656 mod_timer(&tp->timer, jiffies + next_tick);
1658 #endif
1661 static void rtl8139_tx_clear (struct rtl8139_private *tp)
1663 tp->cur_tx = 0;
1664 tp->dirty_tx = 0;
1666 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1670 static void rtl8139_tx_timeout (struct net_device *dev)
1672 struct rtl8139_private *tp = dev->priv;
1673 void *ioaddr = tp->mmio_addr;
1674 int i;
1675 u8 tmp8;
1676 unsigned long flags;
1678 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1679 "media %2.2x.\n", dev->name,
1680 RTL_R8 (ChipCmd),
1681 RTL_R16 (IntrStatus),
1682 RTL_R8 (MediaStatus));
1684 tp->xstats.tx_timeouts++;
1686 /* disable Tx ASAP, if not already */
1687 tmp8 = RTL_R8 (ChipCmd);
1688 if (tmp8 & CmdTxEnb)
1689 RTL_W8 (ChipCmd, CmdRxEnb);
1691 /* Disable interrupts by clearing the interrupt mask. */
1692 RTL_W16 (IntrMask, 0x0000);
1694 /* Emit info to figure out what went wrong. */
1695 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1696 dev->name, tp->cur_tx, tp->dirty_tx);
1697 for (i = 0; i < NUM_TX_DESC; i++)
1698 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1699 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1700 i == tp->dirty_tx % NUM_TX_DESC ?
1701 " (queue head)" : "");
1703 /* Stop a shared interrupt from scavenging while we are. */
1704 spin_lock_irqsave (&tp->lock, flags);
1705 rtl8139_tx_clear (tp);
1706 spin_unlock_irqrestore (&tp->lock, flags);
1708 /* ...and finally, reset everything */
1709 rtl8139_hw_start (dev);
1711 netif_wake_queue (dev);
1715 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1717 struct rtl8139_private *tp = dev->priv;
1718 void *ioaddr = tp->mmio_addr;
1719 unsigned int entry;
1720 unsigned int len = skb->len;
1722 /* Calculate the next Tx descriptor entry. */
1723 entry = tp->cur_tx % NUM_TX_DESC;
1725 if (likely(len < TX_BUF_SIZE)) {
1726 if(len < ETH_ZLEN)
1727 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1728 #if 0
1729 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1730 #else
1731 skb_copy_bits(skb, 0, tp->tx_buf[entry], skb->len);
1732 #endif
1733 dev_kfree_skb(skb);
1734 } else {
1735 dev_kfree_skb(skb);
1736 tp->stats.tx_dropped++;
1737 return 0;
1740 /* Note: the chip doesn't have auto-pad! */
1741 spin_lock_irq(&tp->lock);
1742 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1743 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1745 dev->trans_start = jiffies;
1747 tp->cur_tx++;
1748 wmb();
1750 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1751 netif_stop_queue (dev);
1752 spin_unlock_irq(&tp->lock);
1754 DPRINTK ("%s: Queued Tx packet size %u to slot %d.\n",
1755 dev->name, len, entry);
1757 return 0;
1761 static void rtl8139_tx_interrupt (struct net_device *dev,
1762 struct rtl8139_private *tp,
1763 void *ioaddr)
1765 unsigned long dirty_tx, tx_left;
1767 assert (dev != NULL);
1768 assert (tp != NULL);
1769 assert (ioaddr != NULL);
1771 dirty_tx = tp->dirty_tx;
1772 tx_left = tp->cur_tx - dirty_tx;
1773 while (tx_left > 0) {
1774 int entry = dirty_tx % NUM_TX_DESC;
1775 int txstatus;
1777 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1779 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1780 break; /* It still hasn't been Txed */
1782 /* Note: TxCarrierLost is always asserted at 100mbps. */
1783 if (txstatus & (TxOutOfWindow | TxAborted)) {
1784 /* There was an major error, log it. */
1785 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1786 dev->name, txstatus);
1787 tp->stats.tx_errors++;
1788 if (txstatus & TxAborted) {
1789 tp->stats.tx_aborted_errors++;
1790 RTL_W32 (TxConfig, TxClearAbt);
1791 RTL_W16 (IntrStatus, TxErr);
1792 wmb();
1794 if (txstatus & TxCarrierLost)
1795 tp->stats.tx_carrier_errors++;
1796 if (txstatus & TxOutOfWindow)
1797 tp->stats.tx_window_errors++;
1798 } else {
1799 if (txstatus & TxUnderrun) {
1800 /* Add 64 to the Tx FIFO threshold. */
1801 if (tp->tx_flag < 0x00300000)
1802 tp->tx_flag += 0x00020000;
1803 tp->stats.tx_fifo_errors++;
1805 tp->stats.collisions += (txstatus >> 24) & 15;
1806 tp->stats.tx_bytes += txstatus & 0x7ff;
1807 tp->stats.tx_packets++;
1810 dirty_tx++;
1811 tx_left--;
1814 #ifndef RTL8139_NDEBUG
1815 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1816 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1817 dev->name, dirty_tx, tp->cur_tx);
1818 dirty_tx += NUM_TX_DESC;
1820 #endif /* RTL8139_NDEBUG */
1822 /* only wake the queue if we did work, and the queue is stopped */
1823 if (tp->dirty_tx != dirty_tx) {
1824 tp->dirty_tx = dirty_tx;
1825 mb();
1826 if (netif_queue_stopped (dev))
1827 netif_wake_queue (dev);
1832 /* TODO: clean this up! Rx reset need not be this intensive */
1833 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1834 struct rtl8139_private *tp, void *ioaddr)
1836 u8 tmp8;
1837 #ifdef CONFIG_8139_OLD_RX_RESET
1838 int tmp_work;
1839 #endif
1841 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1842 dev->name, rx_status);
1843 tp->stats.rx_errors++;
1844 if (!(rx_status & RxStatusOK)) {
1845 if (rx_status & RxTooLong) {
1846 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1847 dev->name, rx_status);
1848 /* A.C.: The chip hangs here. */
1850 if (rx_status & (RxBadSymbol | RxBadAlign))
1851 tp->stats.rx_frame_errors++;
1852 if (rx_status & (RxRunt | RxTooLong))
1853 tp->stats.rx_length_errors++;
1854 if (rx_status & RxCRCErr)
1855 tp->stats.rx_crc_errors++;
1856 } else {
1857 tp->xstats.rx_lost_in_ring++;
1860 #ifndef CONFIG_8139_OLD_RX_RESET
1861 tmp8 = RTL_R8 (ChipCmd);
1862 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1863 RTL_W8 (ChipCmd, tmp8);
1864 RTL_W32 (RxConfig, tp->rx_config);
1865 tp->cur_rx = 0;
1866 #else
1867 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1869 /* disable receive */
1870 RTL_W8_F (ChipCmd, CmdTxEnb);
1871 tmp_work = 200;
1872 while (--tmp_work > 0) {
1873 udelay(1);
1874 tmp8 = RTL_R8 (ChipCmd);
1875 if (!(tmp8 & CmdRxEnb))
1876 break;
1878 if (tmp_work <= 0)
1879 printk (KERN_WARNING PFX "rx stop wait too long\n");
1880 /* restart receive */
1881 tmp_work = 200;
1882 while (--tmp_work > 0) {
1883 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1884 udelay(1);
1885 tmp8 = RTL_R8 (ChipCmd);
1886 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1887 break;
1889 if (tmp_work <= 0)
1890 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1892 /* and reinitialize all rx related registers */
1893 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1894 /* Must enable Tx/Rx before setting transfer thresholds! */
1895 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1897 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1898 RTL_W32 (RxConfig, tp->rx_config);
1899 tp->cur_rx = 0;
1901 DPRINTK("init buffer addresses\n");
1903 /* Lock Config[01234] and BMCR register writes */
1904 RTL_W8 (Cfg9346, Cfg9346_Lock);
1906 /* init Rx ring buffer DMA address */
1907 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1909 /* A.C.: Reset the multicast list. */
1910 __set_rx_mode (dev);
1911 #endif
1914 static void rtl8139_rx_interrupt (struct net_device *dev,
1915 struct rtl8139_private *tp, void *ioaddr)
1917 unsigned char *rx_ring;
1918 u16 cur_rx;
1920 assert (dev != NULL);
1921 assert (tp != NULL);
1922 assert (ioaddr != NULL);
1924 rx_ring = tp->rx_ring;
1925 cur_rx = tp->cur_rx;
1927 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1928 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1929 RTL_R16 (RxBufAddr),
1930 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1932 while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1933 int ring_offset = cur_rx % RX_BUF_LEN;
1934 u32 rx_status;
1935 unsigned int rx_size;
1936 unsigned int pkt_size;
1937 struct sk_buff *skb;
1939 rmb();
1941 /* read size+status of next frame from DMA ring buffer */
1942 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1943 rx_size = rx_status >> 16;
1944 pkt_size = rx_size - 4;
1946 DPRINTK ("%s: rtl8139_rx() status %4.4x, size %4.4x,"
1947 " cur %4.4x.\n", dev->name, rx_status,
1948 rx_size, cur_rx);
1949 #if RTL8139_DEBUG > 2
1951 int i;
1952 DPRINTK ("%s: Frame contents ", dev->name);
1953 for (i = 0; i < 70; i++)
1954 printk (" %2.2x",
1955 rx_ring[ring_offset + i]);
1956 printk (".\n");
1958 #endif
1960 /* Packet copy from FIFO still in progress.
1961 * Theoretically, this should never happen
1962 * since EarlyRx is disabled.
1963 */
1964 if (rx_size == 0xfff0) {
1965 tp->xstats.early_rx++;
1966 break;
1969 /* If Rx err or invalid rx_size/rx_status received
1970 * (which happens if we get lost in the ring),
1971 * Rx process gets reset, so we abort any further
1972 * Rx processing.
1973 */
1974 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1975 (rx_size < 8) ||
1976 (!(rx_status & RxStatusOK))) {
1977 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1978 return;
1981 /* Malloc up new buffer, compatible with net-2e. */
1982 /* Omit the four octet CRC from the length. */
1984 /* TODO: consider allocating skb's outside of
1985 * interrupt context, both to speed interrupt processing,
1986 * and also to reduce the chances of having to
1987 * drop packets here under memory pressure.
1988 */
1990 skb = dev_alloc_skb (pkt_size + 2);
1991 if (skb) {
1992 skb->dev = dev;
1993 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1995 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1996 skb_put (skb, pkt_size);
1998 skb->protocol = eth_type_trans (skb, dev);
1999 netif_rx (skb);
2000 dev->last_rx = jiffies;
2001 tp->stats.rx_bytes += pkt_size;
2002 tp->stats.rx_packets++;
2003 } else {
2004 printk (KERN_WARNING
2005 "%s: Memory squeeze, dropping packet.\n",
2006 dev->name);
2007 tp->stats.rx_dropped++;
2010 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2011 RTL_W16 (RxBufPtr, cur_rx - 16);
2013 if (RTL_R16 (IntrStatus) & RxAckBits)
2014 RTL_W16_F (IntrStatus, RxAckBits);
2017 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2018 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2019 RTL_R16 (RxBufAddr),
2020 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2022 tp->cur_rx = cur_rx;
2026 static void rtl8139_weird_interrupt (struct net_device *dev,
2027 struct rtl8139_private *tp,
2028 void *ioaddr,
2029 int status, int link_changed)
2031 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2032 dev->name, status);
2034 assert (dev != NULL);
2035 assert (tp != NULL);
2036 assert (ioaddr != NULL);
2038 /* Update the error count. */
2039 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2040 RTL_W32 (RxMissed, 0);
2042 if ((status & RxUnderrun) && link_changed &&
2043 (tp->drv_flags & HAS_LNK_CHNG)) {
2044 /* Really link-change on new chips. */
2045 int lpar = RTL_R16 (NWayLPAR);
2046 int duplex = (lpar & LPA_100FULL) || (lpar & 0x01C0) == 0x0040
2047 || tp->mii.force_media;
2048 if (tp->mii.full_duplex != duplex) {
2049 tp->mii.full_duplex = duplex;
2050 #if 0
2051 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2052 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
2053 RTL_W8 (Cfg9346, Cfg9346_Lock);
2054 #endif
2056 status &= ~RxUnderrun;
2059 /* XXX along with rtl8139_rx_err, are we double-counting errors? */
2060 if (status &
2061 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
2062 tp->stats.rx_errors++;
2064 if (status & PCSTimeout)
2065 tp->stats.rx_length_errors++;
2066 if (status & (RxUnderrun | RxFIFOOver))
2067 tp->stats.rx_fifo_errors++;
2068 if (status & PCIErr) {
2069 u16 pci_cmd_status;
2070 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2071 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2073 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2074 dev->name, pci_cmd_status);
2079 /* The interrupt handler does all of the Rx thread work and cleans up
2080 after the Tx thread. */
2081 static void rtl8139_interrupt (int irq, void *dev_instance,
2082 struct pt_regs *regs)
2084 struct net_device *dev = (struct net_device *) dev_instance;
2085 struct rtl8139_private *tp = dev->priv;
2086 int boguscnt = max_interrupt_work;
2087 void *ioaddr = tp->mmio_addr;
2088 int ackstat, status;
2089 int link_changed = 0; /* avoid bogus "uninit" warning */
2091 spin_lock (&tp->lock);
2093 do {
2094 status = RTL_R16 (IntrStatus);
2096 /* h/w no longer present (hotplug?) or major error, bail */
2097 if (status == 0xFFFF)
2098 break;
2100 if ((status &
2101 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2102 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
2103 break;
2105 /* Acknowledge all of the current interrupt sources ASAP, but
2106 an first get an additional status bit from CSCR. */
2107 if (status & RxUnderrun)
2108 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2110 /* The chip takes special action when we clear RxAckBits,
2111 * so we clear them later in rtl8139_rx_interrupt
2112 */
2113 ackstat = status & ~(RxAckBits | TxErr);
2114 RTL_W16 (IntrStatus, ackstat);
2116 DPRINTK ("%s: interrupt status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
2117 dev->name, ackstat, status, RTL_R16 (IntrStatus));
2119 if (netif_running (dev) && (status & RxAckBits))
2120 rtl8139_rx_interrupt (dev, tp, ioaddr);
2122 /* Check uncommon events with one test. */
2123 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
2124 RxFIFOOver | RxErr))
2125 rtl8139_weird_interrupt (dev, tp, ioaddr,
2126 status, link_changed);
2128 if (netif_running (dev) && (status & (TxOK | TxErr))) {
2129 rtl8139_tx_interrupt (dev, tp, ioaddr);
2130 if (status & TxErr)
2131 RTL_W16 (IntrStatus, TxErr);
2134 boguscnt--;
2135 } while (boguscnt > 0);
2137 if (boguscnt <= 0) {
2138 printk (KERN_WARNING "%s: Too much work at interrupt, "
2139 "IntrStatus=0x%4.4x.\n", dev->name, status);
2141 /* Clear all interrupt sources. */
2142 RTL_W16 (IntrStatus, 0xffff);
2145 spin_unlock (&tp->lock);
2147 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2148 dev->name, RTL_R16 (IntrStatus));
2152 static int rtl8139_close (struct net_device *dev)
2154 struct rtl8139_private *tp = dev->priv;
2155 void *ioaddr = tp->mmio_addr;
2156 #if 0
2157 int ret = 0;
2158 #endif
2159 unsigned long flags;
2161 netif_stop_queue (dev);
2163 #if 0
2164 if (tp->thr_pid >= 0) {
2165 tp->time_to_die = 1;
2166 wmb();
2167 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2168 if (ret) {
2169 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2170 return ret;
2172 wait_for_completion (&tp->thr_exited);
2174 #else
2175 del_timer_sync(&tp->timer);
2176 #endif
2178 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
2179 dev->name, RTL_R16 (IntrStatus));
2181 spin_lock_irqsave (&tp->lock, flags);
2183 /* Stop the chip's Tx and Rx DMA processes. */
2184 RTL_W8 (ChipCmd, 0);
2186 /* Disable interrupts by clearing the interrupt mask. */
2187 RTL_W16 (IntrMask, 0);
2189 /* Update the error counts. */
2190 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2191 RTL_W32 (RxMissed, 0);
2193 spin_unlock_irqrestore (&tp->lock, flags);
2195 synchronize_irq ();
2196 free_irq (dev->irq, dev);
2198 rtl8139_tx_clear (tp);
2200 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2201 tp->rx_ring, tp->rx_ring_dma);
2202 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2203 tp->tx_bufs, tp->tx_bufs_dma);
2204 tp->rx_ring = NULL;
2205 tp->tx_bufs = NULL;
2207 /* Green! Put the chip in low-power mode. */
2208 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2210 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2211 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2213 return 0;
2217 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2218 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2219 other threads or interrupts aren't messing with the 8139. */
2220 static void netdev_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
2222 struct rtl8139_private *np = dev->priv;
2223 void *ioaddr = np->mmio_addr;
2225 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2226 u8 cfg3 = RTL_R8 (Config3);
2227 u8 cfg5 = RTL_R8 (Config5);
2229 wol->supported = WAKE_PHY | WAKE_MAGIC
2230 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2232 wol->wolopts = 0;
2233 if (cfg3 & Cfg3_LinkUp)
2234 wol->wolopts |= WAKE_PHY;
2235 if (cfg3 & Cfg3_Magic)
2236 wol->wolopts |= WAKE_MAGIC;
2237 /* (KON)FIXME: See how netdev_set_wol() handles the
2238 following constants. */
2239 if (cfg5 & Cfg5_UWF)
2240 wol->wolopts |= WAKE_UCAST;
2241 if (cfg5 & Cfg5_MWF)
2242 wol->wolopts |= WAKE_MCAST;
2243 if (cfg5 & Cfg5_BWF)
2244 wol->wolopts |= WAKE_BCAST;
2249 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2250 that wol points to kernel memory and other threads or interrupts
2251 aren't messing with the 8139. */
2252 static int netdev_set_wol (struct net_device *dev,
2253 const struct ethtool_wolinfo *wol)
2255 struct rtl8139_private *np = dev->priv;
2256 void *ioaddr = np->mmio_addr;
2257 u32 support;
2258 u8 cfg3, cfg5;
2260 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2261 ? (WAKE_PHY | WAKE_MAGIC
2262 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2263 : 0);
2264 if (wol->wolopts & ~support)
2265 return -EINVAL;
2267 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2268 if (wol->wolopts & WAKE_PHY)
2269 cfg3 |= Cfg3_LinkUp;
2270 if (wol->wolopts & WAKE_MAGIC)
2271 cfg3 |= Cfg3_Magic;
2272 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2273 RTL_W8 (Config3, cfg3);
2274 RTL_W8 (Cfg9346, Cfg9346_Lock);
2276 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2277 /* (KON)FIXME: These are untested. We may have to set the
2278 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2279 documentation. */
2280 if (wol->wolopts & WAKE_UCAST)
2281 cfg5 |= Cfg5_UWF;
2282 if (wol->wolopts & WAKE_MCAST)
2283 cfg5 |= Cfg5_MWF;
2284 if (wol->wolopts & WAKE_BCAST)
2285 cfg5 |= Cfg5_BWF;
2286 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2288 return 0;
2291 #if 0
2292 static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
2294 struct rtl8139_private *np = dev->priv;
2295 u32 ethcmd;
2297 /* dev_ioctl() in ../../net/core/dev.c has already checked
2298 capable(CAP_NET_ADMIN), so don't bother with that here. */
2300 if (get_user(ethcmd, (u32 *)useraddr))
2301 return -EFAULT;
2303 switch (ethcmd) {
2305 case ETHTOOL_GDRVINFO: {
2306 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
2307 strcpy (info.driver, DRV_NAME);
2308 strcpy (info.version, DRV_VERSION);
2309 strcpy (info.bus_info, np->pci_dev->slot_name);
2310 info.regdump_len = np->regs_len;
2311 if (copy_to_user (useraddr, &info, sizeof (info)))
2312 return -EFAULT;
2313 return 0;
2316 /* get settings */
2317 case ETHTOOL_GSET: {
2318 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
2319 spin_lock_irq(&np->lock);
2320 mii_ethtool_gset(&np->mii, &ecmd);
2321 spin_unlock_irq(&np->lock);
2322 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
2323 return -EFAULT;
2324 return 0;
2326 /* set settings */
2327 case ETHTOOL_SSET: {
2328 int r;
2329 struct ethtool_cmd ecmd;
2330 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
2331 return -EFAULT;
2332 spin_lock_irq(&np->lock);
2333 r = mii_ethtool_sset(&np->mii, &ecmd);
2334 spin_unlock_irq(&np->lock);
2335 return r;
2337 /* restart autonegotiation */
2338 case ETHTOOL_NWAY_RST: {
2339 return mii_nway_restart(&np->mii);
2341 /* get link status */
2342 case ETHTOOL_GLINK: {
2343 struct ethtool_value edata = {ETHTOOL_GLINK};
2344 edata.data = mii_link_ok(&np->mii);
2345 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2346 return -EFAULT;
2347 return 0;
2350 /* get message-level */
2351 case ETHTOOL_GMSGLVL: {
2352 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
2353 edata.data = debug;
2354 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2355 return -EFAULT;
2356 return 0;
2358 /* set message-level */
2359 case ETHTOOL_SMSGLVL: {
2360 struct ethtool_value edata;
2361 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2362 return -EFAULT;
2363 debug = edata.data;
2364 return 0;
2367 case ETHTOOL_GWOL:
2369 struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
2370 spin_lock_irq (&np->lock);
2371 netdev_get_wol (dev, &wol);
2372 spin_unlock_irq (&np->lock);
2373 if (copy_to_user (useraddr, &wol, sizeof (wol)))
2374 return -EFAULT;
2375 return 0;
2378 case ETHTOOL_SWOL:
2380 struct ethtool_wolinfo wol;
2381 int rc;
2382 if (copy_from_user (&wol, useraddr, sizeof (wol)))
2383 return -EFAULT;
2384 spin_lock_irq (&np->lock);
2385 rc = netdev_set_wol (dev, &wol);
2386 spin_unlock_irq (&np->lock);
2387 return rc;
2390 /* TODO: we are too slack to do reg dumping for pio, for now */
2391 #ifndef CONFIG_8139TOO_PIO
2392 /* NIC register dump */
2393 case ETHTOOL_GREGS: {
2394 struct ethtool_regs regs;
2395 unsigned int regs_len = np->regs_len;
2396 u8 *regbuf = kmalloc(regs_len, GFP_KERNEL);
2397 int rc;
2399 if (!regbuf)
2400 return -ENOMEM;
2401 memset(regbuf, 0, regs_len);
2403 rc = copy_from_user(&regs, useraddr, sizeof(regs));
2404 if (rc) {
2405 rc = -EFAULT;
2406 goto err_out_gregs;
2409 if (regs.len > regs_len)
2410 regs.len = regs_len;
2411 if (regs.len < regs_len) {
2412 rc = -EINVAL;
2413 goto err_out_gregs;
2416 regs.version = RTL_REGS_VER;
2417 rc = copy_to_user(useraddr, &regs, sizeof(regs));
2418 if (rc) {
2419 rc = -EFAULT;
2420 goto err_out_gregs;
2423 useraddr += offsetof(struct ethtool_regs, data);
2425 spin_lock_irq(&np->lock);
2426 memcpy_fromio(regbuf, np->mmio_addr, regs_len);
2427 spin_unlock_irq(&np->lock);
2429 if (copy_to_user(useraddr, regbuf, regs_len))
2430 rc = -EFAULT;
2432 err_out_gregs:
2433 kfree(regbuf);
2434 return rc;
2436 #endif /* CONFIG_8139TOO_PIO */
2438 /* get string list(s) */
2439 case ETHTOOL_GSTRINGS: {
2440 struct ethtool_gstrings estr = { ETHTOOL_GSTRINGS };
2442 if (copy_from_user(&estr, useraddr, sizeof(estr)))
2443 return -EFAULT;
2444 if (estr.string_set != ETH_SS_STATS)
2445 return -EINVAL;
2447 estr.len = RTL_NUM_STATS;
2448 if (copy_to_user(useraddr, &estr, sizeof(estr)))
2449 return -EFAULT;
2450 if (copy_to_user(useraddr + sizeof(estr),
2451 &ethtool_stats_keys,
2452 sizeof(ethtool_stats_keys)))
2453 return -EFAULT;
2454 return 0;
2457 /* get NIC-specific statistics */
2458 case ETHTOOL_GSTATS: {
2459 struct ethtool_stats estats = { ETHTOOL_GSTATS };
2460 u64 *tmp_stats;
2461 const unsigned int sz = sizeof(u64) * RTL_NUM_STATS;
2462 int i;
2464 estats.n_stats = RTL_NUM_STATS;
2465 if (copy_to_user(useraddr, &estats, sizeof(estats)))
2466 return -EFAULT;
2468 tmp_stats = kmalloc(sz, GFP_KERNEL);
2469 if (!tmp_stats)
2470 return -ENOMEM;
2471 memset(tmp_stats, 0, sz);
2473 i = 0;
2474 tmp_stats[i++] = np->xstats.early_rx;
2475 tmp_stats[i++] = np->xstats.tx_buf_mapped;
2476 tmp_stats[i++] = np->xstats.tx_timeouts;
2477 tmp_stats[i++] = np->xstats.rx_lost_in_ring;
2478 if (i != RTL_NUM_STATS)
2479 BUG();
2481 i = copy_to_user(useraddr + sizeof(estats), tmp_stats, sz);
2482 kfree(tmp_stats);
2484 if (i)
2485 return -EFAULT;
2486 return 0;
2488 default:
2489 break;
2492 return -EOPNOTSUPP;
2496 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2498 struct rtl8139_private *np = dev->priv;
2499 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
2500 int rc;
2502 if (!netif_running(dev))
2503 return -EINVAL;
2505 if (cmd == SIOCETHTOOL)
2506 rc = netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
2508 else {
2509 spin_lock_irq(&np->lock);
2510 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
2511 spin_unlock_irq(&np->lock);
2514 return rc;
2516 #endif
2519 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2521 struct rtl8139_private *tp = dev->priv;
2522 void *ioaddr = tp->mmio_addr;
2523 unsigned long flags;
2525 if (netif_running(dev)) {
2526 spin_lock_irqsave (&tp->lock, flags);
2527 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2528 RTL_W32 (RxMissed, 0);
2529 spin_unlock_irqrestore (&tp->lock, flags);
2532 return &tp->stats;
2535 /* Set or clear the multicast filter for this adaptor.
2536 This routine is not state sensitive and need not be SMP locked. */
2538 static void __set_rx_mode (struct net_device *dev)
2540 struct rtl8139_private *tp = dev->priv;
2541 void *ioaddr = tp->mmio_addr;
2542 u32 mc_filter[2]; /* Multicast hash filter */
2543 int i, rx_mode;
2544 u32 tmp;
2546 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2547 dev->name, dev->flags, RTL_R32 (RxConfig));
2549 /* Note: do not reorder, GCC is clever about common statements. */
2550 if (dev->flags & IFF_PROMISC) {
2551 /* Unconditionally log net taps. */
2552 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2553 dev->name);
2554 rx_mode =
2555 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2556 AcceptAllPhys;
2557 mc_filter[1] = mc_filter[0] = 0xffffffff;
2558 } else if ((dev->mc_count > multicast_filter_limit)
2559 || (dev->flags & IFF_ALLMULTI)) {
2560 /* Too many to filter perfectly -- accept all multicasts. */
2561 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2562 mc_filter[1] = mc_filter[0] = 0xffffffff;
2563 } else {
2564 struct dev_mc_list *mclist;
2565 rx_mode = AcceptBroadcast | AcceptMyPhys;
2566 mc_filter[1] = mc_filter[0] = 0;
2567 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2568 i++, mclist = mclist->next) {
2569 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2571 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2572 rx_mode |= AcceptMulticast;
2576 /* We can safely update without stopping the chip. */
2577 tmp = rtl8139_rx_config | rx_mode;
2578 if (tp->rx_config != tmp) {
2579 RTL_W32_F (RxConfig, tmp);
2580 tp->rx_config = tmp;
2582 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2583 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2586 static void rtl8139_set_rx_mode (struct net_device *dev)
2588 unsigned long flags;
2589 struct rtl8139_private *tp = dev->priv;
2591 spin_lock_irqsave (&tp->lock, flags);
2592 __set_rx_mode(dev);
2593 spin_unlock_irqrestore (&tp->lock, flags);
2596 #ifdef CONFIG_PM
2598 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2600 struct net_device *dev = pci_get_drvdata (pdev);
2601 struct rtl8139_private *tp = dev->priv;
2602 void *ioaddr = tp->mmio_addr;
2603 unsigned long flags;
2605 if (!netif_running (dev))
2606 return 0;
2608 netif_device_detach (dev);
2610 spin_lock_irqsave (&tp->lock, flags);
2612 /* Disable interrupts, stop Tx and Rx. */
2613 RTL_W16 (IntrMask, 0);
2614 RTL_W8 (ChipCmd, 0);
2616 /* Update the error counts. */
2617 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2618 RTL_W32 (RxMissed, 0);
2620 spin_unlock_irqrestore (&tp->lock, flags);
2621 return 0;
2625 static int rtl8139_resume (struct pci_dev *pdev)
2627 struct net_device *dev = pci_get_drvdata (pdev);
2629 if (!netif_running (dev))
2630 return 0;
2631 netif_device_attach (dev);
2632 rtl8139_hw_start (dev);
2633 return 0;
2636 #endif /* CONFIG_PM */
2639 static struct pci_driver rtl8139_pci_driver = {
2640 .name = DRV_NAME,
2641 .id_table = rtl8139_pci_tbl,
2642 .probe = rtl8139_init_one,
2643 .remove = __devexit_p(rtl8139_remove_one),
2644 #ifdef CONFIG_PM
2645 .suspend = rtl8139_suspend,
2646 .resume = rtl8139_resume,
2647 #endif /* CONFIG_PM */
2648 };
2651 static int __init rtl8139_init_module (void)
2653 /* when we're a module, we always print a version message,
2654 * even if no 8139 board is found.
2655 */
2656 #ifdef MODULE
2657 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2658 #endif
2660 return pci_module_init (&rtl8139_pci_driver);
2664 static void __exit rtl8139_cleanup_module (void)
2666 pci_unregister_driver (&rtl8139_pci_driver);
2670 module_init(rtl8139_init_module);
2671 module_exit(rtl8139_cleanup_module);