debuggers.hg

view xen/drivers/net/pcnet32.c @ 618:4480b471191c

bitkeeper revision 1.259.2.7 (3f0c428fGYxQAV_56B2hOOjYs1PF0A)

Port a bunch of network drivers for low-quality NICS (which will incur extra copying overheads within Xen). But will allow us to work on a wider range of systems at least.
author kaf24@scramble.cl.cam.ac.uk
date Wed Jul 09 16:27:59 2003 +0000 (2003-07-09)
parents
children 125f43340354
line source
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.27a"
26 #define DRV_RELDATE "10.02.2002"
27 #define PFX DRV_NAME ": "
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/sched.h>
36 #include <linux/string.h>
37 #include <linux/errno.h>
38 #include <linux/ioport.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <linux/init.h>
44 #include <linux/ethtool.h>
45 #include <linux/mii.h>
46 #include <linux/crc32.h>
47 #include <asm/bitops.h>
48 #include <asm/io.h>
49 #include <asm/dma.h>
50 #include <asm/uaccess.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/skbuff.h>
55 #include <linux/spinlock.h>
57 #undef TX_RING_SIZE
58 #undef RX_RING_SIZE
60 /*
61 * PCI device identifiers for "new style" Linux PCI Device Drivers
62 */
63 static struct pci_device_id pcnet32_pci_tbl[] __devinitdata = {
64 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
65 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
66 { 0, }
67 };
69 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
71 int cards_found __initdata;
73 /*
74 * VLB I/O addresses
75 */
76 static unsigned int pcnet32_portlist[] __initdata =
77 { 0x300, 0x320, 0x340, 0x360, 0 };
81 static int pcnet32_debug = 1;
82 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
83 static int pcnet32vlb; /* check for VLB cards ? */
85 static struct net_device *pcnet32_dev;
87 static int max_interrupt_work = 80;
88 static int rx_copybreak = 200;
90 #define PCNET32_PORT_AUI 0x00
91 #define PCNET32_PORT_10BT 0x01
92 #define PCNET32_PORT_GPSI 0x02
93 #define PCNET32_PORT_MII 0x03
95 #define PCNET32_PORT_PORTSEL 0x03
96 #define PCNET32_PORT_ASEL 0x04
97 #define PCNET32_PORT_100 0x40
98 #define PCNET32_PORT_FD 0x80
100 #define PCNET32_DMA_MASK 0xffffffff
102 /*
103 * table to translate option values from tulip
104 * to internal options
105 */
106 static unsigned char options_mapping[] = {
107 PCNET32_PORT_ASEL, /* 0 Auto-select */
108 PCNET32_PORT_AUI, /* 1 BNC/AUI */
109 PCNET32_PORT_AUI, /* 2 AUI/BNC */
110 PCNET32_PORT_ASEL, /* 3 not supported */
111 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
112 PCNET32_PORT_ASEL, /* 5 not supported */
113 PCNET32_PORT_ASEL, /* 6 not supported */
114 PCNET32_PORT_ASEL, /* 7 not supported */
115 PCNET32_PORT_ASEL, /* 8 not supported */
116 PCNET32_PORT_MII, /* 9 MII 10baseT */
117 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
118 PCNET32_PORT_MII, /* 11 MII (autosel) */
119 PCNET32_PORT_10BT, /* 12 10BaseT */
120 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
121 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
122 PCNET32_PORT_ASEL /* 15 not supported */
123 };
125 #define MAX_UNITS 8 /* More are supported, limit only on options */
126 static int options[MAX_UNITS];
127 static int full_duplex[MAX_UNITS];
129 /*
130 * Theory of Operation
131 *
132 * This driver uses the same software structure as the normal lance
133 * driver. So look for a verbose description in lance.c. The differences
134 * to the normal lance driver is the use of the 32bit mode of PCnet32
135 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
136 * 16MB limitation and we don't need bounce buffers.
137 */
139 /*
140 * History:
141 * v0.01: Initial version
142 * only tested on Alpha Noname Board
143 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
144 * tested on a ASUS SP3G
145 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
146 * looks like the 974 doesn't like stopping and restarting in a
147 * short period of time; now we do a reinit of the lance; the
148 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
149 * and hangs the machine (thanks to Klaus Liedl for debugging)
150 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
151 * made it standalone (no need for lance.c)
152 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
153 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
154 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
155 * v0.15: added 79C965 (VLB) probe
156 * added interrupt sharing for PCI chips
157 * v0.16: fixed set_multicast_list on Alpha machines
158 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
159 * v0.19: changed setting of autoselect bit
160 * v0.20: removed additional Compaq PCI probe; there is now a working one
161 * in arch/i386/bios32.c
162 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
163 * v0.22: added printing of status to ring dump
164 * v0.23: changed enet_statistics to net_devive_stats
165 * v0.90: added multicast filter
166 * added module support
167 * changed irq probe to new style
168 * added PCnetFast chip id
169 * added fix for receive stalls with Intel saturn chipsets
170 * added in-place rx skbs like in the tulip driver
171 * minor cleanups
172 * v0.91: added PCnetFast+ chip id
173 * back port to 2.0.x
174 * v1.00: added some stuff from Donald Becker's 2.0.34 version
175 * added support for byte counters in net_dev_stats
176 * v1.01: do ring dumps, only when debugging the driver
177 * increased the transmit timeout
178 * v1.02: fixed memory leak in pcnet32_init_ring()
179 * v1.10: workaround for stopped transmitter
180 * added port selection for modules
181 * detect special T1/E1 WAN card and setup port selection
182 * v1.11: fixed wrong checking of Tx errors
183 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
184 * added save original kmalloc addr for freeing (mcr@solidum.com)
185 * added support for PCnetHome chip (joe@MIT.EDU)
186 * rewritten PCI card detection
187 * added dwio mode to get driver working on some PPC machines
188 * v1.21: added mii selection and mii ioctl
189 * v1.22: changed pci scanning code to make PPC people happy
190 * fixed switching to 32bit mode in pcnet32_open() (thanks
191 * to Michael Richard <mcr@solidum.com> for noticing this one)
192 * added sub vendor/device id matching (thanks again to
193 * Michael Richard <mcr@solidum.com>)
194 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
195 * v1.23 fixed small bug, when manual selecting MII speed/duplex
196 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
197 * underflows. Added tx_start_pt module parameter. Increased
198 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
199 * for FAST[+] chipsets. <kaf@fc.hp.com>
200 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
201 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
202 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
203 * <jamey@crl.dec.com>
204 * - Fixed a few bugs, related to running the controller in 32bit mode.
205 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
206 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
207 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
208 * v1.27 improved CSR/PROM address detection, lots of cleanups,
209 * new pcnet32vlb module option, HP-PARISC support,
210 * added module parameter descriptions,
211 * initial ethtool support - Helge Deller <deller@gmx.de>
212 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
213 * use alloc_etherdev and register_netdev
214 * fix pci probe not increment cards_found
215 * FD auto negotiate error workaround for xSeries250
216 * clean up and using new mii module
217 */
220 /*
221 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
222 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
223 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
224 */
225 #ifndef PCNET32_LOG_TX_BUFFERS
226 #define PCNET32_LOG_TX_BUFFERS 4
227 #define PCNET32_LOG_RX_BUFFERS 5
228 #endif
230 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
231 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
232 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
234 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
235 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
236 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
238 #define PKT_BUF_SZ 1544
240 /* Offsets from base I/O address. */
241 #define PCNET32_WIO_RDP 0x10
242 #define PCNET32_WIO_RAP 0x12
243 #define PCNET32_WIO_RESET 0x14
244 #define PCNET32_WIO_BDP 0x16
246 #define PCNET32_DWIO_RDP 0x10
247 #define PCNET32_DWIO_RAP 0x14
248 #define PCNET32_DWIO_RESET 0x18
249 #define PCNET32_DWIO_BDP 0x1C
251 #define PCNET32_TOTAL_SIZE 0x20
253 /* The PCNET32 Rx and Tx ring descriptors. */
254 struct pcnet32_rx_head {
255 u32 base;
256 s16 buf_length;
257 s16 status;
258 u32 msg_length;
259 u32 reserved;
260 };
262 struct pcnet32_tx_head {
263 u32 base;
264 s16 length;
265 s16 status;
266 u32 misc;
267 u32 reserved;
268 };
270 /* The PCNET32 32-Bit initialization block, described in databook. */
271 struct pcnet32_init_block {
272 u16 mode;
273 u16 tlen_rlen;
274 u8 phys_addr[6];
275 u16 reserved;
276 u32 filter[2];
277 /* Receive and transmit ring base, along with extra bits. */
278 u32 rx_ring;
279 u32 tx_ring;
280 };
282 /* PCnet32 access functions */
283 struct pcnet32_access {
284 u16 (*read_csr)(unsigned long, int);
285 void (*write_csr)(unsigned long, int, u16);
286 u16 (*read_bcr)(unsigned long, int);
287 void (*write_bcr)(unsigned long, int, u16);
288 u16 (*read_rap)(unsigned long);
289 void (*write_rap)(unsigned long, u16);
290 void (*reset)(unsigned long);
291 };
293 /*
294 * The first three fields of pcnet32_private are read by the ethernet device
295 * so we allocate the structure should be allocated by pci_alloc_consistent().
296 */
297 struct pcnet32_private {
298 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
299 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
300 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
301 struct pcnet32_init_block init_block;
302 dma_addr_t dma_addr; /* DMA address of beginning of this object,
303 returned by pci_alloc_consistent */
304 struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */
305 const char *name;
306 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
307 struct sk_buff *tx_skbuff[TX_RING_SIZE];
308 struct sk_buff *rx_skbuff[RX_RING_SIZE];
309 dma_addr_t tx_dma_addr[TX_RING_SIZE];
310 dma_addr_t rx_dma_addr[RX_RING_SIZE];
311 struct pcnet32_access a;
312 spinlock_t lock; /* Guard lock */
313 unsigned int cur_rx, cur_tx; /* The next free ring entry */
314 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
315 struct net_device_stats stats;
316 char tx_full;
317 int options;
318 int shared_irq:1, /* shared irq possible */
319 ltint:1, /* enable TxDone-intr inhibitor */
320 dxsuflo:1, /* disable transmit stop on uflo */
321 mii:1; /* mii port available */
322 struct net_device *next;
323 struct mii_if_info mii_if;
324 };
326 static void pcnet32_probe_vlbus(void);
327 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
328 static int pcnet32_probe1(unsigned long, unsigned int, int, struct pci_dev *);
329 static int pcnet32_open(struct net_device *);
330 static int pcnet32_init_ring(struct net_device *);
331 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
332 static int pcnet32_rx(struct net_device *);
333 static void pcnet32_tx_timeout (struct net_device *dev);
334 static void pcnet32_interrupt(int, void *, struct pt_regs *);
335 static int pcnet32_close(struct net_device *);
336 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
337 static void pcnet32_set_multicast_list(struct net_device *);
338 #if 0
339 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
340 #endif
341 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
342 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
344 enum pci_flags_bit {
345 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
346 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
347 };
350 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
351 {
352 outw (index, addr+PCNET32_WIO_RAP);
353 return inw (addr+PCNET32_WIO_RDP);
354 }
356 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
357 {
358 outw (index, addr+PCNET32_WIO_RAP);
359 outw (val, addr+PCNET32_WIO_RDP);
360 }
362 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
363 {
364 outw (index, addr+PCNET32_WIO_RAP);
365 return inw (addr+PCNET32_WIO_BDP);
366 }
368 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
369 {
370 outw (index, addr+PCNET32_WIO_RAP);
371 outw (val, addr+PCNET32_WIO_BDP);
372 }
374 static u16 pcnet32_wio_read_rap (unsigned long addr)
375 {
376 return inw (addr+PCNET32_WIO_RAP);
377 }
379 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
380 {
381 outw (val, addr+PCNET32_WIO_RAP);
382 }
384 static void pcnet32_wio_reset (unsigned long addr)
385 {
386 inw (addr+PCNET32_WIO_RESET);
387 }
389 static int pcnet32_wio_check (unsigned long addr)
390 {
391 outw (88, addr+PCNET32_WIO_RAP);
392 return (inw (addr+PCNET32_WIO_RAP) == 88);
393 }
395 static struct pcnet32_access pcnet32_wio = {
396 read_csr: pcnet32_wio_read_csr,
397 write_csr: pcnet32_wio_write_csr,
398 read_bcr: pcnet32_wio_read_bcr,
399 write_bcr: pcnet32_wio_write_bcr,
400 read_rap: pcnet32_wio_read_rap,
401 write_rap: pcnet32_wio_write_rap,
402 reset: pcnet32_wio_reset
403 };
405 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
406 {
407 outl (index, addr+PCNET32_DWIO_RAP);
408 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
409 }
411 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
412 {
413 outl (index, addr+PCNET32_DWIO_RAP);
414 outl (val, addr+PCNET32_DWIO_RDP);
415 }
417 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
418 {
419 outl (index, addr+PCNET32_DWIO_RAP);
420 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
421 }
423 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
424 {
425 outl (index, addr+PCNET32_DWIO_RAP);
426 outl (val, addr+PCNET32_DWIO_BDP);
427 }
429 static u16 pcnet32_dwio_read_rap (unsigned long addr)
430 {
431 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
432 }
434 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
435 {
436 outl (val, addr+PCNET32_DWIO_RAP);
437 }
439 static void pcnet32_dwio_reset (unsigned long addr)
440 {
441 inl (addr+PCNET32_DWIO_RESET);
442 }
444 static int pcnet32_dwio_check (unsigned long addr)
445 {
446 outl (88, addr+PCNET32_DWIO_RAP);
447 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
448 }
450 static struct pcnet32_access pcnet32_dwio = {
451 read_csr: pcnet32_dwio_read_csr,
452 write_csr: pcnet32_dwio_write_csr,
453 read_bcr: pcnet32_dwio_read_bcr,
454 write_bcr: pcnet32_dwio_write_bcr,
455 read_rap: pcnet32_dwio_read_rap,
456 write_rap: pcnet32_dwio_write_rap,
457 reset: pcnet32_dwio_reset
458 };
462 /* only probes for non-PCI devices, the rest are handled by
463 * pci_register_driver via pcnet32_probe_pci */
465 static void __devinit
466 pcnet32_probe_vlbus(void)
467 {
468 unsigned int *port, ioaddr;
470 /* search for PCnet32 VLB cards at known addresses */
471 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
472 if (!check_region(ioaddr, PCNET32_TOTAL_SIZE)) {
473 /* check if there is really a pcnet chip on that ioaddr */
474 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57))
475 pcnet32_probe1(ioaddr, 0, 0, NULL);
476 }
477 }
478 }
481 static int __devinit
482 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
483 {
484 unsigned long ioaddr;
485 int err;
487 err = pci_enable_device(pdev);
488 if (err < 0) {
489 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
490 return err;
491 }
492 pci_set_master(pdev);
494 ioaddr = pci_resource_start (pdev, 0);
495 if (!ioaddr) {
496 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
497 return -ENODEV;
498 }
500 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
501 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
502 return -ENODEV;
503 }
505 return pcnet32_probe1(ioaddr, pdev->irq, 1, pdev);
506 }
509 /* pcnet32_probe1
510 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
511 * pdev will be NULL when called from pcnet32_probe_vlbus.
512 */
513 static int __devinit
514 pcnet32_probe1(unsigned long ioaddr, unsigned int irq_line, int shared,
515 struct pci_dev *pdev)
516 {
517 struct pcnet32_private *lp;
518 dma_addr_t lp_dma_addr;
519 int i, media;
520 int fdx, mii, fset, dxsuflo, ltint;
521 int chip_version;
522 char *chipname;
523 struct net_device *dev;
524 struct pcnet32_access *a = NULL;
525 u8 promaddr[6];
527 /* reset the chip */
528 pcnet32_wio_reset(ioaddr);
530 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
531 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
532 a = &pcnet32_wio;
533 } else {
534 pcnet32_dwio_reset(ioaddr);
535 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
536 a = &pcnet32_dwio;
537 } else
538 return -ENODEV;
539 }
541 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
542 if (pcnet32_debug > 2)
543 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
544 if ((chip_version & 0xfff) != 0x003)
545 return -ENODEV;
547 /* initialize variables */
548 fdx = mii = fset = dxsuflo = ltint = 0;
549 chip_version = (chip_version >> 12) & 0xffff;
551 switch (chip_version) {
552 case 0x2420:
553 chipname = "PCnet/PCI 79C970"; /* PCI */
554 break;
555 case 0x2430:
556 if (shared)
557 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
558 else
559 chipname = "PCnet/32 79C965"; /* 486/VL bus */
560 break;
561 case 0x2621:
562 chipname = "PCnet/PCI II 79C970A"; /* PCI */
563 fdx = 1;
564 break;
565 case 0x2623:
566 chipname = "PCnet/FAST 79C971"; /* PCI */
567 fdx = 1; mii = 1; fset = 1;
568 ltint = 1;
569 break;
570 case 0x2624:
571 chipname = "PCnet/FAST+ 79C972"; /* PCI */
572 fdx = 1; mii = 1; fset = 1;
573 break;
574 case 0x2625:
575 chipname = "PCnet/FAST III 79C973"; /* PCI */
576 fdx = 1; mii = 1;
577 break;
578 case 0x2626:
579 chipname = "PCnet/Home 79C978"; /* PCI */
580 fdx = 1;
581 /*
582 * This is based on specs published at www.amd.com. This section
583 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
584 * mode. The 79C978 can also go into standard ethernet, and there
585 * probably should be some sort of module option to select the
586 * mode by which the card should operate
587 */
588 /* switch to home wiring mode */
589 media = a->read_bcr(ioaddr, 49);
590 #if 0
591 if (pcnet32_debug > 2)
592 printk(KERN_DEBUG PFX "media value %#x.\n", media);
593 media &= ~3;
594 media |= 1;
595 #endif
596 if (pcnet32_debug > 2)
597 printk(KERN_DEBUG PFX "media reset to %#x.\n", media);
598 a->write_bcr(ioaddr, 49, media);
599 break;
600 case 0x2627:
601 chipname = "PCnet/FAST III 79C975"; /* PCI */
602 fdx = 1; mii = 1;
603 break;
604 default:
605 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
606 chip_version);
607 return -ENODEV;
608 }
610 /*
611 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
612 * starting until the packet is loaded. Strike one for reliability, lose
613 * one for latency - although on PCI this isnt a big loss. Older chips
614 * have FIFO's smaller than a packet, so you can't do this.
615 */
617 if(fset)
618 {
619 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0800));
620 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
621 dxsuflo = 1;
622 ltint = 1;
623 }
625 dev = alloc_etherdev(0);
626 if(!dev)
627 return -ENOMEM;
629 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
631 /* In most chips, after a chip reset, the ethernet address is read from the
632 * station address PROM at the base address and programmed into the
633 * "Physical Address Registers" CSR12-14.
634 * As a precautionary measure, we read the PROM values and complain if
635 * they disagree with the CSRs. Either way, we use the CSR values, and
636 * double check that they are valid.
637 */
638 for (i = 0; i < 3; i++) {
639 unsigned int val;
640 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
641 /* There may be endianness issues here. */
642 dev->dev_addr[2*i] = val & 0x0ff;
643 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
644 }
646 /* read PROM address and compare with CSR address */
647 for (i = 0; i < 6; i++)
648 promaddr[i] = inb(ioaddr + i);
650 if( memcmp( promaddr, dev->dev_addr, 6)
651 || !is_valid_ether_addr(dev->dev_addr) ) {
652 #ifndef __powerpc__
653 if( is_valid_ether_addr(promaddr) ){
654 #else
655 if( !is_valid_ether_addr(dev->dev_addr)
656 && is_valid_ether_addr(promaddr)) {
657 #endif
658 printk(" warning: CSR address invalid,\n");
659 printk(KERN_INFO " using instead PROM address of");
660 memcpy(dev->dev_addr, promaddr, 6);
661 }
662 }
664 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
665 if( !is_valid_ether_addr(dev->dev_addr) )
666 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
668 for (i = 0; i < 6; i++)
669 printk(" %2.2x", dev->dev_addr[i] );
671 if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
672 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
673 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
674 switch(i>>10) {
675 case 0: printk(" 20 bytes,"); break;
676 case 1: printk(" 64 bytes,"); break;
677 case 2: printk(" 128 bytes,"); break;
678 case 3: printk("~220 bytes,"); break;
679 }
680 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
681 printk(" BCR18(%x):",i&0xffff);
682 if (i & (1<<5)) printk("BurstWrEn ");
683 if (i & (1<<6)) printk("BurstRdEn ");
684 if (i & (1<<7)) printk("DWordIO ");
685 if (i & (1<<11)) printk("NoUFlow ");
686 i = a->read_bcr(ioaddr, 25);
687 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
688 i = a->read_bcr(ioaddr, 26);
689 printk(" SRAM_BND=0x%04x,",i<<8);
690 i = a->read_bcr(ioaddr, 27);
691 if (i & (1<<14)) printk("LowLatRx");
692 }
694 dev->base_addr = ioaddr;
695 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, chipname) == NULL)
696 return -EBUSY;
698 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
699 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
700 release_region(ioaddr, PCNET32_TOTAL_SIZE);
701 return -ENOMEM;
702 }
704 memset(lp, 0, sizeof(*lp));
705 lp->dma_addr = lp_dma_addr;
706 lp->pci_dev = pdev;
708 spin_lock_init(&lp->lock);
710 dev->priv = lp;
711 lp->name = chipname;
712 lp->shared_irq = shared;
713 lp->mii_if.full_duplex = fdx;
714 lp->dxsuflo = dxsuflo;
715 lp->ltint = ltint;
716 lp->mii = mii;
717 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
718 lp->options = PCNET32_PORT_ASEL;
719 else
720 lp->options = options_mapping[options[cards_found]];
721 lp->mii_if.dev = dev;
722 lp->mii_if.mdio_read = mdio_read;
723 lp->mii_if.mdio_write = mdio_write;
725 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
726 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
727 lp->options |= PCNET32_PORT_FD;
729 if (!a) {
730 printk(KERN_ERR PFX "No access methods\n");
731 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
732 release_region(ioaddr, PCNET32_TOTAL_SIZE);
733 return -ENODEV;
734 }
735 lp->a = *a;
737 /* detect special T1/E1 WAN card by checking for MAC address */
738 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && dev->dev_addr[2] == 0x75)
739 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
741 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
742 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
743 for (i = 0; i < 6; i++)
744 lp->init_block.phys_addr[i] = dev->dev_addr[i];
745 lp->init_block.filter[0] = 0x00000000;
746 lp->init_block.filter[1] = 0x00000000;
747 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
748 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
750 /* switch pcnet32 to 32bit mode */
751 a->write_bcr (ioaddr, 20, 2);
753 a->write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) & 0xffff);
754 a->write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
756 if (irq_line) {
757 dev->irq = irq_line;
758 }
760 if (dev->irq >= 2)
761 printk(" assigned IRQ %d.\n", dev->irq);
762 else {
763 unsigned long irq_mask = probe_irq_on();
765 /*
766 * To auto-IRQ we enable the initialization-done and DMA error
767 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
768 * boards will work.
769 */
770 /* Trigger an initialization just for the interrupt. */
771 a->write_csr (ioaddr, 0, 0x41);
772 mdelay (1);
774 dev->irq = probe_irq_off (irq_mask);
775 if (dev->irq)
776 printk(", probed IRQ %d.\n", dev->irq);
777 else {
778 printk(", failed to detect IRQ line.\n");
779 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
780 release_region(ioaddr, PCNET32_TOTAL_SIZE);
781 return -ENODEV;
782 }
783 }
786 /* The PCNET32-specific entries in the device structure. */
787 dev->open = &pcnet32_open;
788 dev->hard_start_xmit = &pcnet32_start_xmit;
789 dev->stop = &pcnet32_close;
790 dev->get_stats = &pcnet32_get_stats;
791 dev->set_multicast_list = &pcnet32_set_multicast_list;
792 #if 0
793 dev->do_ioctl = &pcnet32_ioctl;
794 #endif
795 dev->tx_timeout = pcnet32_tx_timeout;
796 dev->watchdog_timeo = (5*HZ);
798 lp->next = pcnet32_dev;
799 pcnet32_dev = dev;
801 /* Fill in the generic fields of the device structure. */
802 register_netdev(dev);
803 printk(KERN_INFO "%s: registered as %s\n",dev->name, lp->name);
804 cards_found++;
806 alert_slow_netdevice(dev, "PCnet32/lance");
808 return 0;
809 }
812 static int
813 pcnet32_open(struct net_device *dev)
814 {
815 struct pcnet32_private *lp = dev->priv;
816 unsigned long ioaddr = dev->base_addr;
817 u16 val;
818 int i;
820 if (dev->irq == 0 ||
821 request_irq(dev->irq, &pcnet32_interrupt,
822 lp->shared_irq ? SA_SHIRQ : 0, lp->name, (void *)dev)) {
823 return -EAGAIN;
824 }
826 /* Check for a valid station address */
827 if( !is_valid_ether_addr(dev->dev_addr) )
828 return -EINVAL;
830 /* Reset the PCNET32 */
831 lp->a.reset (ioaddr);
833 /* switch pcnet32 to 32bit mode */
834 lp->a.write_bcr (ioaddr, 20, 2);
836 if (pcnet32_debug > 1)
837 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
838 dev->name, dev->irq,
839 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
840 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
841 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
843 /* set/reset autoselect bit */
844 val = lp->a.read_bcr (ioaddr, 2) & ~2;
845 if (lp->options & PCNET32_PORT_ASEL)
846 val |= 2;
847 lp->a.write_bcr (ioaddr, 2, val);
849 /* handle full duplex setting */
850 if (lp->mii_if.full_duplex) {
851 val = lp->a.read_bcr (ioaddr, 9) & ~3;
852 if (lp->options & PCNET32_PORT_FD) {
853 val |= 1;
854 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
855 val |= 2;
856 } else if (lp->options & PCNET32_PORT_ASEL) {
857 /* workaround of xSeries250, turn on for 79C975 only */
858 i = ((lp->a.read_csr(ioaddr, 88) | (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
859 if (i == 0x2627) val |= 3;
860 }
861 lp->a.write_bcr (ioaddr, 9, val);
862 }
864 /* set/reset GPSI bit in test register */
865 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
866 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
867 val |= 0x10;
868 lp->a.write_csr (ioaddr, 124, val);
870 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
871 val = lp->a.read_bcr (ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
872 if (lp->options & PCNET32_PORT_FD)
873 val |= 0x10;
874 if (lp->options & PCNET32_PORT_100)
875 val |= 0x08;
876 lp->a.write_bcr (ioaddr, 32, val);
877 } else {
878 if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
879 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
880 val |= 0x20;
881 lp->a.write_bcr(ioaddr, 32, val);
882 }
883 }
885 #ifdef DO_DXSUFLO
886 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
887 val = lp->a.read_csr (ioaddr, 3);
888 val |= 0x40;
889 lp->a.write_csr (ioaddr, 3, val);
890 }
891 #endif
893 if (lp->ltint) { /* Enable TxDone-intr inhibitor */
894 val = lp->a.read_csr (ioaddr, 5);
895 val |= (1<<14);
896 lp->a.write_csr (ioaddr, 5, val);
897 }
899 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
900 lp->init_block.filter[0] = 0x00000000;
901 lp->init_block.filter[1] = 0x00000000;
902 if (pcnet32_init_ring(dev))
903 return -ENOMEM;
905 /* Re-initialize the PCNET32, and start it when done. */
906 lp->a.write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) &0xffff);
907 lp->a.write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
909 lp->a.write_csr (ioaddr, 4, 0x0915);
910 lp->a.write_csr (ioaddr, 0, 0x0001);
912 netif_start_queue(dev);
914 i = 0;
915 while (i++ < 100)
916 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
917 break;
918 /*
919 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
920 * reports that doing so triggers a bug in the '974.
921 */
922 lp->a.write_csr (ioaddr, 0, 0x0042);
924 if (pcnet32_debug > 2)
925 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
926 dev->name, i, (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)),
927 lp->a.read_csr(ioaddr, 0));
930 MOD_INC_USE_COUNT;
932 return 0; /* Always succeed */
933 }
935 /*
936 * The LANCE has been halted for one reason or another (busmaster memory
937 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
938 * etc.). Modern LANCE variants always reload their ring-buffer
939 * configuration when restarted, so we must reinitialize our ring
940 * context before restarting. As part of this reinitialization,
941 * find all packets still on the Tx ring and pretend that they had been
942 * sent (in effect, drop the packets on the floor) - the higher-level
943 * protocols will time out and retransmit. It'd be better to shuffle
944 * these skbs to a temp list and then actually re-Tx them after
945 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
946 */
948 static void
949 pcnet32_purge_tx_ring(struct net_device *dev)
950 {
951 struct pcnet32_private *lp = dev->priv;
952 int i;
954 for (i = 0; i < TX_RING_SIZE; i++) {
955 if (lp->tx_skbuff[i]) {
956 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
957 dev_kfree_skb_any(lp->tx_skbuff[i]);
958 lp->tx_skbuff[i] = NULL;
959 lp->tx_dma_addr[i] = 0;
960 }
961 }
962 }
965 /* Initialize the PCNET32 Rx and Tx rings. */
966 static int
967 pcnet32_init_ring(struct net_device *dev)
968 {
969 struct pcnet32_private *lp = dev->priv;
970 int i;
972 lp->tx_full = 0;
973 lp->cur_rx = lp->cur_tx = 0;
974 lp->dirty_rx = lp->dirty_tx = 0;
976 for (i = 0; i < RX_RING_SIZE; i++) {
977 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
978 if (rx_skbuff == NULL) {
979 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
980 /* there is not much, we can do at this point */
981 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",dev->name);
982 return -1;
983 }
984 skb_reserve (rx_skbuff, 2);
985 }
986 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail, rx_skbuff->len, PCI_DMA_FROMDEVICE);
987 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
988 lp->rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
989 lp->rx_ring[i].status = le16_to_cpu(0x8000);
990 }
991 /* The Tx buffer address is filled in as needed, but we do need to clear
992 the upper ownership bit. */
993 for (i = 0; i < TX_RING_SIZE; i++) {
994 lp->tx_ring[i].base = 0;
995 lp->tx_ring[i].status = 0;
996 lp->tx_dma_addr[i] = 0;
997 }
999 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1000 for (i = 0; i < 6; i++)
1001 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1002 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
1003 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
1004 return 0;
1007 static void
1008 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1010 struct pcnet32_private *lp = dev->priv;
1011 unsigned long ioaddr = dev->base_addr;
1012 int i;
1014 pcnet32_purge_tx_ring(dev);
1015 if (pcnet32_init_ring(dev))
1016 return;
1018 /* ReInit Ring */
1019 lp->a.write_csr (ioaddr, 0, 1);
1020 i = 0;
1021 while (i++ < 100)
1022 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1023 break;
1025 lp->a.write_csr (ioaddr, 0, csr0_bits);
1029 static void
1030 pcnet32_tx_timeout (struct net_device *dev)
1032 struct pcnet32_private *lp = dev->priv;
1033 unsigned long ioaddr = dev->base_addr, flags;
1035 spin_lock_irqsave(&lp->lock, flags);
1036 /* Transmitter timeout, serious problems. */
1037 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1038 dev->name, lp->a.read_csr(ioaddr, 0));
1039 lp->a.write_csr (ioaddr, 0, 0x0004);
1040 lp->stats.tx_errors++;
1041 if (pcnet32_debug > 2) {
1042 int i;
1043 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1044 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1045 lp->cur_rx);
1046 for (i = 0 ; i < RX_RING_SIZE; i++)
1047 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1048 lp->rx_ring[i].base, -lp->rx_ring[i].buf_length,
1049 lp->rx_ring[i].msg_length, (unsigned)lp->rx_ring[i].status);
1050 for (i = 0 ; i < TX_RING_SIZE; i++)
1051 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1052 lp->tx_ring[i].base, -lp->tx_ring[i].length,
1053 lp->tx_ring[i].misc, (unsigned)lp->tx_ring[i].status);
1054 printk("\n");
1056 pcnet32_restart(dev, 0x0042);
1058 dev->trans_start = jiffies;
1059 netif_start_queue(dev);
1061 spin_unlock_irqrestore(&lp->lock, flags);
1065 static int
1066 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1068 struct pcnet32_private *lp = dev->priv;
1069 unsigned long ioaddr = dev->base_addr;
1070 u16 status;
1071 int entry;
1072 unsigned long flags;
1074 if (pcnet32_debug > 3) {
1075 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1076 dev->name, lp->a.read_csr(ioaddr, 0));
1079 if (skb_shinfo(skb)->nr_frags != 0)
1080 BUG();
1082 spin_lock_irqsave(&lp->lock, flags);
1084 /* Default status -- will not enable Successful-TxDone
1085 * interrupt when that option is available to us.
1086 */
1087 status = 0x8300;
1088 if ((lp->ltint) &&
1089 ((lp->cur_tx - lp->dirty_tx == TX_RING_SIZE/2) ||
1090 (lp->cur_tx - lp->dirty_tx >= TX_RING_SIZE-2)))
1092 /* Enable Successful-TxDone interrupt if we have
1093 * 1/2 of, or nearly all of, our ring buffer Tx'd
1094 * but not yet cleaned up. Thus, most of the time,
1095 * we will not enable Successful-TxDone interrupts.
1096 */
1097 status = 0x9300;
1100 /* Fill in a Tx ring entry */
1102 /* Mask to ring buffer boundary. */
1103 entry = lp->cur_tx & TX_RING_MOD_MASK;
1105 /* Caution: the write order is important here, set the base address
1106 with the "ownership" bits last. */
1108 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1110 lp->tx_ring[entry].misc = 0x00000000;
1112 lp->tx_skbuff[entry] = skb;
1113 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1114 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1115 lp->tx_ring[entry].status = le16_to_cpu(status);
1117 lp->cur_tx++;
1118 lp->stats.tx_bytes += skb->len;
1120 /* Trigger an immediate send poll. */
1121 lp->a.write_csr (ioaddr, 0, 0x0048);
1123 dev->trans_start = jiffies;
1125 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base == 0)
1126 netif_start_queue(dev);
1127 else {
1128 lp->tx_full = 1;
1129 netif_stop_queue(dev);
1131 spin_unlock_irqrestore(&lp->lock, flags);
1132 return 0;
1135 /* The PCNET32 interrupt handler. */
1136 static void
1137 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1139 struct net_device *dev = dev_id;
1140 struct pcnet32_private *lp;
1141 unsigned long ioaddr;
1142 u16 csr0,rap;
1143 int boguscnt = max_interrupt_work;
1144 int must_restart;
1146 if (!dev) {
1147 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1148 __FUNCTION__, irq);
1149 return;
1152 ioaddr = dev->base_addr;
1153 lp = dev->priv;
1155 spin_lock(&lp->lock);
1157 rap = lp->a.read_rap(ioaddr);
1158 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8600 && --boguscnt >= 0) {
1159 /* Acknowledge all of the current interrupt sources ASAP. */
1160 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1162 must_restart = 0;
1164 if (pcnet32_debug > 5)
1165 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1166 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1168 if (csr0 & 0x0400) /* Rx interrupt */
1169 pcnet32_rx(dev);
1171 if (csr0 & 0x0200) { /* Tx-done interrupt */
1172 unsigned int dirty_tx = lp->dirty_tx;
1174 while (dirty_tx < lp->cur_tx) {
1175 int entry = dirty_tx & TX_RING_MOD_MASK;
1176 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1178 if (status < 0)
1179 break; /* It still hasn't been Txed */
1181 lp->tx_ring[entry].base = 0;
1183 if (status & 0x4000) {
1184 /* There was an major error, log it. */
1185 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1186 lp->stats.tx_errors++;
1187 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1188 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1189 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1190 #ifndef DO_DXSUFLO
1191 if (err_status & 0x40000000) {
1192 lp->stats.tx_fifo_errors++;
1193 /* Ackk! On FIFO errors the Tx unit is turned off! */
1194 /* Remove this verbosity later! */
1195 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1196 dev->name, csr0);
1197 must_restart = 1;
1199 #else
1200 if (err_status & 0x40000000) {
1201 lp->stats.tx_fifo_errors++;
1202 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1203 /* Ackk! On FIFO errors the Tx unit is turned off! */
1204 /* Remove this verbosity later! */
1205 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1206 dev->name, csr0);
1207 must_restart = 1;
1210 #endif
1211 } else {
1212 if (status & 0x1800)
1213 lp->stats.collisions++;
1214 lp->stats.tx_packets++;
1217 /* We must free the original skb */
1218 if (lp->tx_skbuff[entry]) {
1219 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1220 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1221 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1222 lp->tx_skbuff[entry] = 0;
1223 lp->tx_dma_addr[entry] = 0;
1225 dirty_tx++;
1228 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1229 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1230 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1231 dirty_tx += TX_RING_SIZE;
1234 if (lp->tx_full &&
1235 netif_queue_stopped(dev) &&
1236 dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1237 /* The ring is no longer full, clear tbusy. */
1238 lp->tx_full = 0;
1239 netif_wake_queue (dev);
1241 lp->dirty_tx = dirty_tx;
1244 /* Log misc errors. */
1245 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1246 if (csr0 & 0x1000) {
1247 /*
1248 * this happens when our receive ring is full. This shouldn't
1249 * be a problem as we will see normal rx interrupts for the frames
1250 * in the receive ring. But there are some PCI chipsets (I can reproduce
1251 * this on SP3G with Intel saturn chipset) which have sometimes problems
1252 * and will fill up the receive ring with error descriptors. In this
1253 * situation we don't get a rx interrupt, but a missed frame interrupt sooner
1254 * or later. So we try to clean up our receive ring here.
1255 */
1256 pcnet32_rx(dev);
1257 lp->stats.rx_errors++; /* Missed a Rx frame. */
1259 if (csr0 & 0x0800) {
1260 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1261 dev->name, csr0);
1262 /* unlike for the lance, there is no restart needed */
1265 if (must_restart) {
1266 /* stop the chip to clear the error condition, then restart */
1267 lp->a.write_csr (ioaddr, 0, 0x0004);
1268 pcnet32_restart(dev, 0x0002);
1272 /* Clear any other interrupt, and set interrupt enable. */
1273 lp->a.write_csr (ioaddr, 0, 0x7940);
1274 lp->a.write_rap (ioaddr,rap);
1276 if (pcnet32_debug > 4)
1277 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1278 dev->name, lp->a.read_csr (ioaddr, 0));
1280 spin_unlock(&lp->lock);
1283 static int
1284 pcnet32_rx(struct net_device *dev)
1286 struct pcnet32_private *lp = dev->priv;
1287 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1289 /* If we own the next entry, it's a new packet. Send it up. */
1290 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1291 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1293 if (status != 0x03) { /* There was an error. */
1294 /*
1295 * There is a tricky error noted by John Murphy,
1296 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1297 * buffers it's possible for a jabber packet to use two
1298 * buffers, with only the last correctly noting the error.
1299 */
1300 if (status & 0x01) /* Only count a general error at the */
1301 lp->stats.rx_errors++; /* end of a packet.*/
1302 if (status & 0x20) lp->stats.rx_frame_errors++;
1303 if (status & 0x10) lp->stats.rx_over_errors++;
1304 if (status & 0x08) lp->stats.rx_crc_errors++;
1305 if (status & 0x04) lp->stats.rx_fifo_errors++;
1306 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1307 } else {
1308 /* Malloc up new buffer, compatible with net-2e. */
1309 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1310 struct sk_buff *skb;
1312 if(pkt_len < 60) {
1313 printk(KERN_ERR "%s: Runt packet!\n",dev->name);
1314 lp->stats.rx_errors++;
1315 } else {
1316 int rx_in_place = 0;
1318 if (pkt_len > rx_copybreak) {
1319 struct sk_buff *newskb;
1321 if ((newskb = dev_alloc_skb (PKT_BUF_SZ))) {
1322 skb_reserve (newskb, 2);
1323 skb = lp->rx_skbuff[entry];
1324 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], skb->len, PCI_DMA_FROMDEVICE);
1325 skb_put (skb, pkt_len);
1326 lp->rx_skbuff[entry] = newskb;
1327 newskb->dev = dev;
1328 lp->rx_dma_addr[entry] =
1329 pci_map_single(lp->pci_dev, newskb->tail,
1330 newskb->len, PCI_DMA_FROMDEVICE);
1331 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1332 rx_in_place = 1;
1333 } else
1334 skb = NULL;
1335 } else {
1336 skb = dev_alloc_skb(pkt_len+2);
1339 if (skb == NULL) {
1340 int i;
1341 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n", dev->name);
1342 for (i = 0; i < RX_RING_SIZE; i++)
1343 if ((short)le16_to_cpu(lp->rx_ring[(entry+i) & RX_RING_MOD_MASK].status) < 0)
1344 break;
1346 if (i > RX_RING_SIZE -2) {
1347 lp->stats.rx_dropped++;
1348 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1349 lp->cur_rx++;
1351 break;
1353 skb->dev = dev;
1354 if (!rx_in_place) {
1355 skb_reserve(skb,2); /* 16 byte align */
1356 skb_put(skb,pkt_len); /* Make room */
1357 eth_copy_and_sum(skb,
1358 (unsigned char *)(lp->rx_skbuff[entry]->tail),
1359 pkt_len,0);
1361 lp->stats.rx_bytes += skb->len;
1362 skb->protocol=eth_type_trans(skb,dev);
1363 netif_rx(skb);
1364 dev->last_rx = jiffies;
1365 lp->stats.rx_packets++;
1368 /*
1369 * The docs say that the buffer length isn't touched, but Andrew Boyd
1370 * of QNX reports that some revs of the 79C965 clear it.
1371 */
1372 lp->rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1373 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1374 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1377 return 0;
1380 static int
1381 pcnet32_close(struct net_device *dev)
1383 unsigned long ioaddr = dev->base_addr;
1384 struct pcnet32_private *lp = dev->priv;
1385 int i;
1387 netif_stop_queue(dev);
1389 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1391 if (pcnet32_debug > 1)
1392 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1393 dev->name, lp->a.read_csr (ioaddr, 0));
1395 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1396 lp->a.write_csr (ioaddr, 0, 0x0004);
1398 /*
1399 * Switch back to 16bit mode to avoid problems with dumb
1400 * DOS packet driver after a warm reboot
1401 */
1402 lp->a.write_bcr (ioaddr, 20, 4);
1404 free_irq(dev->irq, dev);
1406 /* free all allocated skbuffs */
1407 for (i = 0; i < RX_RING_SIZE; i++) {
1408 lp->rx_ring[i].status = 0;
1409 if (lp->rx_skbuff[i]) {
1410 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], lp->rx_skbuff[i]->len, PCI_DMA_FROMDEVICE);
1411 dev_kfree_skb(lp->rx_skbuff[i]);
1413 lp->rx_skbuff[i] = NULL;
1414 lp->rx_dma_addr[i] = 0;
1417 for (i = 0; i < TX_RING_SIZE; i++) {
1418 if (lp->tx_skbuff[i]) {
1419 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1420 dev_kfree_skb(lp->tx_skbuff[i]);
1422 lp->tx_skbuff[i] = NULL;
1423 lp->tx_dma_addr[i] = 0;
1426 MOD_DEC_USE_COUNT;
1428 return 0;
1431 static struct net_device_stats *
1432 pcnet32_get_stats(struct net_device *dev)
1434 struct pcnet32_private *lp = dev->priv;
1435 unsigned long ioaddr = dev->base_addr;
1436 u16 saved_addr;
1437 unsigned long flags;
1439 spin_lock_irqsave(&lp->lock, flags);
1440 saved_addr = lp->a.read_rap(ioaddr);
1441 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1442 lp->a.write_rap(ioaddr, saved_addr);
1443 spin_unlock_irqrestore(&lp->lock, flags);
1445 return &lp->stats;
1448 /* taken from the sunlance driver, which it took from the depca driver */
1449 static void pcnet32_load_multicast (struct net_device *dev)
1451 struct pcnet32_private *lp = dev->priv;
1452 volatile struct pcnet32_init_block *ib = &lp->init_block;
1453 volatile u16 *mcast_table = (u16 *)&ib->filter;
1454 struct dev_mc_list *dmi=dev->mc_list;
1455 char *addrs;
1456 int i;
1457 u32 crc;
1459 /* set all multicast bits */
1460 if (dev->flags & IFF_ALLMULTI){
1461 ib->filter[0] = 0xffffffff;
1462 ib->filter[1] = 0xffffffff;
1463 return;
1465 /* clear the multicast filter */
1466 ib->filter[0] = 0;
1467 ib->filter[1] = 0;
1469 /* Add addresses */
1470 for (i = 0; i < dev->mc_count; i++){
1471 addrs = dmi->dmi_addr;
1472 dmi = dmi->next;
1474 /* multicast address? */
1475 if (!(*addrs & 1))
1476 continue;
1478 crc = ether_crc_le(6, addrs);
1479 crc = crc >> 26;
1480 mcast_table [crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
1482 return;
1486 /*
1487 * Set or clear the multicast filter for this adaptor.
1488 */
1489 static void pcnet32_set_multicast_list(struct net_device *dev)
1491 unsigned long ioaddr = dev->base_addr, flags;
1492 struct pcnet32_private *lp = dev->priv;
1494 spin_lock_irqsave(&lp->lock, flags);
1495 if (dev->flags&IFF_PROMISC) {
1496 /* Log any net taps. */
1497 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1498 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
1499 } else {
1500 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1501 pcnet32_load_multicast (dev);
1504 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
1506 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
1507 spin_unlock_irqrestore(&lp->lock, flags);
1510 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
1512 struct pcnet32_private *lp = dev->priv;
1513 unsigned long ioaddr = dev->base_addr;
1514 u16 val_out;
1515 int phyaddr;
1517 if (!lp->mii)
1518 return 0;
1520 phyaddr = lp->a.read_bcr(ioaddr, 33);
1522 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1523 val_out = lp->a.read_bcr(ioaddr, 34);
1524 lp->a.write_bcr(ioaddr, 33, phyaddr);
1526 return val_out;
1529 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
1531 struct pcnet32_private *lp = dev->priv;
1532 unsigned long ioaddr = dev->base_addr;
1533 int phyaddr;
1535 if (!lp->mii)
1536 return;
1538 phyaddr = lp->a.read_bcr(ioaddr, 33);
1540 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1541 lp->a.write_bcr(ioaddr, 34, val);
1542 lp->a.write_bcr(ioaddr, 33, phyaddr);
1545 #if 0
1546 static int pcnet32_ethtool_ioctl (struct net_device *dev, void *useraddr)
1548 struct pcnet32_private *lp = dev->priv;
1549 u32 ethcmd;
1550 int phyaddr = 0;
1551 int phy_id = 0;
1552 unsigned long ioaddr = dev->base_addr;
1554 if (lp->mii) {
1555 phyaddr = lp->a.read_bcr (ioaddr, 33);
1556 phy_id = (phyaddr >> 5) & 0x1f;
1557 lp->mii_if.phy_id = phy_id;
1560 if (copy_from_user (&ethcmd, useraddr, sizeof (ethcmd)))
1561 return -EFAULT;
1563 switch (ethcmd) {
1564 case ETHTOOL_GDRVINFO: {
1565 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1566 strcpy (info.driver, DRV_NAME);
1567 strcpy (info.version, DRV_VERSION);
1568 if (lp->pci_dev)
1569 strcpy (info.bus_info, lp->pci_dev->slot_name);
1570 else
1571 sprintf(info.bus_info, "VLB 0x%lx", dev->base_addr);
1572 if (copy_to_user (useraddr, &info, sizeof (info)))
1573 return -EFAULT;
1574 return 0;
1577 /* get settings */
1578 case ETHTOOL_GSET: {
1579 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
1580 spin_lock_irq(&lp->lock);
1581 mii_ethtool_gset(&lp->mii_if, &ecmd);
1582 spin_unlock_irq(&lp->lock);
1583 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1584 return -EFAULT;
1585 return 0;
1587 /* set settings */
1588 case ETHTOOL_SSET: {
1589 int r;
1590 struct ethtool_cmd ecmd;
1591 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1592 return -EFAULT;
1593 spin_lock_irq(&lp->lock);
1594 r = mii_ethtool_sset(&lp->mii_if, &ecmd);
1595 spin_unlock_irq(&lp->lock);
1596 return r;
1598 /* restart autonegotiation */
1599 case ETHTOOL_NWAY_RST: {
1600 return mii_nway_restart(&lp->mii_if);
1602 /* get link status */
1603 case ETHTOOL_GLINK: {
1604 struct ethtool_value edata = {ETHTOOL_GLINK};
1605 edata.data = mii_link_ok(&lp->mii_if);
1606 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1607 return -EFAULT;
1608 return 0;
1611 /* get message-level */
1612 case ETHTOOL_GMSGLVL: {
1613 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
1614 edata.data = pcnet32_debug;
1615 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1616 return -EFAULT;
1617 return 0;
1619 /* set message-level */
1620 case ETHTOOL_SMSGLVL: {
1621 struct ethtool_value edata;
1622 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1623 return -EFAULT;
1624 pcnet32_debug = edata.data;
1625 return 0;
1627 default:
1628 break;
1631 return -EOPNOTSUPP;
1634 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1636 unsigned long ioaddr = dev->base_addr;
1637 struct pcnet32_private *lp = dev->priv;
1638 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1639 int phyaddr = lp->a.read_bcr (ioaddr, 33);
1641 if (cmd == SIOCETHTOOL)
1642 return pcnet32_ethtool_ioctl(dev, (void *) rq->ifr_data);
1644 if (lp->mii) {
1645 switch(cmd) {
1646 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1647 data->phy_id = (phyaddr >> 5) & 0x1f;
1648 /* Fall Through */
1649 case SIOCGMIIREG: /* Read MII PHY register. */
1650 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1651 data->val_out = lp->a.read_bcr (ioaddr, 34);
1652 lp->a.write_bcr (ioaddr, 33, phyaddr);
1653 return 0;
1654 case SIOCSMIIREG: /* Write MII PHY register. */
1655 if (!capable(CAP_NET_ADMIN))
1656 return -EPERM;
1657 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1658 lp->a.write_bcr (ioaddr, 34, data->val_in);
1659 lp->a.write_bcr (ioaddr, 33, phyaddr);
1660 return 0;
1661 default:
1662 return -EOPNOTSUPP;
1665 return -EOPNOTSUPP;
1667 #endif
1669 static struct pci_driver pcnet32_driver = {
1670 name: DRV_NAME,
1671 probe: pcnet32_probe_pci,
1672 id_table: pcnet32_pci_tbl,
1673 };
1675 MODULE_PARM(debug, "i");
1676 MODULE_PARM_DESC(debug, DRV_NAME " debug level (0-6)");
1677 MODULE_PARM(max_interrupt_work, "i");
1678 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
1679 MODULE_PARM(rx_copybreak, "i");
1680 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1681 MODULE_PARM(tx_start_pt, "i");
1682 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
1683 MODULE_PARM(pcnet32vlb, "i");
1684 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
1685 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
1686 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
1687 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
1688 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
1690 MODULE_AUTHOR("Thomas Bogendoerfer");
1691 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
1692 MODULE_LICENSE("GPL");
1694 /* An additional parameter that may be passed in... */
1695 static int debug = -1;
1696 static int tx_start_pt = -1;
1698 static int __init pcnet32_init_module(void)
1700 if (debug > 0)
1701 pcnet32_debug = debug;
1703 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
1704 tx_start = tx_start_pt;
1706 /* find the PCI devices */
1707 pci_module_init(&pcnet32_driver);
1709 /* should we find any remaining VLbus devices ? */
1710 if (pcnet32vlb)
1711 pcnet32_probe_vlbus();
1713 if (cards_found) {
1714 printk(KERN_INFO "%s", version);
1715 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1718 return cards_found ? 0 : -ENODEV;
1721 static void __exit pcnet32_cleanup_module(void)
1723 struct net_device *next_dev;
1725 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1726 while (pcnet32_dev) {
1727 struct pcnet32_private *lp = pcnet32_dev->priv;
1728 next_dev = lp->next;
1729 unregister_netdev(pcnet32_dev);
1730 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
1731 if (lp->pci_dev)
1732 pci_unregister_driver(&pcnet32_driver);
1733 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1734 kfree(pcnet32_dev);
1735 pcnet32_dev = next_dev;
1739 module_init(pcnet32_init_module);
1740 module_exit(pcnet32_cleanup_module);
1742 /*
1743 * Local variables:
1744 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c pcnet32.c"
1745 * c-indent-level: 4
1746 * tab-width: 8
1747 * End:
1748 */