debuggers.hg

view tools/ioemu/hw/vga.c @ 16636:51c9755a52d5

Revert 16579:0884e0a5ecc33afac8d60ea09652cf436d1a33ce.
author Keir Fraser <keir.fraser@citrix.com>
date Wed Dec 12 12:00:46 2007 +0000 (2007-12-12)
parents 0884e0a5ecc3
children 20898120c8f9
line source
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "vga_int.h"
27 //#define DEBUG_VGA
28 //#define DEBUG_VGA_MEM
29 //#define DEBUG_VGA_REG
31 //#define DEBUG_BOCHS_VBE
33 /* force some bits to zero */
34 const uint8_t sr_mask[8] = {
35 (uint8_t)~0xfc,
36 (uint8_t)~0xc2,
37 (uint8_t)~0xf0,
38 (uint8_t)~0xc0,
39 (uint8_t)~0xf1,
40 (uint8_t)~0xff,
41 (uint8_t)~0xff,
42 (uint8_t)~0x00,
43 };
45 const uint8_t gr_mask[16] = {
46 (uint8_t)~0xf0, /* 0x00 */
47 (uint8_t)~0xf0, /* 0x01 */
48 (uint8_t)~0xf0, /* 0x02 */
49 (uint8_t)~0xe0, /* 0x03 */
50 (uint8_t)~0xfc, /* 0x04 */
51 (uint8_t)~0x84, /* 0x05 */
52 (uint8_t)~0xf0, /* 0x06 */
53 (uint8_t)~0xf0, /* 0x07 */
54 (uint8_t)~0x00, /* 0x08 */
55 (uint8_t)~0xff, /* 0x09 */
56 (uint8_t)~0xff, /* 0x0a */
57 (uint8_t)~0xff, /* 0x0b */
58 (uint8_t)~0xff, /* 0x0c */
59 (uint8_t)~0xff, /* 0x0d */
60 (uint8_t)~0xff, /* 0x0e */
61 (uint8_t)~0xff, /* 0x0f */
62 };
64 #define cbswap_32(__x) \
65 ((uint32_t)( \
66 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
67 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
68 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
69 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
71 #ifdef WORDS_BIGENDIAN
72 #define PAT(x) cbswap_32(x)
73 #else
74 #define PAT(x) (x)
75 #endif
77 #ifdef WORDS_BIGENDIAN
78 #define BIG 1
79 #else
80 #define BIG 0
81 #endif
83 #ifdef WORDS_BIGENDIAN
84 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
85 #else
86 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
87 #endif
89 static const uint32_t mask16[16] = {
90 PAT(0x00000000),
91 PAT(0x000000ff),
92 PAT(0x0000ff00),
93 PAT(0x0000ffff),
94 PAT(0x00ff0000),
95 PAT(0x00ff00ff),
96 PAT(0x00ffff00),
97 PAT(0x00ffffff),
98 PAT(0xff000000),
99 PAT(0xff0000ff),
100 PAT(0xff00ff00),
101 PAT(0xff00ffff),
102 PAT(0xffff0000),
103 PAT(0xffff00ff),
104 PAT(0xffffff00),
105 PAT(0xffffffff),
106 };
108 #undef PAT
110 #ifdef WORDS_BIGENDIAN
111 #define PAT(x) (x)
112 #else
113 #define PAT(x) cbswap_32(x)
114 #endif
116 static const uint32_t dmask16[16] = {
117 PAT(0x00000000),
118 PAT(0x000000ff),
119 PAT(0x0000ff00),
120 PAT(0x0000ffff),
121 PAT(0x00ff0000),
122 PAT(0x00ff00ff),
123 PAT(0x00ffff00),
124 PAT(0x00ffffff),
125 PAT(0xff000000),
126 PAT(0xff0000ff),
127 PAT(0xff00ff00),
128 PAT(0xff00ffff),
129 PAT(0xffff0000),
130 PAT(0xffff00ff),
131 PAT(0xffffff00),
132 PAT(0xffffffff),
133 };
135 static const uint32_t dmask4[4] = {
136 PAT(0x00000000),
137 PAT(0x0000ffff),
138 PAT(0xffff0000),
139 PAT(0xffffffff),
140 };
142 static uint32_t expand4[256];
143 static uint16_t expand2[256];
144 static uint8_t expand4to8[16];
146 static void vga_screen_dump(void *opaque, const char *filename);
148 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
149 {
150 VGAState *s = opaque;
151 int val, index;
153 /* check port range access depending on color/monochrome mode */
154 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
155 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
156 val = 0xff;
157 } else {
158 switch(addr) {
159 case 0x3c0:
160 if (s->ar_flip_flop == 0) {
161 val = s->ar_index;
162 } else {
163 val = 0;
164 }
165 break;
166 case 0x3c1:
167 index = s->ar_index & 0x1f;
168 if (index < 21)
169 val = s->ar[index];
170 else
171 val = 0;
172 break;
173 case 0x3c2:
174 val = s->st00;
175 break;
176 case 0x3c4:
177 val = s->sr_index;
178 break;
179 case 0x3c5:
180 val = s->sr[s->sr_index];
181 #ifdef DEBUG_VGA_REG
182 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
183 #endif
184 break;
185 case 0x3c7:
186 val = s->dac_state;
187 break;
188 case 0x3c8:
189 val = s->dac_write_index;
190 break;
191 case 0x3c9:
192 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
193 if (++s->dac_sub_index == 3) {
194 s->dac_sub_index = 0;
195 s->dac_read_index++;
196 }
197 break;
198 case 0x3ca:
199 val = s->fcr;
200 break;
201 case 0x3cc:
202 val = s->msr;
203 break;
204 case 0x3ce:
205 val = s->gr_index;
206 break;
207 case 0x3cf:
208 val = s->gr[s->gr_index];
209 #ifdef DEBUG_VGA_REG
210 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
211 #endif
212 break;
213 case 0x3b4:
214 case 0x3d4:
215 val = s->cr_index;
216 break;
217 case 0x3b5:
218 case 0x3d5:
219 val = s->cr[s->cr_index];
220 #ifdef DEBUG_VGA_REG
221 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
222 #endif
223 break;
224 case 0x3ba:
225 case 0x3da:
226 /* just toggle to fool polling */
227 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
228 val = s->st01;
229 s->ar_flip_flop = 0;
230 break;
231 default:
232 val = 0x00;
233 break;
234 }
235 }
236 #if defined(DEBUG_VGA)
237 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
238 #endif
239 return val;
240 }
242 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
243 {
244 VGAState *s = opaque;
245 int index;
247 /* check port range access depending on color/monochrome mode */
248 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
249 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
250 return;
252 #ifdef DEBUG_VGA
253 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
254 #endif
256 switch(addr) {
257 case 0x3c0:
258 if (s->ar_flip_flop == 0) {
259 val &= 0x3f;
260 s->ar_index = val;
261 } else {
262 index = s->ar_index & 0x1f;
263 switch(index) {
264 case 0x00 ... 0x0f:
265 s->ar[index] = val & 0x3f;
266 break;
267 case 0x10:
268 s->ar[index] = val & ~0x10;
269 break;
270 case 0x11:
271 s->ar[index] = val;
272 break;
273 case 0x12:
274 s->ar[index] = val & ~0xc0;
275 break;
276 case 0x13:
277 s->ar[index] = val & ~0xf0;
278 break;
279 case 0x14:
280 s->ar[index] = val & ~0xf0;
281 break;
282 default:
283 break;
284 }
285 }
286 s->ar_flip_flop ^= 1;
287 break;
288 case 0x3c2:
289 s->msr = val & ~0x10;
290 break;
291 case 0x3c4:
292 s->sr_index = val & 7;
293 break;
294 case 0x3c5:
295 #ifdef DEBUG_VGA_REG
296 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
297 #endif
298 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
299 break;
300 case 0x3c7:
301 s->dac_read_index = val;
302 s->dac_sub_index = 0;
303 s->dac_state = 3;
304 break;
305 case 0x3c8:
306 s->dac_write_index = val;
307 s->dac_sub_index = 0;
308 s->dac_state = 0;
309 break;
310 case 0x3c9:
311 s->dac_cache[s->dac_sub_index] = val;
312 if (++s->dac_sub_index == 3) {
313 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
314 s->dac_sub_index = 0;
315 s->dac_write_index++;
316 }
317 break;
318 case 0x3ce:
319 s->gr_index = val & 0x0f;
320 break;
321 case 0x3cf:
322 #ifdef DEBUG_VGA_REG
323 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
324 #endif
325 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
326 break;
327 case 0x3b4:
328 case 0x3d4:
329 s->cr_index = val;
330 break;
331 case 0x3b5:
332 case 0x3d5:
333 #ifdef DEBUG_VGA_REG
334 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
335 #endif
336 /* handle CR0-7 protection */
337 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
338 /* can always write bit 4 of CR7 */
339 if (s->cr_index == 7)
340 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
341 return;
342 }
343 switch(s->cr_index) {
344 case 0x01: /* horizontal display end */
345 case 0x07:
346 case 0x09:
347 case 0x0c:
348 case 0x0d:
349 case 0x12: /* veritcal display end */
350 s->cr[s->cr_index] = val;
351 break;
352 default:
353 s->cr[s->cr_index] = val;
354 break;
355 }
356 break;
357 case 0x3ba:
358 case 0x3da:
359 s->fcr = val & 0x10;
360 break;
361 }
362 }
364 #ifdef CONFIG_BOCHS_VBE
365 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
366 {
367 VGAState *s = opaque;
368 uint32_t val;
369 val = s->vbe_index;
370 return val;
371 }
373 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
374 {
375 VGAState *s = opaque;
376 uint32_t val;
378 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
379 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
380 switch(s->vbe_index) {
381 /* XXX: do not hardcode ? */
382 case VBE_DISPI_INDEX_XRES:
383 val = VBE_DISPI_MAX_XRES;
384 break;
385 case VBE_DISPI_INDEX_YRES:
386 val = VBE_DISPI_MAX_YRES;
387 break;
388 case VBE_DISPI_INDEX_BPP:
389 val = VBE_DISPI_MAX_BPP;
390 break;
391 default:
392 val = s->vbe_regs[s->vbe_index];
393 break;
394 }
395 } else {
396 val = s->vbe_regs[s->vbe_index];
397 }
398 } else {
399 val = 0;
400 }
401 #ifdef DEBUG_BOCHS_VBE
402 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
403 #endif
404 return val;
405 }
407 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
408 {
409 VGAState *s = opaque;
410 s->vbe_index = val;
411 }
413 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
414 {
415 VGAState *s = opaque;
417 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
418 #ifdef DEBUG_BOCHS_VBE
419 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
420 #endif
421 switch(s->vbe_index) {
422 case VBE_DISPI_INDEX_ID:
423 if (val == VBE_DISPI_ID0 ||
424 val == VBE_DISPI_ID1 ||
425 val == VBE_DISPI_ID2 ||
426 val == VBE_DISPI_ID3 ||
427 val == VBE_DISPI_ID4) {
428 s->vbe_regs[s->vbe_index] = val;
429 }
430 break;
431 case VBE_DISPI_INDEX_XRES:
432 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
433 s->vbe_regs[s->vbe_index] = val;
434 }
435 break;
436 case VBE_DISPI_INDEX_YRES:
437 if (val <= VBE_DISPI_MAX_YRES) {
438 s->vbe_regs[s->vbe_index] = val;
439 }
440 break;
441 case VBE_DISPI_INDEX_BPP:
442 if (val == 0)
443 val = 8;
444 if (val == 4 || val == 8 || val == 15 ||
445 val == 16 || val == 24 || val == 32) {
446 s->vbe_regs[s->vbe_index] = val;
447 }
448 break;
449 case VBE_DISPI_INDEX_BANK:
450 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
451 val &= (s->vbe_bank_mask >> 2);
452 } else {
453 val &= s->vbe_bank_mask;
454 }
455 s->vbe_regs[s->vbe_index] = val;
456 s->bank_offset = (val << 16);
457 break;
458 case VBE_DISPI_INDEX_ENABLE:
459 if ((val & VBE_DISPI_ENABLED) &&
460 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
461 int h, shift_control;
463 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
464 s->vbe_regs[VBE_DISPI_INDEX_XRES];
465 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
466 s->vbe_regs[VBE_DISPI_INDEX_YRES];
467 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
468 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
470 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
471 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
472 else
473 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
474 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
475 s->vbe_start_addr = 0;
477 /* clear the screen (should be done in BIOS) */
478 if (!(val & VBE_DISPI_NOCLEARMEM)) {
479 memset(s->vram_ptr, 0,
480 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
481 }
483 /* we initialize the VGA graphic mode (should be done
484 in BIOS) */
485 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
486 s->cr[0x17] |= 3; /* no CGA modes */
487 s->cr[0x13] = s->vbe_line_offset >> 3;
488 /* width */
489 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
490 /* height (only meaningful if < 1024) */
491 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
492 s->cr[0x12] = h;
493 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
494 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
495 /* line compare to 1023 */
496 s->cr[0x18] = 0xff;
497 s->cr[0x07] |= 0x10;
498 s->cr[0x09] |= 0x40;
500 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
501 shift_control = 0;
502 s->sr[0x01] &= ~8; /* no double line */
503 } else {
504 shift_control = 2;
505 s->sr[4] |= 0x08; /* set chain 4 mode */
506 s->sr[2] |= 0x0f; /* activate all planes */
507 }
508 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
509 s->cr[0x09] &= ~0x9f; /* no double scan */
510 } else {
511 /* XXX: the bios should do that */
512 s->bank_offset = 0;
513 }
514 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
515 s->vbe_regs[s->vbe_index] = val;
516 break;
517 case VBE_DISPI_INDEX_VIRT_WIDTH:
518 {
519 int w, h, line_offset;
521 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
522 return;
523 w = val;
524 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
525 line_offset = w >> 1;
526 else
527 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
528 h = s->vram_size / line_offset;
529 /* XXX: support weird bochs semantics ? */
530 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
531 return;
532 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
533 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
534 s->vbe_line_offset = line_offset;
535 }
536 break;
537 case VBE_DISPI_INDEX_X_OFFSET:
538 case VBE_DISPI_INDEX_Y_OFFSET:
539 {
540 int x;
541 s->vbe_regs[s->vbe_index] = val;
542 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
543 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
544 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
545 s->vbe_start_addr += x >> 1;
546 else
547 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
548 s->vbe_start_addr >>= 2;
549 }
550 break;
551 default:
552 break;
553 }
554 }
555 }
556 #endif
558 /* called for accesses between 0xa0000 and 0xc0000 */
559 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
560 {
561 VGAState *s = opaque;
562 int memory_map_mode, plane;
563 uint32_t ret;
565 /* convert to VGA memory offset */
566 memory_map_mode = (s->gr[6] >> 2) & 3;
567 addr &= 0x1ffff;
568 switch(memory_map_mode) {
569 case 0:
570 break;
571 case 1:
572 if (addr >= 0x10000)
573 return 0xff;
574 addr += s->bank_offset;
575 break;
576 case 2:
577 addr -= 0x10000;
578 if (addr >= 0x8000)
579 return 0xff;
580 break;
581 default:
582 case 3:
583 addr -= 0x18000;
584 if (addr >= 0x8000)
585 return 0xff;
586 break;
587 }
589 if (s->sr[4] & 0x08) {
590 /* chain 4 mode : simplest access */
591 ret = s->vram_ptr[addr];
592 } else if (s->gr[5] & 0x10) {
593 /* odd/even mode (aka text mode mapping) */
594 plane = (s->gr[4] & 2) | (addr & 1);
595 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
596 } else {
597 /* standard VGA latched access */
598 s->latch = ((uint32_t *)s->vram_ptr)[addr];
600 if (!(s->gr[5] & 0x08)) {
601 /* read mode 0 */
602 plane = s->gr[4];
603 ret = GET_PLANE(s->latch, plane);
604 } else {
605 /* read mode 1 */
606 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
607 ret |= ret >> 16;
608 ret |= ret >> 8;
609 ret = (~ret) & 0xff;
610 }
611 }
612 return ret;
613 }
615 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
616 {
617 uint32_t v;
618 #ifdef TARGET_WORDS_BIGENDIAN
619 v = vga_mem_readb(opaque, addr) << 8;
620 v |= vga_mem_readb(opaque, addr + 1);
621 #else
622 v = vga_mem_readb(opaque, addr);
623 v |= vga_mem_readb(opaque, addr + 1) << 8;
624 #endif
625 return v;
626 }
628 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
629 {
630 uint32_t v;
631 #ifdef TARGET_WORDS_BIGENDIAN
632 v = vga_mem_readb(opaque, addr) << 24;
633 v |= vga_mem_readb(opaque, addr + 1) << 16;
634 v |= vga_mem_readb(opaque, addr + 2) << 8;
635 v |= vga_mem_readb(opaque, addr + 3);
636 #else
637 v = vga_mem_readb(opaque, addr);
638 v |= vga_mem_readb(opaque, addr + 1) << 8;
639 v |= vga_mem_readb(opaque, addr + 2) << 16;
640 v |= vga_mem_readb(opaque, addr + 3) << 24;
641 #endif
642 return v;
643 }
645 /* called for accesses between 0xa0000 and 0xc0000 */
646 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
647 {
648 VGAState *s = opaque;
649 int memory_map_mode, plane, write_mode, b, func_select, mask;
650 uint32_t write_mask, bit_mask, set_mask;
652 #ifdef DEBUG_VGA_MEM
653 printf("vga: [0x%x] = 0x%02x\n", addr, val);
654 #endif
655 /* convert to VGA memory offset */
656 memory_map_mode = (s->gr[6] >> 2) & 3;
657 addr &= 0x1ffff;
658 switch(memory_map_mode) {
659 case 0:
660 break;
661 case 1:
662 if (addr >= 0x10000)
663 return;
664 addr += s->bank_offset;
665 break;
666 case 2:
667 addr -= 0x10000;
668 if (addr >= 0x8000)
669 return;
670 break;
671 default:
672 case 3:
673 addr -= 0x18000;
674 if (addr >= 0x8000)
675 return;
676 break;
677 }
679 if (s->sr[4] & 0x08) {
680 /* chain 4 mode : simplest access */
681 plane = addr & 3;
682 mask = (1 << plane);
683 if (s->sr[2] & mask) {
684 s->vram_ptr[addr] = val;
685 #ifdef DEBUG_VGA_MEM
686 printf("vga: chain4: [0x%x]\n", addr);
687 #endif
688 s->plane_updated |= mask; /* only used to detect font change */
689 cpu_physical_memory_set_dirty(s->vram_offset + addr);
690 }
691 } else if (s->gr[5] & 0x10) {
692 /* odd/even mode (aka text mode mapping) */
693 plane = (s->gr[4] & 2) | (addr & 1);
694 mask = (1 << plane);
695 if (s->sr[2] & mask) {
696 addr = ((addr & ~1) << 1) | plane;
697 s->vram_ptr[addr] = val;
698 #ifdef DEBUG_VGA_MEM
699 printf("vga: odd/even: [0x%x]\n", addr);
700 #endif
701 s->plane_updated |= mask; /* only used to detect font change */
702 cpu_physical_memory_set_dirty(s->vram_offset + addr);
703 }
704 } else {
705 /* standard VGA latched access */
706 write_mode = s->gr[5] & 3;
707 switch(write_mode) {
708 default:
709 case 0:
710 /* rotate */
711 b = s->gr[3] & 7;
712 val = ((val >> b) | (val << (8 - b))) & 0xff;
713 val |= val << 8;
714 val |= val << 16;
716 /* apply set/reset mask */
717 set_mask = mask16[s->gr[1]];
718 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
719 bit_mask = s->gr[8];
720 break;
721 case 1:
722 val = s->latch;
723 goto do_write;
724 case 2:
725 val = mask16[val & 0x0f];
726 bit_mask = s->gr[8];
727 break;
728 case 3:
729 /* rotate */
730 b = s->gr[3] & 7;
731 val = (val >> b) | (val << (8 - b));
733 bit_mask = s->gr[8] & val;
734 val = mask16[s->gr[0]];
735 break;
736 }
738 /* apply logical operation */
739 func_select = s->gr[3] >> 3;
740 switch(func_select) {
741 case 0:
742 default:
743 /* nothing to do */
744 break;
745 case 1:
746 /* and */
747 val &= s->latch;
748 break;
749 case 2:
750 /* or */
751 val |= s->latch;
752 break;
753 case 3:
754 /* xor */
755 val ^= s->latch;
756 break;
757 }
759 /* apply bit mask */
760 bit_mask |= bit_mask << 8;
761 bit_mask |= bit_mask << 16;
762 val = (val & bit_mask) | (s->latch & ~bit_mask);
764 do_write:
765 /* mask data according to sr[2] */
766 mask = s->sr[2];
767 s->plane_updated |= mask; /* only used to detect font change */
768 write_mask = mask16[mask];
769 ((uint32_t *)s->vram_ptr)[addr] =
770 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
771 (val & write_mask);
772 #ifdef DEBUG_VGA_MEM
773 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
774 addr * 4, write_mask, val);
775 #endif
776 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
777 }
778 }
780 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
781 {
782 #ifdef TARGET_WORDS_BIGENDIAN
783 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
784 vga_mem_writeb(opaque, addr + 1, val & 0xff);
785 #else
786 vga_mem_writeb(opaque, addr, val & 0xff);
787 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
788 #endif
789 }
791 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
792 {
793 #ifdef TARGET_WORDS_BIGENDIAN
794 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
795 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
796 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
797 vga_mem_writeb(opaque, addr + 3, val & 0xff);
798 #else
799 vga_mem_writeb(opaque, addr, val & 0xff);
800 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
801 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
802 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
803 #endif
804 }
806 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
807 const uint8_t *font_ptr, int h,
808 uint32_t fgcol, uint32_t bgcol);
809 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
810 const uint8_t *font_ptr, int h,
811 uint32_t fgcol, uint32_t bgcol, int dup9);
812 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
813 const uint8_t *s, int width);
815 static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
816 {
817 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
818 }
820 static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
821 {
822 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
823 }
825 static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
826 {
827 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
828 }
830 static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
831 {
832 return (r << 16) | (g << 8) | b;
833 }
835 static inline unsigned int rgb_to_pixel32bgr(unsigned int r, unsigned int g, unsigned b)
836 {
837 return (b << 16) | (g << 8) | r;
838 }
840 #define DEPTH 8
841 #include "vga_template.h"
843 #define DEPTH 15
844 #include "vga_template.h"
846 #define DEPTH 16
847 #include "vga_template.h"
849 #define DEPTH 32
850 #include "vga_template.h"
852 #define BGR_FORMAT
853 #define DEPTH 32
854 #include "vga_template.h"
856 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
857 {
858 unsigned int col;
859 col = rgb_to_pixel8(r, g, b);
860 col |= col << 8;
861 col |= col << 16;
862 return col;
863 }
865 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
866 {
867 unsigned int col;
868 col = rgb_to_pixel15(r, g, b);
869 col |= col << 16;
870 return col;
871 }
873 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
874 {
875 unsigned int col;
876 col = rgb_to_pixel16(r, g, b);
877 col |= col << 16;
878 return col;
879 }
881 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
882 {
883 unsigned int col;
884 col = rgb_to_pixel32(r, g, b);
885 return col;
886 }
888 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
889 {
890 unsigned int col;
891 col = rgb_to_pixel32bgr(r, g, b);
892 return col;
893 }
895 /* return true if the palette was modified */
896 static int update_palette16(VGAState *s)
897 {
898 int full_update, i;
899 uint32_t v, col, *palette;
901 full_update = 0;
902 palette = s->last_palette;
903 for(i = 0; i < 16; i++) {
904 v = s->ar[i];
905 if (s->ar[0x10] & 0x80)
906 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
907 else
908 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
909 v = v * 3;
910 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
911 c6_to_8(s->palette[v + 1]),
912 c6_to_8(s->palette[v + 2]));
913 if (col != palette[i]) {
914 full_update = 1;
915 palette[i] = col;
916 }
917 }
918 return full_update;
919 }
921 /* return true if the palette was modified */
922 static int update_palette256(VGAState *s)
923 {
924 int full_update, i;
925 uint32_t v, col, *palette;
927 full_update = 0;
928 palette = s->last_palette;
929 v = 0;
930 for(i = 0; i < 256; i++) {
931 if (s->dac_8bit) {
932 col = s->rgb_to_pixel(s->palette[v],
933 s->palette[v + 1],
934 s->palette[v + 2]);
935 } else {
936 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
937 c6_to_8(s->palette[v + 1]),
938 c6_to_8(s->palette[v + 2]));
939 }
940 if (col != palette[i]) {
941 full_update = 1;
942 palette[i] = col;
943 }
944 v += 3;
945 }
946 return full_update;
947 }
949 static void vga_get_offsets(VGAState *s,
950 uint32_t *pline_offset,
951 uint32_t *pstart_addr,
952 uint32_t *pline_compare)
953 {
954 uint32_t start_addr, line_offset, line_compare;
955 #ifdef CONFIG_BOCHS_VBE
956 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
957 line_offset = s->vbe_line_offset;
958 start_addr = s->vbe_start_addr;
959 line_compare = 65535;
960 } else
961 #endif
962 {
963 /* compute line_offset in bytes */
964 line_offset = s->cr[0x13];
965 line_offset <<= 3;
967 /* starting address */
968 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
970 /* line compare */
971 line_compare = s->cr[0x18] |
972 ((s->cr[0x07] & 0x10) << 4) |
973 ((s->cr[0x09] & 0x40) << 3);
974 }
975 *pline_offset = line_offset;
976 *pstart_addr = start_addr;
977 *pline_compare = line_compare;
978 }
980 /* update start_addr and line_offset. Return TRUE if modified */
981 static int update_basic_params(VGAState *s)
982 {
983 int full_update;
984 uint32_t start_addr, line_offset, line_compare;
986 full_update = 0;
988 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
990 if (line_offset != s->line_offset ||
991 start_addr != s->start_addr ||
992 line_compare != s->line_compare) {
993 s->line_offset = line_offset;
994 s->start_addr = start_addr;
995 s->line_compare = line_compare;
996 full_update = 1;
997 }
998 return full_update;
999 }
1001 #define NB_DEPTHS 5
1003 static inline int get_depth_index(DisplayState *s)
1005 switch(s->depth) {
1006 default:
1007 case 8:
1008 return 0;
1009 case 15:
1010 return 1;
1011 case 16:
1012 return 2;
1013 case 32:
1014 if (s->bgr)
1015 return 4;
1016 else
1017 return 3;
1021 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1022 vga_draw_glyph8_8,
1023 vga_draw_glyph8_16,
1024 vga_draw_glyph8_16,
1025 vga_draw_glyph8_32,
1026 vga_draw_glyph8_32,
1027 };
1029 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1030 vga_draw_glyph16_8,
1031 vga_draw_glyph16_16,
1032 vga_draw_glyph16_16,
1033 vga_draw_glyph16_32,
1034 vga_draw_glyph16_32,
1035 };
1037 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1038 vga_draw_glyph9_8,
1039 vga_draw_glyph9_16,
1040 vga_draw_glyph9_16,
1041 vga_draw_glyph9_32,
1042 vga_draw_glyph9_32,
1043 };
1045 static const uint8_t cursor_glyph[32 * 4] = {
1046 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1047 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1048 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1049 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1050 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1051 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1052 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1053 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1054 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1055 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1056 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1057 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1058 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1059 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1060 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1061 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1062 };
1064 /*
1065 * Text mode update
1066 * Missing:
1067 * - double scan
1068 * - double width
1069 * - underline
1070 * - flashing
1071 */
1072 static void vga_draw_text(VGAState *s, int full_update)
1074 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1075 int cx_min, cx_max, linesize, x_incr;
1076 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1077 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1078 const uint8_t *font_ptr, *font_base[2];
1079 int dup9, line_offset, depth_index;
1080 uint32_t *palette;
1081 uint32_t *ch_attr_ptr;
1082 vga_draw_glyph8_func *vga_draw_glyph8;
1083 vga_draw_glyph9_func *vga_draw_glyph9;
1085 full_update |= update_palette16(s);
1086 palette = s->last_palette;
1088 /* compute font data address (in plane 2) */
1089 v = s->sr[3];
1090 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1091 if (offset != s->font_offsets[0]) {
1092 s->font_offsets[0] = offset;
1093 full_update = 1;
1095 font_base[0] = s->vram_ptr + offset;
1097 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1098 font_base[1] = s->vram_ptr + offset;
1099 if (offset != s->font_offsets[1]) {
1100 s->font_offsets[1] = offset;
1101 full_update = 1;
1103 if (s->plane_updated & (1 << 2)) {
1104 /* if the plane 2 was modified since the last display, it
1105 indicates the font may have been modified */
1106 s->plane_updated = 0;
1107 full_update = 1;
1109 full_update |= update_basic_params(s);
1111 line_offset = s->line_offset;
1112 s1 = s->vram_ptr + (s->start_addr * 4);
1114 /* total width & height */
1115 cheight = (s->cr[9] & 0x1f) + 1;
1116 cw = 8;
1117 if (!(s->sr[1] & 0x01))
1118 cw = 9;
1119 if (s->sr[1] & 0x08)
1120 cw = 16; /* NOTE: no 18 pixel wide */
1121 x_incr = cw * ((s->ds->depth + 7) >> 3);
1122 width = (s->cr[0x01] + 1);
1123 if (s->cr[0x06] == 100) {
1124 /* ugly hack for CGA 160x100x16 - explain me the logic */
1125 height = 100;
1126 } else {
1127 height = s->cr[0x12] |
1128 ((s->cr[0x07] & 0x02) << 7) |
1129 ((s->cr[0x07] & 0x40) << 3);
1130 height = (height + 1) / cheight;
1132 if ((height * width) > CH_ATTR_SIZE) {
1133 /* better than nothing: exit if transient size is too big */
1134 return;
1137 if (width != s->last_width || height != s->last_height ||
1138 cw != s->last_cw || cheight != s->last_ch) {
1139 s->last_scr_width = width * cw;
1140 s->last_scr_height = height * cheight;
1141 dpy_resize(s->ds, s->last_scr_width, s->last_scr_height);
1142 s->last_width = width;
1143 s->last_height = height;
1144 s->last_ch = cheight;
1145 s->last_cw = cw;
1146 full_update = 1;
1148 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1149 if (cursor_offset != s->cursor_offset ||
1150 s->cr[0xa] != s->cursor_start ||
1151 s->cr[0xb] != s->cursor_end) {
1152 /* if the cursor position changed, we update the old and new
1153 chars */
1154 if (s->cursor_offset < CH_ATTR_SIZE)
1155 s->last_ch_attr[s->cursor_offset] = -1;
1156 if (cursor_offset < CH_ATTR_SIZE)
1157 s->last_ch_attr[cursor_offset] = -1;
1158 s->cursor_offset = cursor_offset;
1159 s->cursor_start = s->cr[0xa];
1160 s->cursor_end = s->cr[0xb];
1162 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1164 depth_index = get_depth_index(s->ds);
1165 if (cw == 16)
1166 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1167 else
1168 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1169 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1171 dest = s->ds->data;
1172 linesize = s->ds->linesize;
1173 ch_attr_ptr = s->last_ch_attr;
1174 for(cy = 0; cy < height; cy++) {
1175 d1 = dest;
1176 src = s1;
1177 cx_min = width;
1178 cx_max = -1;
1179 for(cx = 0; cx < width; cx++) {
1180 ch_attr = *(uint16_t *)src;
1181 if (full_update || ch_attr != *ch_attr_ptr) {
1182 if (cx < cx_min)
1183 cx_min = cx;
1184 if (cx > cx_max)
1185 cx_max = cx;
1186 *ch_attr_ptr = ch_attr;
1187 #ifdef WORDS_BIGENDIAN
1188 ch = ch_attr >> 8;
1189 cattr = ch_attr & 0xff;
1190 #else
1191 ch = ch_attr & 0xff;
1192 cattr = ch_attr >> 8;
1193 #endif
1194 font_ptr = font_base[(cattr >> 3) & 1];
1195 font_ptr += 32 * 4 * ch;
1196 bgcol = palette[cattr >> 4];
1197 fgcol = palette[cattr & 0x0f];
1198 if (cw != 9) {
1199 vga_draw_glyph8(d1, linesize,
1200 font_ptr, cheight, fgcol, bgcol);
1201 } else {
1202 dup9 = 0;
1203 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1204 dup9 = 1;
1205 vga_draw_glyph9(d1, linesize,
1206 font_ptr, cheight, fgcol, bgcol, dup9);
1208 if (src == cursor_ptr &&
1209 !(s->cr[0x0a] & 0x20)) {
1210 int line_start, line_last, h;
1211 /* draw the cursor */
1212 line_start = s->cr[0x0a] & 0x1f;
1213 line_last = s->cr[0x0b] & 0x1f;
1214 /* XXX: check that */
1215 if (line_last > cheight - 1)
1216 line_last = cheight - 1;
1217 if (line_last >= line_start && line_start < cheight) {
1218 h = line_last - line_start + 1;
1219 d = d1 + linesize * line_start;
1220 if (cw != 9) {
1221 vga_draw_glyph8(d, linesize,
1222 cursor_glyph, h, fgcol, bgcol);
1223 } else {
1224 vga_draw_glyph9(d, linesize,
1225 cursor_glyph, h, fgcol, bgcol, 1);
1230 d1 += x_incr;
1231 src += 4;
1232 ch_attr_ptr++;
1234 if (cx_max != -1) {
1235 dpy_update(s->ds, cx_min * cw, cy * cheight,
1236 (cx_max - cx_min + 1) * cw, cheight);
1238 dest += linesize * cheight;
1239 s1 += line_offset;
1243 enum {
1244 VGA_DRAW_LINE2,
1245 VGA_DRAW_LINE2D2,
1246 VGA_DRAW_LINE4,
1247 VGA_DRAW_LINE4D2,
1248 VGA_DRAW_LINE8D2,
1249 VGA_DRAW_LINE8,
1250 VGA_DRAW_LINE15,
1251 VGA_DRAW_LINE16,
1252 VGA_DRAW_LINE24,
1253 VGA_DRAW_LINE32,
1254 VGA_DRAW_LINE_NB,
1255 };
1257 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1258 vga_draw_line2_8,
1259 vga_draw_line2_16,
1260 vga_draw_line2_16,
1261 vga_draw_line2_32,
1262 vga_draw_line2_32,
1264 vga_draw_line2d2_8,
1265 vga_draw_line2d2_16,
1266 vga_draw_line2d2_16,
1267 vga_draw_line2d2_32,
1268 vga_draw_line2d2_32,
1270 vga_draw_line4_8,
1271 vga_draw_line4_16,
1272 vga_draw_line4_16,
1273 vga_draw_line4_32,
1274 vga_draw_line4_32,
1276 vga_draw_line4d2_8,
1277 vga_draw_line4d2_16,
1278 vga_draw_line4d2_16,
1279 vga_draw_line4d2_32,
1280 vga_draw_line4d2_32,
1282 vga_draw_line8d2_8,
1283 vga_draw_line8d2_16,
1284 vga_draw_line8d2_16,
1285 vga_draw_line8d2_32,
1286 vga_draw_line8d2_32,
1288 vga_draw_line8_8,
1289 vga_draw_line8_16,
1290 vga_draw_line8_16,
1291 vga_draw_line8_32,
1292 vga_draw_line8_32,
1294 vga_draw_line15_8,
1295 vga_draw_line15_15,
1296 vga_draw_line15_16,
1297 vga_draw_line15_32,
1298 vga_draw_line15_32bgr,
1300 vga_draw_line16_8,
1301 vga_draw_line16_15,
1302 vga_draw_line16_16,
1303 vga_draw_line16_32,
1304 vga_draw_line16_32bgr,
1306 vga_draw_line24_8,
1307 vga_draw_line24_15,
1308 vga_draw_line24_16,
1309 vga_draw_line24_32,
1310 vga_draw_line24_32bgr,
1312 vga_draw_line32_8,
1313 vga_draw_line32_15,
1314 vga_draw_line32_16,
1315 vga_draw_line32_32,
1316 vga_draw_line32_32bgr,
1317 };
1319 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1321 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1322 rgb_to_pixel8_dup,
1323 rgb_to_pixel15_dup,
1324 rgb_to_pixel16_dup,
1325 rgb_to_pixel32_dup,
1326 rgb_to_pixel32bgr_dup,
1327 };
1329 static int vga_get_bpp(VGAState *s)
1331 int ret;
1332 #ifdef CONFIG_BOCHS_VBE
1333 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1334 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1335 } else
1336 #endif
1338 ret = 0;
1340 return ret;
1343 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1345 int width, height;
1347 #ifdef CONFIG_BOCHS_VBE
1348 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1349 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1350 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1351 } else
1352 #endif
1354 width = (s->cr[0x01] + 1) * 8;
1355 height = s->cr[0x12] |
1356 ((s->cr[0x07] & 0x02) << 7) |
1357 ((s->cr[0x07] & 0x40) << 3);
1358 height = (height + 1);
1360 *pwidth = width;
1361 *pheight = height;
1364 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1366 int y;
1367 if (y1 >= VGA_MAX_HEIGHT)
1368 return;
1369 if (y2 >= VGA_MAX_HEIGHT)
1370 y2 = VGA_MAX_HEIGHT;
1371 for(y = y1; y < y2; y++) {
1372 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1376 static inline int cmp_vram(VGAState *s, int offset, int n)
1378 long *vp, *sp;
1380 if (s->vram_shadow == NULL)
1381 return 1;
1382 vp = (long *)(s->vram_ptr + offset);
1383 sp = (long *)(s->vram_shadow + offset);
1384 while ((n -= sizeof(*vp)) >= 0) {
1385 if (*vp++ != *sp++) {
1386 memcpy(sp - 1, vp - 1, n + sizeof(*vp));
1387 return 1;
1390 return 0;
1393 #ifdef USE_SSE2
1395 #include <signal.h>
1396 #include <setjmp.h>
1397 #include <emmintrin.h>
1399 int sse2_ok = 1;
1401 static inline unsigned int cpuid_edx(unsigned int op)
1403 unsigned int eax, edx;
1405 #ifdef __x86_64__
1406 #define __bx "rbx"
1407 #else
1408 #define __bx "ebx"
1409 #endif
1410 __asm__("push %%"__bx"; cpuid; pop %%"__bx
1411 : "=a" (eax), "=d" (edx)
1412 : "0" (op)
1413 : "cx");
1414 #undef __bx
1416 return edx;
1419 jmp_buf sse_jbuf;
1421 void intr(int sig)
1423 sse2_ok = 0;
1424 longjmp(sse_jbuf, 1);
1427 void check_sse2(void)
1429 /* Check 1: What does CPUID say? */
1430 if ((cpuid_edx(1) & 0x4000000) == 0) {
1431 sse2_ok = 0;
1432 return;
1435 /* Check 2: Can we use SSE2 in anger? */
1436 signal(SIGILL, intr);
1437 if (setjmp(sse_jbuf) == 0)
1438 __asm__("xorps %xmm0,%xmm0\n");
1441 int vram_dirty(VGAState *s, int offset, int n)
1443 __m128i *sp, *vp;
1445 if (s->vram_shadow == NULL)
1446 return 1;
1447 if (sse2_ok == 0)
1448 return cmp_vram(s, offset, n);
1449 vp = (__m128i *)(s->vram_ptr + offset);
1450 sp = (__m128i *)(s->vram_shadow + offset);
1451 while ((n -= sizeof(*vp)) >= 0) {
1452 if (_mm_movemask_epi8(_mm_cmpeq_epi8(*sp, *vp)) != 0xffff) {
1453 while (n >= 0) {
1454 _mm_store_si128(sp++, _mm_load_si128(vp++));
1455 n -= sizeof(*vp);
1457 return 1;
1459 sp++;
1460 vp++;
1462 return 0;
1464 #else /* !USE_SSE2 */
1465 int vram_dirty(VGAState *s, int offset, int n)
1467 return cmp_vram(s, offset, n);
1470 void check_sse2(void)
1473 #endif /* !USE_SSE2 */
1475 /*
1476 * graphic modes
1477 */
1478 static void vga_draw_graphic(VGAState *s, int full_update)
1480 int y1, y, update, linesize, y_start, double_scan, mask;
1481 int width, height, shift_control, line_offset, bwidth;
1482 ram_addr_t page0, page1;
1483 int disp_width, multi_scan, multi_run;
1484 uint8_t *d;
1485 uint32_t v, addr1, addr;
1486 vga_draw_line_func *vga_draw_line;
1487 ram_addr_t page_min, page_max;
1489 full_update |= update_basic_params(s);
1491 s->get_resolution(s, &width, &height);
1492 disp_width = width;
1494 shift_control = (s->gr[0x05] >> 5) & 3;
1495 double_scan = (s->cr[0x09] >> 7);
1496 if (shift_control != 1) {
1497 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1498 } else {
1499 /* in CGA modes, multi_scan is ignored */
1500 /* XXX: is it correct ? */
1501 multi_scan = double_scan;
1503 multi_run = multi_scan;
1504 if (shift_control != s->shift_control ||
1505 double_scan != s->double_scan) {
1506 full_update = 1;
1507 s->shift_control = shift_control;
1508 s->double_scan = double_scan;
1511 if (shift_control == 0) {
1512 full_update |= update_palette16(s);
1513 if (s->sr[0x01] & 8) {
1514 v = VGA_DRAW_LINE4D2;
1515 disp_width <<= 1;
1516 } else {
1517 v = VGA_DRAW_LINE4;
1519 } else if (shift_control == 1) {
1520 full_update |= update_palette16(s);
1521 if (s->sr[0x01] & 8) {
1522 v = VGA_DRAW_LINE2D2;
1523 disp_width <<= 1;
1524 } else {
1525 v = VGA_DRAW_LINE2;
1527 } else {
1528 switch(s->get_bpp(s)) {
1529 default:
1530 case 0:
1531 full_update |= update_palette256(s);
1532 v = VGA_DRAW_LINE8D2;
1533 break;
1534 case 8:
1535 full_update |= update_palette256(s);
1536 v = VGA_DRAW_LINE8;
1537 break;
1538 case 15:
1539 v = VGA_DRAW_LINE15;
1540 break;
1541 case 16:
1542 v = VGA_DRAW_LINE16;
1543 break;
1544 case 24:
1545 v = VGA_DRAW_LINE24;
1546 break;
1547 case 32:
1548 v = VGA_DRAW_LINE32;
1549 break;
1552 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1554 if (disp_width != s->last_width ||
1555 height != s->last_height) {
1556 dpy_resize(s->ds, disp_width, height);
1557 s->last_scr_width = disp_width;
1558 s->last_scr_height = height;
1559 s->last_width = disp_width;
1560 s->last_height = height;
1561 full_update = 1;
1563 if (s->cursor_invalidate)
1564 s->cursor_invalidate(s);
1566 line_offset = s->line_offset;
1567 #if 0
1568 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1569 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1570 #endif
1572 for (y = 0; y < s->vram_size; y += TARGET_PAGE_SIZE)
1573 if (vram_dirty(s, y, TARGET_PAGE_SIZE))
1574 cpu_physical_memory_set_dirty(s->vram_offset + y);
1576 addr1 = (s->start_addr * 4);
1577 bwidth = width * 4;
1578 y_start = -1;
1579 page_min = 0;
1580 page_max = 0;
1581 d = s->ds->data;
1582 linesize = s->ds->linesize;
1583 y1 = 0;
1584 for(y = 0; y < height; y++) {
1585 addr = addr1;
1586 if (!(s->cr[0x17] & 1)) {
1587 int shift;
1588 /* CGA compatibility handling */
1589 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1590 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1592 if (!(s->cr[0x17] & 2)) {
1593 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1595 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1596 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1597 update = full_update |
1598 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1599 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1600 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1601 /* if wide line, can use another page */
1602 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1603 VGA_DIRTY_FLAG);
1605 /* explicit invalidation for the hardware cursor */
1606 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1607 if (update) {
1608 if (y_start < 0)
1609 y_start = y;
1610 if (page_min == 0 || page0 < page_min)
1611 page_min = page0;
1612 if (page_max == 0 || page1 > page_max)
1613 page_max = page1;
1614 vga_draw_line(s, d, s->vram_ptr + addr, width);
1615 if (s->cursor_draw_line)
1616 s->cursor_draw_line(s, d, y);
1617 } else {
1618 if (y_start >= 0) {
1619 /* flush to display */
1620 dpy_update(s->ds, 0, y_start,
1621 disp_width, y - y_start);
1622 y_start = -1;
1625 if (!multi_run) {
1626 mask = (s->cr[0x17] & 3) ^ 3;
1627 if ((y1 & mask) == mask)
1628 addr1 += line_offset;
1629 y1++;
1630 multi_run = multi_scan;
1631 } else {
1632 multi_run--;
1634 /* line compare acts on the displayed lines */
1635 if (y == s->line_compare)
1636 addr1 = 0;
1637 d += linesize;
1639 if (y_start >= 0) {
1640 /* flush to display */
1641 dpy_update(s->ds, 0, y_start,
1642 disp_width, y - y_start);
1644 /* reset modified pages */
1645 if (page_max != -1) {
1646 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1647 VGA_DIRTY_FLAG);
1649 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1652 static void vga_draw_blank(VGAState *s, int full_update)
1654 int i, w, val;
1655 uint8_t *d;
1657 if (!full_update)
1658 return;
1659 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1660 return;
1661 if (s->ds->depth == 8)
1662 val = s->rgb_to_pixel(0, 0, 0);
1663 else
1664 val = 0;
1665 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
1666 d = s->ds->data;
1667 for(i = 0; i < s->last_scr_height; i++) {
1668 memset(d, val, w);
1669 d += s->ds->linesize;
1671 dpy_update(s->ds, 0, 0,
1672 s->last_scr_width, s->last_scr_height);
1675 #define GMODE_TEXT 0
1676 #define GMODE_GRAPH 1
1677 #define GMODE_BLANK 2
1679 static void vga_update_display(void *opaque)
1681 VGAState *s = (VGAState *)opaque;
1682 int full_update, graphic_mode;
1684 if (s->ds->depth == 0) {
1685 /* nothing to do */
1686 } else {
1687 s->rgb_to_pixel =
1688 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1690 full_update = 0;
1691 if (!(s->ar_index & 0x20)) {
1692 graphic_mode = GMODE_BLANK;
1693 } else {
1694 graphic_mode = s->gr[6] & 1;
1696 if (graphic_mode != s->graphic_mode) {
1697 s->graphic_mode = graphic_mode;
1698 full_update = 1;
1700 switch(graphic_mode) {
1701 case GMODE_TEXT:
1702 vga_draw_text(s, full_update);
1703 break;
1704 case GMODE_GRAPH:
1705 vga_draw_graphic(s, full_update);
1706 break;
1707 case GMODE_BLANK:
1708 default:
1709 vga_draw_blank(s, full_update);
1710 break;
1715 /* force a full display refresh */
1716 static void vga_invalidate_display(void *opaque)
1718 VGAState *s = (VGAState *)opaque;
1720 s->last_width = -1;
1721 s->last_height = -1;
1724 static void vga_reset(VGAState *s)
1726 memset(s, 0, sizeof(VGAState));
1727 s->graphic_mode = -1; /* force full update */
1730 static CPUReadMemoryFunc *vga_mem_read[3] = {
1731 vga_mem_readb,
1732 vga_mem_readw,
1733 vga_mem_readl,
1734 };
1736 static CPUWriteMemoryFunc *vga_mem_write[3] = {
1737 vga_mem_writeb,
1738 vga_mem_writew,
1739 vga_mem_writel,
1740 };
1742 static void vga_save(QEMUFile *f, void *opaque)
1744 VGAState *s = opaque;
1745 #ifdef CONFIG_BOCHS_VBE
1746 int i;
1747 #endif
1749 if (s->pci_dev)
1750 pci_device_save(s->pci_dev, f);
1752 qemu_put_be32s(f, &s->latch);
1753 qemu_put_8s(f, &s->sr_index);
1754 qemu_put_buffer(f, s->sr, 8);
1755 qemu_put_8s(f, &s->gr_index);
1756 qemu_put_buffer(f, s->gr, 16);
1757 qemu_put_8s(f, &s->ar_index);
1758 qemu_put_buffer(f, s->ar, 21);
1759 qemu_put_be32s(f, &s->ar_flip_flop);
1760 qemu_put_8s(f, &s->cr_index);
1761 qemu_put_buffer(f, s->cr, 256);
1762 qemu_put_8s(f, &s->msr);
1763 qemu_put_8s(f, &s->fcr);
1764 qemu_put_8s(f, &s->st00);
1765 qemu_put_8s(f, &s->st01);
1767 qemu_put_8s(f, &s->dac_state);
1768 qemu_put_8s(f, &s->dac_sub_index);
1769 qemu_put_8s(f, &s->dac_read_index);
1770 qemu_put_8s(f, &s->dac_write_index);
1771 qemu_put_buffer(f, s->dac_cache, 3);
1772 qemu_put_buffer(f, s->palette, 768);
1774 qemu_put_be32s(f, &s->bank_offset);
1775 #ifdef CONFIG_BOCHS_VBE
1776 qemu_put_byte(f, 1);
1777 qemu_put_be16s(f, &s->vbe_index);
1778 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1779 qemu_put_be16s(f, &s->vbe_regs[i]);
1780 qemu_put_be32s(f, &s->vbe_start_addr);
1781 qemu_put_be32s(f, &s->vbe_line_offset);
1782 qemu_put_be32s(f, &s->vbe_bank_mask);
1783 #else
1784 qemu_put_byte(f, 0);
1785 #endif
1788 static int vga_load(QEMUFile *f, void *opaque, int version_id)
1790 VGAState *s = opaque;
1791 int is_vbe, ret;
1792 #ifdef CONFIG_BOCHS_VBE
1793 int i;
1794 #endif
1796 if (version_id > 2)
1797 return -EINVAL;
1799 if (s->pci_dev && version_id >= 2) {
1800 ret = pci_device_load(s->pci_dev, f);
1801 if (ret < 0)
1802 return ret;
1805 qemu_get_be32s(f, &s->latch);
1806 qemu_get_8s(f, &s->sr_index);
1807 qemu_get_buffer(f, s->sr, 8);
1808 qemu_get_8s(f, &s->gr_index);
1809 qemu_get_buffer(f, s->gr, 16);
1810 qemu_get_8s(f, &s->ar_index);
1811 qemu_get_buffer(f, s->ar, 21);
1812 qemu_get_be32s(f, &s->ar_flip_flop);
1813 qemu_get_8s(f, &s->cr_index);
1814 qemu_get_buffer(f, s->cr, 256);
1815 qemu_get_8s(f, &s->msr);
1816 qemu_get_8s(f, &s->fcr);
1817 qemu_get_8s(f, &s->st00);
1818 qemu_get_8s(f, &s->st01);
1820 qemu_get_8s(f, &s->dac_state);
1821 qemu_get_8s(f, &s->dac_sub_index);
1822 qemu_get_8s(f, &s->dac_read_index);
1823 qemu_get_8s(f, &s->dac_write_index);
1824 qemu_get_buffer(f, s->dac_cache, 3);
1825 qemu_get_buffer(f, s->palette, 768);
1827 qemu_get_be32s(f, &s->bank_offset);
1828 is_vbe = qemu_get_byte(f);
1829 #ifdef CONFIG_BOCHS_VBE
1830 if (!is_vbe)
1831 return -EINVAL;
1832 qemu_get_be16s(f, &s->vbe_index);
1833 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1834 qemu_get_be16s(f, &s->vbe_regs[i]);
1835 qemu_get_be32s(f, &s->vbe_start_addr);
1836 qemu_get_be32s(f, &s->vbe_line_offset);
1837 qemu_get_be32s(f, &s->vbe_bank_mask);
1838 #else
1839 if (is_vbe)
1840 return -EINVAL;
1841 #endif
1843 /* force refresh */
1844 s->graphic_mode = -1;
1845 return 0;
1848 typedef struct PCIVGAState {
1849 PCIDevice dev;
1850 VGAState vga_state;
1851 } PCIVGAState;
1853 static void vga_map(PCIDevice *pci_dev, int region_num,
1854 uint32_t addr, uint32_t size, int type)
1856 PCIVGAState *d = (PCIVGAState *)pci_dev;
1857 VGAState *s = &d->vga_state;
1858 if (region_num == PCI_ROM_SLOT) {
1859 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
1860 } else {
1861 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
1865 /* do the same job as vgabios before vgabios get ready - yeah */
1866 void vga_bios_init(VGAState *s)
1868 uint8_t palette_model[192] = {
1869 0, 0, 0, 0, 0, 170, 0, 170,
1870 0, 0, 170, 170, 170, 0, 0, 170,
1871 0, 170, 170, 85, 0, 170, 170, 170,
1872 85, 85, 85, 85, 85, 255, 85, 255,
1873 85, 85, 255, 255, 255, 85, 85, 255,
1874 85, 255, 255, 255, 85, 255, 255, 255,
1875 0, 21, 0, 0, 21, 42, 0, 63,
1876 0, 0, 63, 42, 42, 21, 0, 42,
1877 21, 42, 42, 63, 0, 42, 63, 42,
1878 0, 21, 21, 0, 21, 63, 0, 63,
1879 21, 0, 63, 63, 42, 21, 21, 42,
1880 21, 63, 42, 63, 21, 42, 63, 63,
1881 21, 0, 0, 21, 0, 42, 21, 42,
1882 0, 21, 42, 42, 63, 0, 0, 63,
1883 0, 42, 63, 42, 0, 63, 42, 42,
1884 21, 0, 21, 21, 0, 63, 21, 42,
1885 21, 21, 42, 63, 63, 0, 21, 63,
1886 0, 63, 63, 42, 21, 63, 42, 63,
1887 21, 21, 0, 21, 21, 42, 21, 63,
1888 0, 21, 63, 42, 63, 21, 0, 63,
1889 21, 42, 63, 63, 0, 63, 63, 42,
1890 21, 21, 21, 21, 21, 63, 21, 63,
1891 21, 21, 63, 63, 63, 21, 21, 63,
1892 21, 63, 63, 63, 21, 63, 63, 63
1893 };
1895 s->latch = 0;
1897 s->sr_index = 3;
1898 s->sr[0] = 3;
1899 s->sr[1] = 0;
1900 s->sr[2] = 3;
1901 s->sr[3] = 0;
1902 s->sr[4] = 2;
1903 s->sr[5] = 0;
1904 s->sr[6] = 0;
1905 s->sr[7] = 0;
1907 s->gr_index = 5;
1908 s->gr[0] = 0;
1909 s->gr[1] = 0;
1910 s->gr[2] = 0;
1911 s->gr[3] = 0;
1912 s->gr[4] = 0;
1913 s->gr[5] = 16;
1914 s->gr[6] = 14;
1915 s->gr[7] = 15;
1916 s->gr[8] = 255;
1918 /* changed by out 0x03c0 */
1919 s->ar_index = 32;
1920 s->ar[0] = 0;
1921 s->ar[1] = 1;
1922 s->ar[2] = 2;
1923 s->ar[3] = 3;
1924 s->ar[4] = 4;
1925 s->ar[5] = 5;
1926 s->ar[6] = 6;
1927 s->ar[7] = 7;
1928 s->ar[8] = 8;
1929 s->ar[9] = 9;
1930 s->ar[10] = 10;
1931 s->ar[11] = 11;
1932 s->ar[12] = 12;
1933 s->ar[13] = 13;
1934 s->ar[14] = 14;
1935 s->ar[15] = 15;
1936 s->ar[16] = 12;
1937 s->ar[17] = 0;
1938 s->ar[18] = 15;
1939 s->ar[19] = 8;
1940 s->ar[20] = 0;
1942 s->ar_flip_flop = 1;
1944 s->cr_index = 15;
1945 s->cr[0] = 95;
1946 s->cr[1] = 79;
1947 s->cr[2] = 80;
1948 s->cr[3] = 130;
1949 s->cr[4] = 85;
1950 s->cr[5] = 129;
1951 s->cr[6] = 191;
1952 s->cr[7] = 31;
1953 s->cr[8] = 0;
1954 s->cr[9] = 79;
1955 s->cr[10] = 14;
1956 s->cr[11] = 15;
1957 s->cr[12] = 0;
1958 s->cr[13] = 0;
1959 s->cr[14] = 5;
1960 s->cr[15] = 160;
1961 s->cr[16] = 156;
1962 s->cr[17] = 142;
1963 s->cr[18] = 143;
1964 s->cr[19] = 40;
1965 s->cr[20] = 31;
1966 s->cr[21] = 150;
1967 s->cr[22] = 185;
1968 s->cr[23] = 163;
1969 s->cr[24] = 255;
1971 s->msr = 103;
1972 s->fcr = 0;
1973 s->st00 = 0;
1974 s->st01 = 0;
1976 /* dac_* & palette will be initialized by os through out 0x03c8 &
1977 * out 0c03c9(1:3) */
1978 s->dac_state = 0;
1979 s->dac_sub_index = 0;
1980 s->dac_read_index = 0;
1981 s->dac_write_index = 16;
1982 s->dac_cache[0] = 255;
1983 s->dac_cache[1] = 255;
1984 s->dac_cache[2] = 255;
1986 /* palette */
1987 memcpy(s->palette, palette_model, 192);
1989 s->bank_offset = 0;
1990 s->graphic_mode = -1;
1992 /* TODO: add vbe support if enabled */
1995 /* when used on xen environment, the vga_ram_base is not used */
1996 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
1997 unsigned long vga_ram_offset, int vga_ram_size)
1999 int i, j, v, b;
2001 for(i = 0;i < 256; i++) {
2002 v = 0;
2003 for(j = 0; j < 8; j++) {
2004 v |= ((i >> j) & 1) << (j * 4);
2006 expand4[i] = v;
2008 v = 0;
2009 for(j = 0; j < 4; j++) {
2010 v |= ((i >> (2 * j)) & 3) << (j * 4);
2012 expand2[i] = v;
2014 for(i = 0; i < 16; i++) {
2015 v = 0;
2016 for(j = 0; j < 4; j++) {
2017 b = ((i >> j) & 1);
2018 v |= b << (2 * j);
2019 v |= b << (2 * j + 1);
2021 expand4to8[i] = v;
2024 vga_reset(s);
2026 check_sse2();
2027 s->vram_shadow = qemu_malloc(vga_ram_size+TARGET_PAGE_SIZE+1);
2028 if (s->vram_shadow == NULL)
2029 fprintf(stderr, "Cannot allocate %d bytes for VRAM shadow, "
2030 "mouse will be slow\n", vga_ram_size);
2031 s->vram_shadow = (uint8_t *)((long)(s->vram_shadow + TARGET_PAGE_SIZE - 1)
2032 & ~(TARGET_PAGE_SIZE - 1));
2034 /* Video RAM must be 128-bit aligned for SSE optimizations later */
2035 s->vram_alloc = qemu_malloc(vga_ram_size + 15);
2036 s->vram_ptr = (uint8_t *)((long)(s->vram_alloc + 15) & ~15L);
2038 s->vram_offset = vga_ram_offset;
2039 s->vram_size = vga_ram_size;
2040 s->ds = ds;
2041 s->get_bpp = vga_get_bpp;
2042 s->get_offsets = vga_get_offsets;
2043 s->get_resolution = vga_get_resolution;
2044 graphic_console_init(s->ds, vga_update_display, vga_invalidate_display,
2045 vga_screen_dump, s);
2047 vga_bios_init(s);
2050 /* used by both ISA and PCI */
2051 static void vga_init(VGAState *s)
2053 int vga_io_memory;
2055 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2057 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2059 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2060 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2061 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2062 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2064 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2066 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2067 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2068 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2069 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2070 s->bank_offset = 0;
2072 #ifdef CONFIG_BOCHS_VBE
2073 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2074 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2075 #if defined (TARGET_I386)
2076 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2077 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2079 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2080 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2082 /* old Bochs IO ports */
2083 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2084 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2086 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2087 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2088 #else
2089 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2090 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2092 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2093 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2094 #endif
2095 #endif /* CONFIG_BOCHS_VBE */
2097 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2098 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2099 vga_io_memory);
2102 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2103 unsigned long vga_ram_offset, int vga_ram_size)
2105 VGAState *s;
2107 s = qemu_mallocz(sizeof(VGAState));
2108 if (!s)
2109 return -1;
2111 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2112 vga_init(s);
2114 #ifdef CONFIG_BOCHS_VBE
2115 /* XXX: use optimized standard vga accesses */
2116 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2117 vga_ram_size, vga_ram_offset);
2118 #endif
2119 return 0;
2122 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2123 unsigned long vga_ram_offset, int vga_ram_size,
2124 unsigned long vga_bios_offset, int vga_bios_size)
2126 PCIVGAState *d;
2127 VGAState *s;
2128 uint8_t *pci_conf;
2130 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2131 sizeof(PCIVGAState),
2132 -1, NULL, NULL);
2133 if (!d)
2134 return -1;
2135 s = &d->vga_state;
2137 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2138 vga_init(s);
2139 s->pci_dev = &d->dev;
2141 pci_conf = d->dev.config;
2142 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2143 pci_conf[0x01] = 0x12;
2144 pci_conf[0x02] = 0x11;
2145 pci_conf[0x03] = 0x11;
2146 pci_conf[0x0a] = 0x00; // VGA controller
2147 pci_conf[0x0b] = 0x03;
2148 pci_conf[0x0e] = 0x00; // header_type
2150 /* XXX: vga_ram_size must be a power of two */
2151 pci_register_io_region(&d->dev, 0, vga_ram_size,
2152 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2153 if (vga_bios_size != 0) {
2154 unsigned int bios_total_size;
2155 s->bios_offset = vga_bios_offset;
2156 s->bios_size = vga_bios_size;
2157 /* must be a power of two */
2158 bios_total_size = 1;
2159 while (bios_total_size < vga_bios_size)
2160 bios_total_size <<= 1;
2161 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2162 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2164 return 0;
2167 void *vga_update_vram(VGAState *s, void *vga_ram_base, int vga_ram_size)
2169 uint8_t *old_pointer;
2171 if (s->vram_size != vga_ram_size) {
2172 fprintf(stderr, "No support to change vga_ram_size\n");
2173 return NULL;
2176 if (!vga_ram_base) {
2177 vga_ram_base = qemu_malloc(vga_ram_size + TARGET_PAGE_SIZE + 1);
2178 if (!vga_ram_base) {
2179 fprintf(stderr, "reallocate error\n");
2180 return NULL;
2184 /* XXX lock needed? */
2185 old_pointer = s->vram_alloc;
2186 s->vram_alloc = vga_ram_base;
2187 vga_ram_base = (uint8_t *)((long)(vga_ram_base + 15) & ~15L);
2188 memcpy(vga_ram_base, s->vram_ptr, vga_ram_size);
2189 s->vram_ptr = vga_ram_base;
2191 return old_pointer;
2194 /********************************************************/
2195 /* vga screen dump */
2197 static int vga_save_w, vga_save_h;
2199 static void vga_save_dpy_update(DisplayState *s,
2200 int x, int y, int w, int h)
2204 static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2206 s->linesize = w * 4;
2207 s->data = qemu_malloc(h * s->linesize);
2208 vga_save_w = w;
2209 vga_save_h = h;
2212 static void vga_save_dpy_refresh(DisplayState *s)
2216 static int ppm_save(const char *filename, uint8_t *data,
2217 int w, int h, int linesize)
2219 FILE *f;
2220 uint8_t *d, *d1;
2221 unsigned int v;
2222 int y, x;
2224 f = fopen(filename, "wb");
2225 if (!f)
2226 return -1;
2227 fprintf(f, "P6\n%d %d\n%d\n",
2228 w, h, 255);
2229 d1 = data;
2230 for(y = 0; y < h; y++) {
2231 d = d1;
2232 for(x = 0; x < w; x++) {
2233 v = *(uint32_t *)d;
2234 fputc((v >> 16) & 0xff, f);
2235 fputc((v >> 8) & 0xff, f);
2236 fputc((v) & 0xff, f);
2237 d += 4;
2239 d1 += linesize;
2241 fclose(f);
2242 return 0;
2245 /* save the vga display in a PPM image even if no display is
2246 available */
2247 static void vga_screen_dump(void *opaque, const char *filename)
2249 VGAState *s = (VGAState *)opaque;
2250 DisplayState *saved_ds, ds1, *ds = &ds1;
2252 /* XXX: this is a little hackish */
2253 vga_invalidate_display(s);
2254 saved_ds = s->ds;
2256 memset(ds, 0, sizeof(DisplayState));
2257 ds->dpy_update = vga_save_dpy_update;
2258 ds->dpy_resize = vga_save_dpy_resize;
2259 ds->dpy_refresh = vga_save_dpy_refresh;
2260 ds->depth = 32;
2262 s->ds = ds;
2263 s->graphic_mode = -1;
2264 vga_update_display(s);
2266 if (ds->data) {
2267 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2268 s->ds->linesize);
2269 qemu_free(ds->data);
2271 s->ds = saved_ds;