debuggers.hg

view tools/ioemu/patches/acpi-support @ 10972:56b2a028dc7e

[qemu patches] Update patches for changeset 10933:386990d004b8.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Fri Aug 04 10:42:02 2006 +0100 (2006-08-04)
parents b450f21472a0
children ec8dd0528fc6
line source
1 Index: ioemu/Makefile.target
2 ===================================================================
3 --- ioemu.orig/Makefile.target 2006-08-03 19:19:39.000000000 +0100
4 +++ ioemu/Makefile.target 2006-08-04 10:35:36.445703379 +0100
5 @@ -335,6 +335,7 @@
6 VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
7 VL_OBJS+= fdc.o mc146818rtc.o serial.o pc.o
8 VL_OBJS+= cirrus_vga.o mixeng.o parallel.o
9 +VL_OBJS+= piix4acpi.o
10 DEFINES += -DHAS_AUDIO
11 endif
12 ifeq ($(TARGET_BASE_ARCH), ppc)
13 Index: ioemu/hw/pc.c
14 ===================================================================
15 --- ioemu.orig/hw/pc.c 2006-08-03 19:19:39.000000000 +0100
16 +++ ioemu/hw/pc.c 2006-08-04 10:38:05.559415853 +0100
17 @@ -566,6 +566,9 @@
18 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
19 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
21 +/* PIIX4 acpi pci configuration space, func 3 */
22 +extern void pci_piix4_acpi_init(PCIBus *bus);
23 +
24 #ifdef HAS_AUDIO
25 static void audio_init (PCIBus *pci_bus)
26 {
27 @@ -867,6 +870,10 @@
29 cmos_init(ram_size, boot_device, bs_table, timeoffset);
31 + /* using PIIX4 acpi model */
32 + if (pci_enabled && acpi_enabled)
33 + pci_piix4_acpi_init(pci_bus);
34 +
35 if (pci_enabled && usb_enabled) {
36 usb_uhci_init(pci_bus, usb_root_ports);
37 usb_attach(usb_root_ports[0], vm_usb_hub);
38 Index: ioemu/hw/pci.c
39 ===================================================================
40 --- ioemu.orig/hw/pci.c 2006-08-03 19:19:35.000000000 +0100
41 +++ ioemu/hw/pci.c 2006-08-03 19:19:39.000000000 +0100
42 @@ -1697,7 +1697,7 @@
43 static uint32_t pci_bios_io_addr;
44 static uint32_t pci_bios_mem_addr;
45 /* host irqs corresponding to PCI irqs A-D */
46 -static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
47 +static uint8_t pci_irqs[4] = { 10, 11, 10, 11 };
49 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
50 {
51 @@ -1750,12 +1750,22 @@
52 pci_set_io_region_addr(d, 3, 0x374);
53 }
54 break;
55 + case 0x0680:
56 + if (vendor_id == 0x8086 && device_id == 0x7113) {
57 + // PIIX4 ACPI PM
58 + pci_config_writew(d, 0x20, 0x0000); // NO smb bus IO enable in PIIX4
59 + pci_config_writew(d, 0x22, 0x0000);
60 + goto default_map;
61 + }
62 + break;
63 +
64 case 0x0300:
65 if (vendor_id != 0x1234)
66 goto default_map;
67 /* VGA: map frame buffer to default Bochs VBE address */
68 pci_set_io_region_addr(d, 0, 0xE0000000);
69 break;
70 +
71 case 0x0800:
72 /* PIC */
73 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
74 @@ -1800,6 +1810,13 @@
75 pic_irq = pci_irqs[pin];
76 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
77 }
78 + if (class== 0x0680&& vendor_id == 0x8086 && device_id == 0x7113) {
79 + // PIIX4 ACPI PM
80 + pci_config_writew(d, 0x20, 0x0000); // NO smb bus IO enable in PIIX4
81 + pci_config_writew(d, 0x22, 0x0000);
82 + pci_config_writew(d, 0x3c, 0x0009); // Hardcodeed IRQ9
83 + pci_config_writew(d, 0x3d, 0x0001);
84 + }
85 }
87 /*
88 Index: ioemu/hw/piix4acpi.c
89 ===================================================================
90 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
91 +++ ioemu/hw/piix4acpi.c 2006-08-04 10:35:36.762666604 +0100
92 @@ -0,0 +1,388 @@
93 +/*
94 + * PIIX4 ACPI controller emulation
95 + *
96 + * Winston liwen Wang, winston.l.wang@intel.com
97 + * Copyright (c) 2006 , Intel Corporation.
98 + *
99 + * Permission is hereby granted, free of charge, to any person obtaining a copy
100 + * of this software and associated documentation files (the "Software"), to deal
101 + * in the Software without restriction, including without limitation the rights
102 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
103 + * copies of the Software, and to permit persons to whom the Software is
104 + * furnished to do so, subject to the following conditions:
105 + *
106 + * The above copyright notice and this permission notice shall be included in
107 + * all copies or substantial portions of the Software.
108 + *
109 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
110 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
111 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
112 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
113 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
114 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
115 + * THE SOFTWARE.
116 + */
117 +
118 +#include "vl.h"
119 +#define FREQUENCE_PMTIMER 3753425
120 +/* acpi register bit define here */
121 +
122 +/* PM1_STS */
123 +#define TMROF_STS (1 << 0)
124 +#define BM_STS (1 << 4)
125 +#define GBL_STS (1 << 5)
126 +#define PWRBTN_STS (1 << 8)
127 +#define RTC_STS (1 << 10)
128 +#define PRBTNOR_STS (1 << 11)
129 +#define WAK_STS (1 << 15)
130 +/* PM1_EN */
131 +#define TMROF_EN (1 << 0)
132 +#define GBL_EN (1 << 5)
133 +#define PWRBTN_EN (1 << 8)
134 +#define RTC_EN (1 << 10)
135 +/* PM1_CNT */
136 +#define SCI_EN (1 << 0)
137 +#define GBL_RLS (1 << 2)
138 +#define SLP_EN (1 << 13)
139 +
140 +typedef struct AcpiDeviceState AcpiDeviceState;
141 +AcpiDeviceState *acpi_device_table;
142 +
143 +/* Bits of PM1a register define here */
144 +typedef struct PM1Event_BLK {
145 + uint16_t pm1_status; /* pm1a_EVT_BLK */
146 + uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
147 +}PM1Event_BLK;
148 +
149 +typedef struct PCIAcpiState {
150 + PCIDevice dev;
151 + uint16_t irq;
152 + uint16_t pm1_status; /* pm1a_EVT_BLK */
153 + uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
154 + uint16_t pm1_control; /* pm1a_ECNT_BLK */
155 + uint32_t pm1_timer; /* pmtmr_BLK */
156 +} PCIAcpiState;
157 +
158 +static PCIAcpiState *acpi_state;
159 +
160 +static inline void acpi_set_irq(PCIAcpiState *s)
161 +{
162 +/* no real SCI event need for now, so comment the following line out */
163 +/* pic_set_irq(s->irq, 1); */
164 + printf("acpi_set_irq: s->irq %x \n",s->irq);
165 +}
166 +
167 +static void acpi_reset(PCIAcpiState *s)
168 +{
169 + uint8_t *pci_conf;
170 + pci_conf = s->dev.config;
171 +
172 + pci_conf[0x42] = 0x00;
173 + pci_conf[0x43] = 0x00;
174 + s->irq = 9;
175 + s->pm1_status = 0;
176 + s->pm1_enable = 0x00; /* TMROF_EN should cleared */
177 + s->pm1_control = SCI_EN; /* SCI_EN */
178 + s->pm1_timer = 0;
179 +}
180 +
181 +/*byte access */
182 +static void acpiPm1Status_writeb(void *opaque, uint32_t addr, uint32_t val)
183 +{
184 + PCIAcpiState *s = opaque;
185 +
186 + if ((val&TMROF_STS)==TMROF_STS)
187 + s->pm1_status = s->pm1_status&!TMROF_STS;
188 +
189 + if ((val&GBL_STS)==GBL_STS)
190 + s->pm1_status = s->pm1_status&!GBL_STS;
191 +
192 +/* printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
193 +}
194 +
195 +static uint32_t acpiPm1Status_readb(void *opaque, uint32_t addr)
196 +{
197 + PCIAcpiState *s = opaque;
198 + uint32_t val;
199 +
200 + val = s->pm1_status;
201 +/* printf("acpiPm1Status_readb \n addr %x val:%x\n", addr, val); */
202 +
203 + return val;
204 +}
205 +
206 +static void acpiPm1StatusP1_writeb(void *opaque, uint32_t addr, uint32_t val)
207 +{
208 + PCIAcpiState *s = opaque;
209 +
210 + s->pm1_status = (val<<8)||(s->pm1_status);
211 +/* printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */
212 +}
213 +
214 +static uint32_t acpiPm1StatusP1_readb(void *opaque, uint32_t addr)
215 +{
216 + PCIAcpiState *s = opaque;
217 + uint32_t val;
218 +
219 + val = (s->pm1_status)>>8;
220 + printf("acpiPm1StatusP1_readb \n addr %x val:%x\n", addr, val);
221 +
222 + return val;
223 +}
224 +
225 +static void acpiPm1Enable_writeb(void *opaque, uint32_t addr, uint32_t val)
226 +{
227 + PCIAcpiState *s = opaque;
228 +
229 + s->pm1_enable = val;
230 +/* printf("acpiPm1Enable_writeb \n addr %x val:%x\n", addr, val); */
231 +}
232 +
233 +static uint32_t acpiPm1Enable_readb(void *opaque, uint32_t addr)
234 +{
235 + PCIAcpiState *s = opaque;
236 + uint32_t val;
237 +
238 + val = (s->pm1_enable)||0x1;
239 +/* printf("acpiPm1Enable_readb \n addr %x val:%x\n", addr, val); */
240 +
241 + return val;
242 +}
243 +
244 +static void acpiPm1EnableP1_writeb(void *opaque, uint32_t addr, uint32_t val)
245 +{
246 + PCIAcpiState *s = opaque;
247 +
248 + s->pm1_enable = (val<<8)||(s->pm1_enable);
249 +/* printf("acpiPm1EnableP1_writeb \n addr %x val:%x\n", addr, val); */
250 +
251 +}
252 +
253 +static uint32_t acpiPm1EnableP1_readb(void *opaque, uint32_t addr)
254 +{
255 + PCIAcpiState *s = opaque;
256 + uint32_t val;
257 +
258 + val = (s->pm1_enable)>>8;
259 +/* printf("acpiPm1EnableP1_readb \n addr %x val:%x\n", addr, val); */
260 +
261 + return val;
262 +}
263 +
264 +static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val)
265 +{
266 + PCIAcpiState *s = opaque;
267 +
268 + s->pm1_control = val;
269 +/* printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */
270 +
271 +}
272 +
273 +static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr)
274 +{
275 + PCIAcpiState *s = opaque;
276 + uint32_t val;
277 +
278 + val = s->pm1_control;
279 +/* printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */
280 +
281 + return val;
282 +}
283 +
284 +static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val)
285 +{
286 + PCIAcpiState *s = opaque;
287 +
288 + s->pm1_control = (val<<8)||(s->pm1_control);
289 +/* printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */
290 +
291 +}
292 +
293 +static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr)
294 +{
295 + PCIAcpiState *s = opaque;
296 + uint32_t val;
297 +
298 + val = (s->pm1_control)>>8;
299 +/* printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */
300 +
301 + return val;
302 +}
303 +
304 +
305 +/* word access */
306 +
307 +static void acpiPm1Status_writew(void *opaque, uint32_t addr, uint32_t val)
308 +{
309 + PCIAcpiState *s = opaque;
310 +
311 + if ((val&TMROF_STS)==TMROF_STS)
312 + s->pm1_status = s->pm1_status&!TMROF_STS;
313 +
314 + if ((val&GBL_STS)==GBL_STS)
315 + s->pm1_status = s->pm1_status&!GBL_STS;
316 +
317 +/* printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
318 +}
319 +
320 +static uint32_t acpiPm1Status_readw(void *opaque, uint32_t addr)
321 +{
322 + PCIAcpiState *s = opaque;
323 + uint32_t val;
324 +
325 + val = s->pm1_status;
326 +/* printf("acpiPm1Status_readw \n addr %x val:%x\n", addr, val); */
327 +
328 + return val;
329 +}
330 +
331 +static void acpiPm1Enable_writew(void *opaque, uint32_t addr, uint32_t val)
332 +{
333 + PCIAcpiState *s = opaque;
334 +
335 + s->pm1_enable = val;
336 +/* printf("acpiPm1Enable_writew \n addr %x val:%x\n", addr, val); */
337 +
338 +}
339 +
340 +static uint32_t acpiPm1Enable_readw(void *opaque, uint32_t addr)
341 +{
342 + PCIAcpiState *s = opaque;
343 + uint32_t val;
344 +
345 + val = s->pm1_enable;
346 +/* printf("acpiPm1Enable_readw \n addr %x val:%x\n", addr, val); */
347 +
348 + return val;
349 +}
350 +
351 +static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
352 +{
353 + PCIAcpiState *s = opaque;
354 +
355 + s->pm1_control = val;
356 +/* printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */
357 +
358 +}
359 +
360 +static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr)
361 +{
362 + PCIAcpiState *s = opaque;
363 + uint32_t val;
364 +
365 + val = s->pm1_control;
366 +/* printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val); */
367 +
368 + return val;
369 +}
370 +
371 +/* dword access */
372 +
373 +static void acpiPm1Event_writel(void *opaque, uint32_t addr, uint32_t val)
374 +{
375 + PCIAcpiState *s = opaque;
376 +
377 + s->pm1_status = val;
378 + s->pm1_enable = val>>16;
379 +/* printf("acpiPm1Event_writel \n addr %x val:%x \n", addr, val); */
380 +
381 +}
382 +
383 +static void acpiPm1Event_readl(void *opaque, uint32_t addr)
384 +{
385 + PCIAcpiState *s = opaque;
386 + uint32_t val;
387 +
388 + val=s->pm1_status|(s->pm1_enable<<16);
389 +/* printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val); */
390 +}
391 +
392 +static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val)
393 +{
394 + PCIAcpiState *s = opaque;
395 +
396 + s->pm1_timer = val;
397 +/* printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */
398 +}
399 +
400 +static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr)
401 +{
402 + PCIAcpiState *s = opaque;
403 + uint32_t val;
404 +
405 + val = s->pm1_timer;
406 +/* printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */
407 + return val;
408 +}
409 +
410 +static void acpi_map(PCIDevice *pci_dev, int region_num,
411 + uint32_t addr, uint32_t size, int type)
412 +{
413 + PCIAcpiState *d = (PCIAcpiState *)pci_dev;
414 +
415 + printf("register acpi io \n");
416 +
417 + /* Byte access */
418 + register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d);
419 + register_ioport_read(addr, 1, 1, acpiPm1Status_readb, d);
420 + register_ioport_write(addr+1, 1, 1, acpiPm1StatusP1_writeb, d);
421 + register_ioport_read(addr+1, 1, 1, acpiPm1StatusP1_readb, d);
422 +
423 + register_ioport_write(addr + 2, 1, 1, acpiPm1Enable_writeb, d);
424 + register_ioport_read(addr + 2, 1, 1, acpiPm1Enable_readb, d);
425 + register_ioport_write(addr + 2 +1, 1, 1, acpiPm1EnableP1_writeb, d);
426 + register_ioport_read(addr + 2 +1, 1, 1, acpiPm1EnableP1_readb, d);
427 +
428 + register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
429 + register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
430 + register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
431 + register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
432 +
433 + /* Word access */
434 + register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d);
435 + register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d);
436 +
437 + register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d);
438 + register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d);
439 +
440 + register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
441 + register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
442 +
443 + /* DWord access */
444 + register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d);
445 + register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d);
446 +
447 + register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d);
448 + register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d);
449 +}
450 +
451 +
452 +/* PIIX4 acpi pci configuration space, func 3 */
453 +void pci_piix4_acpi_init(PCIBus *bus)
454 +{
455 + PCIAcpiState *d;
456 + uint8_t *pci_conf;
457 +
458 + /* register a function 3 of PIIX4 */
459 + d = (PCIAcpiState *)pci_register_device(
460 + bus, "PIIX4 ACPI", sizeof(PCIAcpiState),
461 + ((PCIDevice *)piix3_state)->devfn + 3, NULL, NULL);
462 +
463 + acpi_state = d;
464 + pci_conf = d->dev.config;
465 + pci_conf[0x00] = 0x86; /* Intel */
466 + pci_conf[0x01] = 0x80;
467 + pci_conf[0x02] = 0x13;
468 + pci_conf[0x03] = 0x71;
469 + pci_conf[0x08] = 0x01; /* B0 stepping */
470 + pci_conf[0x09] = 0x00; /* base class */
471 + pci_conf[0x0a] = 0x80; /* Sub class */
472 + pci_conf[0x0b] = 0x06;
473 + pci_conf[0x0e] = 0x00;
474 + pci_conf[0x3d] = 0x01; /* Hardwired to PIRQA is used */
475 +
476 + pci_register_io_region((PCIDevice *)d, 4, 0x10,
477 + PCI_ADDRESS_SPACE_IO, acpi_map);
478 +
479 + acpi_reset (d);
480 +}
481 Index: ioemu/vl.c
482 ===================================================================
483 --- ioemu.orig/vl.c 2006-08-04 10:35:36.697674145 +0100
484 +++ ioemu/vl.c 2006-08-04 10:37:38.001608828 +0100
485 @@ -166,6 +166,8 @@
487 time_t timeoffset = 0;
489 +int acpi_enabled = 0;
490 +
491 char domain_name[1024] = { 'H','V', 'M', 'X', 'E', 'N', '-'};
492 extern int domid;
494 @@ -4803,6 +4805,7 @@
495 "-loadvm file start right away with a saved state (loadvm in monitor)\n"
496 "-vnc display start a VNC server on display\n"
497 "-timeoffset time offset (in seconds) from local time\n"
498 + "-acpi disable or enable ACPI of HVM domain \n"
499 "\n"
500 "During emulation, the following keys are useful:\n"
501 "ctrl-alt-f toggle full screen\n"
502 @@ -4894,6 +4897,7 @@
503 QEMU_OPTION_d,
504 QEMU_OPTION_vcpus,
505 QEMU_OPTION_timeoffset,
506 + QEMU_OPTION_acpi,
507 };
509 typedef struct QEMUOption {
510 @@ -4973,6 +4977,7 @@
511 { "d", HAS_ARG, QEMU_OPTION_d },
512 { "vcpus", 1, QEMU_OPTION_vcpus },
513 { "timeoffset", HAS_ARG, QEMU_OPTION_timeoffset },
514 + { "acpi", 0, QEMU_OPTION_acpi },
515 { NULL },
516 };
518 @@ -5678,6 +5683,9 @@
519 case QEMU_OPTION_timeoffset:
520 timeoffset = strtol(optarg, NULL, 0);
521 break;
522 + case QEMU_OPTION_acpi:
523 + acpi_enabled = 1;
524 + break;
525 }
526 }
527 }
528 Index: ioemu/vl.h
529 ===================================================================
530 --- ioemu.orig/vl.h 2006-08-04 10:35:36.629682033 +0100
531 +++ ioemu/vl.h 2006-08-04 10:36:21.513475699 +0100
532 @@ -159,6 +159,7 @@
533 extern int kqemu_allowed;
534 extern int win2k_install_hack;
535 extern int usb_enabled;
536 +extern int acpi_enabled;
537 extern int smp_cpus;
539 /* XXX: make it dynamic */