debuggers.hg

view xen/arch/x86/x86_32/asm-offsets.c @ 3634:578b6c14e635

bitkeeper revision 1.1159.212.61 (41ff4ae9QGwwPUv_OONjfk2SaSj0dw)

Merge scramble.cl.cam.ac.uk:/local/scratch/kaf24/xen-2.0-testing.bk
into scramble.cl.cam.ac.uk:/local/scratch/kaf24/xen-unstable.bk
author kaf24@scramble.cl.cam.ac.uk
date Tue Feb 01 09:24:57 2005 +0000 (2005-02-01)
parents ddf5b350364f a5f1a6abfc46
children bbe8541361dd d93748c50893
line source
1 /*
2 * Generate definitions needed by assembly language modules.
3 * This code generates raw asm output which is post-processed
4 * to extract and format the required data.
5 */
7 #include <xen/sched.h>
9 #define DEFINE(_sym, _val) \
10 __asm__ __volatile__ ( "\n->" #_sym " %0 " #_val : : "i" (_val) )
11 #define BLANK() \
12 __asm__ __volatile__ ( "\n->" : : )
13 #define OFFSET(_sym, _str, _mem) \
14 DEFINE(_sym, offsetof(_str, _mem));
16 void __dummy__(void)
17 {
18 OFFSET(XREGS_eax, struct xen_regs, eax);
19 OFFSET(XREGS_ebx, struct xen_regs, ebx);
20 OFFSET(XREGS_ecx, struct xen_regs, ecx);
21 OFFSET(XREGS_edx, struct xen_regs, edx);
22 OFFSET(XREGS_esi, struct xen_regs, esi);
23 OFFSET(XREGS_edi, struct xen_regs, edi);
24 OFFSET(XREGS_esp, struct xen_regs, esp);
25 OFFSET(XREGS_ebp, struct xen_regs, ebp);
26 OFFSET(XREGS_eip, struct xen_regs, eip);
27 OFFSET(XREGS_cs, struct xen_regs, cs);
28 OFFSET(XREGS_ds, struct xen_regs, ds);
29 OFFSET(XREGS_es, struct xen_regs, es);
30 OFFSET(XREGS_fs, struct xen_regs, fs);
31 OFFSET(XREGS_gs, struct xen_regs, gs);
32 OFFSET(XREGS_ss, struct xen_regs, ss);
33 OFFSET(XREGS_eflags, struct xen_regs, eflags);
34 OFFSET(XREGS_error_code, struct xen_regs, error_code);
35 OFFSET(XREGS_entry_vector, struct xen_regs, entry_vector);
36 OFFSET(XREGS_kernel_sizeof, struct xen_regs, esp);
37 DEFINE(XREGS_user_sizeof, sizeof(struct xen_regs));
38 BLANK();
40 OFFSET(EDOMAIN_processor, struct exec_domain, processor);
41 OFFSET(EDOMAIN_vcpu_info, struct exec_domain, vcpu_info);
42 OFFSET(EDOMAIN_event_sel, struct exec_domain, thread.event_selector);
43 OFFSET(EDOMAIN_event_addr, struct exec_domain, thread.event_address);
44 OFFSET(EDOMAIN_failsafe_sel, struct exec_domain, thread.failsafe_selector);
45 OFFSET(EDOMAIN_failsafe_addr, struct exec_domain, thread.failsafe_address);
46 OFFSET(EDOMAIN_trap_bounce, struct exec_domain, thread.trap_bounce);
47 OFFSET(EDOMAIN_thread_flags, struct exec_domain, thread.flags);
48 BLANK();
50 OFFSET(VCPUINFO_upcall_pending, vcpu_info_t, evtchn_upcall_pending);
51 OFFSET(VCPUINFO_upcall_mask, vcpu_info_t, evtchn_upcall_mask);
52 BLANK();
54 OFFSET(TRAPBOUNCE_error_code, struct trap_bounce, error_code);
55 OFFSET(TRAPBOUNCE_cr2, struct trap_bounce, cr2);
56 OFFSET(TRAPBOUNCE_flags, struct trap_bounce, flags);
57 OFFSET(TRAPBOUNCE_cs, struct trap_bounce, cs);
58 OFFSET(TRAPBOUNCE_eip, struct trap_bounce, eip);
59 BLANK();
61 OFFSET(MULTICALL_op, multicall_entry_t, op);
62 OFFSET(MULTICALL_arg0, multicall_entry_t, args[0]);
63 OFFSET(MULTICALL_arg1, multicall_entry_t, args[1]);
64 OFFSET(MULTICALL_arg2, multicall_entry_t, args[2]);
65 OFFSET(MULTICALL_arg3, multicall_entry_t, args[3]);
66 OFFSET(MULTICALL_arg4, multicall_entry_t, args[4]);
67 OFFSET(MULTICALL_result, multicall_entry_t, args[5]);
68 BLANK();
70 DEFINE(FIXMAP_apic_base, fix_to_virt(FIX_APIC_BASE));
71 }