debuggers.hg

view xen/arch/ia64/patch/linux-2.6.11/ivt.S @ 4619:5b9e241131fb

bitkeeper revision 1.1329 (42661815u5WPq8d5f4_axi2xWheybA)

Merge firebug.cl.cam.ac.uk:/local/scratch/kaf24/xen-unstable.bk
into firebug.cl.cam.ac.uk:/local/scratch/kaf24/xeno-unstable-ia64.bk
author kaf24@firebug.cl.cam.ac.uk
date Wed Apr 20 08:51:33 2005 +0000 (2005-04-20)
parents 58efb3448933
children
line source
1 ivt.S | 254 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 1 files changed, 254 insertions(+)
4 Index: linux-2.6.11-xendiffs/arch/ia64/kernel/ivt.S
5 ===================================================================
6 --- linux-2.6.11-xendiffs.orig/arch/ia64/kernel/ivt.S 2005-04-07 10:29:00.565766924 -0500
7 +++ linux-2.6.11-xendiffs/arch/ia64/kernel/ivt.S 2005-04-07 10:29:50.923594750 -0500
8 @@ -1,3 +1,21 @@
9 +
10 +#ifdef XEN
11 +//#define CONFIG_DISABLE_VHPT // FIXME: change when VHPT is enabled??
12 +// these are all hacked out for now as the entire IVT
13 +// will eventually be replaced... just want to use it
14 +// for startup code to handle TLB misses
15 +//#define ia64_leave_kernel 0
16 +//#define ia64_ret_from_syscall 0
17 +//#define ia64_handle_irq 0
18 +//#define ia64_fault 0
19 +#define ia64_illegal_op_fault 0
20 +#define ia64_prepare_handle_unaligned 0
21 +#define ia64_bad_break 0
22 +#define ia64_trace_syscall 0
23 +#define sys_call_table 0
24 +#define sys_ni_syscall 0
25 +#include <asm/vhpt.h>
26 +#endif
27 /*
28 * arch/ia64/kernel/ivt.S
29 *
30 @@ -77,6 +95,13 @@
31 mov r19=n;; /* prepare to save predicates */ \
32 br.sptk.many dispatch_to_fault_handler
34 +#ifdef XEN
35 +#define REFLECT(n) \
36 + mov r31=pr; \
37 + mov r19=n;; /* prepare to save predicates */ \
38 + br.sptk.many dispatch_reflection
39 +#endif
40 +
41 .section .text.ivt,"ax"
43 .align 32768 // align on 32KB boundary
44 @@ -214,6 +239,13 @@ END(vhpt_miss)
45 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
46 ENTRY(itlb_miss)
47 DBG_FAULT(1)
48 +#ifdef XEN
49 + VHPT_CCHAIN_LOOKUP(itlb_miss,i)
50 +#ifdef VHPT_GLOBAL
51 + br.cond.sptk page_fault
52 + ;;
53 +#endif
54 +#endif
55 /*
56 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
57 * page table. If a nested TLB miss occurs, we switch into physical
58 @@ -258,6 +290,13 @@ END(itlb_miss)
59 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
60 ENTRY(dtlb_miss)
61 DBG_FAULT(2)
62 +#ifdef XEN
63 + VHPT_CCHAIN_LOOKUP(dtlb_miss,d)
64 +#ifdef VHPT_GLOBAL
65 + br.cond.sptk page_fault
66 + ;;
67 +#endif
68 +#endif
69 /*
70 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
71 * page table. If a nested TLB miss occurs, we switch into physical
72 @@ -302,6 +341,13 @@ END(dtlb_miss)
73 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
74 ENTRY(alt_itlb_miss)
75 DBG_FAULT(3)
76 +#ifdef XEN
77 +//#ifdef VHPT_GLOBAL
78 +// VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i)
79 +// br.cond.sptk page_fault
80 +// ;;
81 +//#endif
82 +#endif
83 mov r16=cr.ifa // get address that caused the TLB miss
84 movl r17=PAGE_KERNEL
85 mov r21=cr.ipsr
86 @@ -340,6 +386,13 @@ END(alt_itlb_miss)
87 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
88 ENTRY(alt_dtlb_miss)
89 DBG_FAULT(4)
90 +#ifdef XEN
91 +//#ifdef VHPT_GLOBAL
92 +// VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d)
93 +// br.cond.sptk page_fault
94 +// ;;
95 +//#endif
96 +#endif
97 mov r16=cr.ifa // get address that caused the TLB miss
98 movl r17=PAGE_KERNEL
99 mov r20=cr.isr
100 @@ -369,6 +422,17 @@ ENTRY(alt_dtlb_miss)
101 cmp.ne p8,p0=r0,r23
102 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
103 (p8) br.cond.spnt page_fault
104 +#ifdef XEN
105 + ;;
106 + // FIXME: inadequate test, this is where we test for Xen address
107 + // note that 0xf000 (cached) and 0xd000 (uncached) addresses
108 + // should be OK. (Though no I/O is done in Xen, EFI needs uncached
109 + // addresses and some domain EFI calls are passed through)
110 + tbit.nz p0,p8=r16,60
111 +(p8) br.cond.spnt page_fault
112 +//(p8) br.cond.spnt 0
113 + ;;
114 +#endif
116 dep r21=-1,r21,IA64_PSR_ED_BIT,1
117 or r19=r19,r17 // insert PTE control bits into r19
118 @@ -449,6 +513,9 @@ END(nested_dtlb_miss)
119 /////////////////////////////////////////////////////////////////////////////////////////
120 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
121 ENTRY(ikey_miss)
122 +#ifdef XEN
123 + REFLECT(6)
124 +#endif
125 DBG_FAULT(6)
126 FAULT(6)
127 END(ikey_miss)
128 @@ -461,9 +528,16 @@ ENTRY(page_fault)
129 srlz.i
130 ;;
131 SAVE_MIN_WITH_COVER
132 +#ifdef XEN
133 + alloc r15=ar.pfs,0,0,4,0
134 + mov out0=cr.ifa
135 + mov out1=cr.isr
136 + mov out3=cr.itir
137 +#else
138 alloc r15=ar.pfs,0,0,3,0
139 mov out0=cr.ifa
140 mov out1=cr.isr
141 +#endif
142 adds r3=8,r2 // set up second base pointer
143 ;;
144 ssm psr.ic | PSR_DEFAULT_BITS
145 @@ -484,6 +558,9 @@ END(page_fault)
146 /////////////////////////////////////////////////////////////////////////////////////////
147 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
148 ENTRY(dkey_miss)
149 +#ifdef XEN
150 + REFLECT(7)
151 +#endif
152 DBG_FAULT(7)
153 FAULT(7)
154 END(dkey_miss)
155 @@ -492,6 +569,9 @@ END(dkey_miss)
156 /////////////////////////////////////////////////////////////////////////////////////////
157 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
158 ENTRY(dirty_bit)
159 +#ifdef XEN
160 + REFLECT(8)
161 +#endif
162 DBG_FAULT(8)
163 /*
164 * What we do here is to simply turn on the dirty bit in the PTE. We need to
165 @@ -554,6 +634,9 @@ END(dirty_bit)
166 /////////////////////////////////////////////////////////////////////////////////////////
167 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
168 ENTRY(iaccess_bit)
169 +#ifdef XEN
170 + REFLECT(9)
171 +#endif
172 DBG_FAULT(9)
173 // Like Entry 8, except for instruction access
174 mov r16=cr.ifa // get the address that caused the fault
175 @@ -619,6 +702,9 @@ END(iaccess_bit)
176 /////////////////////////////////////////////////////////////////////////////////////////
177 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
178 ENTRY(daccess_bit)
179 +#ifdef XEN
180 + REFLECT(10)
181 +#endif
182 DBG_FAULT(10)
183 // Like Entry 8, except for data access
184 mov r16=cr.ifa // get the address that caused the fault
185 @@ -687,6 +773,16 @@ ENTRY(break_fault)
186 * to prevent leaking bits from kernel to user level.
187 */
188 DBG_FAULT(11)
189 +#ifdef XEN
190 + mov r16=cr.isr
191 + mov r17=cr.iim
192 + mov r31=pr
193 + ;;
194 + cmp.eq p7,p0=r0,r17 // is this a psuedo-cover?
195 + // FIXME: may also need to check slot==2?
196 +(p7) br.sptk.many dispatch_privop_fault
197 + br.sptk.many dispatch_break_fault
198 +#endif
199 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat.
200 mov r17=cr.iim
201 mov r18=__IA64_BREAK_SYSCALL
202 @@ -697,7 +793,9 @@ ENTRY(break_fault)
203 mov r27=ar.rsc
204 mov r26=ar.pfs
205 mov r28=cr.iip
206 +#ifndef XEN
207 mov r31=pr // prepare to save predicates
208 +#endif
209 mov r20=r1
210 ;;
211 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
212 @@ -797,6 +895,36 @@ END(interrupt)
213 DBG_FAULT(13)
214 FAULT(13)
216 +#ifdef XEN
217 + // There is no particular reason for this code to be here, other than that
218 + // there happens to be space here that would go unused otherwise. If this
219 + // fault ever gets "unreserved", simply moved the following code to a more
220 + // suitable spot...
221 +
222 +ENTRY(dispatch_break_fault)
223 + SAVE_MIN_WITH_COVER
224 + ;;
225 + alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
226 + mov out0=cr.ifa
227 + adds out1=16,sp
228 + mov out2=cr.isr // FIXME: pity to make this slow access twice
229 + mov out3=cr.iim // FIXME: pity to make this slow access twice
230 +
231 + ssm psr.ic | PSR_DEFAULT_BITS
232 + ;;
233 + srlz.i // guarantee that interruption collection is on
234 + ;;
235 +(p15) ssm psr.i // restore psr.i
236 + adds r3=8,r2 // set up second base pointer
237 + ;;
238 + SAVE_REST
239 + movl r14=ia64_leave_kernel
240 + ;;
241 + mov rp=r14
242 + br.sptk.many ia64_prepare_handle_break
243 +END(dispatch_break_fault)
244 +#endif
245 +
246 .org ia64_ivt+0x3800
247 /////////////////////////////////////////////////////////////////////////////////////////
248 // 0x3800 Entry 14 (size 64 bundles) Reserved
249 @@ -850,9 +978,11 @@ END(interrupt)
250 * - ar.fpsr: set to kernel settings
251 */
252 GLOBAL_ENTRY(ia64_syscall_setup)
253 +#ifndef XEN
254 #if PT(B6) != 0
255 # error This code assumes that b6 is the first field in pt_regs.
256 #endif
257 +#endif
258 st8 [r1]=r19 // save b6
259 add r16=PT(CR_IPSR),r1 // initialize first base pointer
260 add r17=PT(R11),r1 // initialize second base pointer
261 @@ -992,6 +1122,37 @@ END(dispatch_illegal_op_fault)
262 DBG_FAULT(16)
263 FAULT(16)
265 +#ifdef XEN
266 + // There is no particular reason for this code to be here, other than that
267 + // there happens to be space here that would go unused otherwise. If this
268 + // fault ever gets "unreserved", simply moved the following code to a more
269 + // suitable spot...
270 +
271 +ENTRY(dispatch_privop_fault)
272 + SAVE_MIN_WITH_COVER
273 + ;;
274 + alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
275 + mov out0=cr.ifa
276 + adds out1=16,sp
277 + mov out2=cr.isr // FIXME: pity to make this slow access twice
278 + mov out3=cr.itir
279 +
280 + ssm psr.ic | PSR_DEFAULT_BITS
281 + ;;
282 + srlz.i // guarantee that interruption collection is on
283 + ;;
284 +(p15) ssm psr.i // restore psr.i
285 + adds r3=8,r2 // set up second base pointer
286 + ;;
287 + SAVE_REST
288 + movl r14=ia64_leave_kernel
289 + ;;
290 + mov rp=r14
291 + br.sptk.many ia64_prepare_handle_privop
292 +END(dispatch_privop_fault)
293 +#endif
294 +
295 +
296 .org ia64_ivt+0x4400
297 /////////////////////////////////////////////////////////////////////////////////////////
298 // 0x4400 Entry 17 (size 64 bundles) Reserved
299 @@ -1108,6 +1269,9 @@ END(dispatch_to_fault_handler)
300 /////////////////////////////////////////////////////////////////////////////////////////
301 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
302 ENTRY(page_not_present)
303 +#ifdef XEN
304 + REFLECT(20)
305 +#endif
306 DBG_FAULT(20)
307 mov r16=cr.ifa
308 rsm psr.dt
309 @@ -1128,6 +1292,9 @@ END(page_not_present)
310 /////////////////////////////////////////////////////////////////////////////////////////
311 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
312 ENTRY(key_permission)
313 +#ifdef XEN
314 + REFLECT(21)
315 +#endif
316 DBG_FAULT(21)
317 mov r16=cr.ifa
318 rsm psr.dt
319 @@ -1141,6 +1308,9 @@ END(key_permission)
320 /////////////////////////////////////////////////////////////////////////////////////////
321 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
322 ENTRY(iaccess_rights)
323 +#ifdef XEN
324 + REFLECT(22)
325 +#endif
326 DBG_FAULT(22)
327 mov r16=cr.ifa
328 rsm psr.dt
329 @@ -1154,6 +1324,9 @@ END(iaccess_rights)
330 /////////////////////////////////////////////////////////////////////////////////////////
331 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
332 ENTRY(daccess_rights)
333 +#ifdef XEN
334 + REFLECT(23)
335 +#endif
336 DBG_FAULT(23)
337 mov r16=cr.ifa
338 rsm psr.dt
339 @@ -1171,8 +1344,13 @@ ENTRY(general_exception)
340 mov r16=cr.isr
341 mov r31=pr
342 ;;
343 +#ifdef XEN
344 + cmp4.ge p6,p0=0x20,r16
345 +(p6) br.sptk.many dispatch_privop_fault
346 +#else
347 cmp4.eq p6,p0=0,r16
348 (p6) br.sptk.many dispatch_illegal_op_fault
349 +#endif
350 ;;
351 mov r19=24 // fault number
352 br.sptk.many dispatch_to_fault_handler
353 @@ -1182,6 +1360,9 @@ END(general_exception)
354 /////////////////////////////////////////////////////////////////////////////////////////
355 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
356 ENTRY(disabled_fp_reg)
357 +#ifdef XEN
358 + REFLECT(25)
359 +#endif
360 DBG_FAULT(25)
361 rsm psr.dfh // ensure we can access fph
362 ;;
363 @@ -1195,6 +1376,9 @@ END(disabled_fp_reg)
364 /////////////////////////////////////////////////////////////////////////////////////////
365 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
366 ENTRY(nat_consumption)
367 +#ifdef XEN
368 + REFLECT(26)
369 +#endif
370 DBG_FAULT(26)
371 FAULT(26)
372 END(nat_consumption)
373 @@ -1203,6 +1387,10 @@ END(nat_consumption)
374 /////////////////////////////////////////////////////////////////////////////////////////
375 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
376 ENTRY(speculation_vector)
377 +#ifdef XEN
378 + // this probably need not reflect...
379 + REFLECT(27)
380 +#endif
381 DBG_FAULT(27)
382 /*
383 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
384 @@ -1246,6 +1434,9 @@ END(speculation_vector)
385 /////////////////////////////////////////////////////////////////////////////////////////
386 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
387 ENTRY(debug_vector)
388 +#ifdef XEN
389 + REFLECT(29)
390 +#endif
391 DBG_FAULT(29)
392 FAULT(29)
393 END(debug_vector)
394 @@ -1254,6 +1445,9 @@ END(debug_vector)
395 /////////////////////////////////////////////////////////////////////////////////////////
396 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
397 ENTRY(unaligned_access)
398 +#ifdef XEN
399 + REFLECT(30)
400 +#endif
401 DBG_FAULT(30)
402 mov r16=cr.ipsr
403 mov r31=pr // prepare to save predicates
404 @@ -1265,6 +1459,9 @@ END(unaligned_access)
405 /////////////////////////////////////////////////////////////////////////////////////////
406 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
407 ENTRY(unsupported_data_reference)
408 +#ifdef XEN
409 + REFLECT(31)
410 +#endif
411 DBG_FAULT(31)
412 FAULT(31)
413 END(unsupported_data_reference)
414 @@ -1273,6 +1470,9 @@ END(unsupported_data_reference)
415 /////////////////////////////////////////////////////////////////////////////////////////
416 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
417 ENTRY(floating_point_fault)
418 +#ifdef XEN
419 + REFLECT(32)
420 +#endif
421 DBG_FAULT(32)
422 FAULT(32)
423 END(floating_point_fault)
424 @@ -1281,6 +1481,9 @@ END(floating_point_fault)
425 /////////////////////////////////////////////////////////////////////////////////////////
426 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
427 ENTRY(floating_point_trap)
428 +#ifdef XEN
429 + REFLECT(33)
430 +#endif
431 DBG_FAULT(33)
432 FAULT(33)
433 END(floating_point_trap)
434 @@ -1289,6 +1492,9 @@ END(floating_point_trap)
435 /////////////////////////////////////////////////////////////////////////////////////////
436 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
437 ENTRY(lower_privilege_trap)
438 +#ifdef XEN
439 + REFLECT(34)
440 +#endif
441 DBG_FAULT(34)
442 FAULT(34)
443 END(lower_privilege_trap)
444 @@ -1297,6 +1503,9 @@ END(lower_privilege_trap)
445 /////////////////////////////////////////////////////////////////////////////////////////
446 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
447 ENTRY(taken_branch_trap)
448 +#ifdef XEN
449 + REFLECT(35)
450 +#endif
451 DBG_FAULT(35)
452 FAULT(35)
453 END(taken_branch_trap)
454 @@ -1305,6 +1514,9 @@ END(taken_branch_trap)
455 /////////////////////////////////////////////////////////////////////////////////////////
456 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
457 ENTRY(single_step_trap)
458 +#ifdef XEN
459 + REFLECT(36)
460 +#endif
461 DBG_FAULT(36)
462 FAULT(36)
463 END(single_step_trap)
464 @@ -1361,6 +1573,9 @@ END(single_step_trap)
465 /////////////////////////////////////////////////////////////////////////////////////////
466 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
467 ENTRY(ia32_exception)
468 +#ifdef XEN
469 + REFLECT(45)
470 +#endif
471 DBG_FAULT(45)
472 FAULT(45)
473 END(ia32_exception)
474 @@ -1369,6 +1584,9 @@ END(ia32_exception)
475 /////////////////////////////////////////////////////////////////////////////////////////
476 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
477 ENTRY(ia32_intercept)
478 +#ifdef XEN
479 + REFLECT(46)
480 +#endif
481 DBG_FAULT(46)
482 #ifdef CONFIG_IA32_SUPPORT
483 mov r31=pr
484 @@ -1399,6 +1617,9 @@ END(ia32_intercept)
485 /////////////////////////////////////////////////////////////////////////////////////////
486 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
487 ENTRY(ia32_interrupt)
488 +#ifdef XEN
489 + REFLECT(47)
490 +#endif
491 DBG_FAULT(47)
492 #ifdef CONFIG_IA32_SUPPORT
493 mov r31=pr
494 @@ -1528,6 +1749,39 @@ END(ia32_interrupt)
495 DBG_FAULT(67)
496 FAULT(67)
498 +#ifdef XEN
499 + .org ia64_ivt+0x8000
500 +ENTRY(dispatch_reflection)
501 + /*
502 + * Input:
503 + * psr.ic: off
504 + * r19: intr type (offset into ivt, see ia64_int.h)
505 + * r31: contains saved predicates (pr)
506 + */
507 + SAVE_MIN_WITH_COVER_R19
508 + alloc r14=ar.pfs,0,0,5,0
509 + mov out4=r15
510 + mov out0=cr.ifa
511 + adds out1=16,sp
512 + mov out2=cr.isr
513 + mov out3=cr.iim
514 +// mov out3=cr.itir
515 +
516 + ssm psr.ic | PSR_DEFAULT_BITS
517 + ;;
518 + srlz.i // guarantee that interruption collection is on
519 + ;;
520 +(p15) ssm psr.i // restore psr.i
521 + adds r3=8,r2 // set up second base pointer
522 + ;;
523 + SAVE_REST
524 + movl r14=ia64_leave_kernel
525 + ;;
526 + mov rp=r14
527 + br.sptk.many ia64_prepare_handle_reflection
528 +END(dispatch_reflection)
529 +#endif
530 +
531 #ifdef CONFIG_IA32_SUPPORT
533 /*