debuggers.hg

view xen/include/asm-x86/msr.h @ 4625:65d78e532664

bitkeeper revision 1.1335 (42662df5Ky_wqkYVs3ghiLYYBXII2Q)

[PATCH] x86-64-rdmsrl.patch

Use the rdmsrl implementation from Linux.

Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author arun.sharma@intel.com[kaf24]
date Wed Apr 20 10:24:53 2005 +0000 (2005-04-20)
parents 24703bde489b
children 569173be116f
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 #define rdmsr(msr,val1,val2) \
5 __asm__ __volatile__("rdmsr" \
6 : "=a" (val1), "=d" (val2) \
7 : "c" (msr))
9 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
10 __asm__ __volatile__("rdmsr" \
11 : "=a" (a__), "=d" (b__) \
12 : "c" (msr)); \
13 val = a__ | (b__<<32); \
14 } while(0);
16 #define wrmsr(msr,val1,val2) \
17 __asm__ __volatile__("wrmsr" \
18 : /* no outputs */ \
19 : "c" (msr), "a" (val1), "d" (val2))
21 #define rdmsr_user(msr,val1,val2) ({\
22 int _rc; \
23 __asm__ __volatile__( \
24 "1: rdmsr\n2:\n" \
25 ".section .fixup,\"ax\"\n" \
26 "3: movl $1,%2\n; jmp 2b\n" \
27 ".previous\n" \
28 ".section __ex_table,\"a\"\n" \
29 " "__FIXUP_ALIGN"\n" \
30 " "__FIXUP_WORD" 1b,3b\n" \
31 ".previous\n" \
32 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
33 : "c" (msr), "2" (0)); \
34 _rc; })
36 #define wrmsr_user(msr,val1,val2) ({\
37 int _rc; \
38 __asm__ __volatile__( \
39 "1: wrmsr\n2:\n" \
40 ".section .fixup,\"ax\"\n" \
41 "3: movl $1,%0\n; jmp 2b\n" \
42 ".previous\n" \
43 ".section __ex_table,\"a\"\n" \
44 " "__FIXUP_ALIGN"\n" \
45 " "__FIXUP_WORD" 1b,3b\n" \
46 ".previous\n" \
47 : "=&r" (_rc) \
48 : "c" (msr), "a" (val1), "d" (val2), "0" (0)); \
49 _rc; })
51 #define rdtsc(low,high) \
52 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
54 #define rdtscl(low) \
55 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
57 #if defined(__i386__)
58 #define rdtscll(val) \
59 __asm__ __volatile__("rdtsc" : "=A" (val))
60 #elif defined(__x86_64__)
61 #define rdtscll(val) do { \
62 unsigned int a,d; \
63 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
64 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
65 } while(0)
66 #endif
68 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
70 #define rdpmc(counter,low,high) \
71 __asm__ __volatile__("rdpmc" \
72 : "=a" (low), "=d" (high) \
73 : "c" (counter))
75 /* symbolic names for some interesting MSRs */
76 /* Intel defined MSRs. */
77 #define MSR_IA32_P5_MC_ADDR 0
78 #define MSR_IA32_P5_MC_TYPE 1
79 #define MSR_IA32_PLATFORM_ID 0x17
80 #define MSR_IA32_EBL_CR_POWERON 0x2a
82 /* AMD/K8 specific MSRs */
83 #define MSR_EFER 0xc0000080 /* extended feature register */
84 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
85 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
86 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
87 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
88 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
89 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
90 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
91 /* EFER bits: */
92 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
93 #define _EFER_LME 8 /* Long mode enable */
94 #define _EFER_LMA 10 /* Long mode active (read-only) */
95 #define _EFER_NX 11 /* No execute enable */
97 #define EFER_SCE (1<<_EFER_SCE)
98 #define EFER_LME (1<<_EFER_LME)
99 #define EFER_LMA (1<<_EFER_LMA)
100 #define EFER_NX (1<<_EFER_NX)
102 /* Intel MSRs. Some also available on other CPUs */
103 #define MSR_IA32_PLATFORM_ID 0x17
105 #define MSR_IA32_PERFCTR0 0xc1
106 #define MSR_IA32_PERFCTR1 0xc2
108 #define MSR_MTRRcap 0x0fe
109 #define MSR_IA32_BBL_CR_CTL 0x119
111 #define MSR_IA32_SYSENTER_CS 0x174
112 #define MSR_IA32_SYSENTER_ESP 0x175
113 #define MSR_IA32_SYSENTER_EIP 0x176
115 #define MSR_IA32_MCG_CAP 0x179
116 #define MSR_IA32_MCG_STATUS 0x17a
117 #define MSR_IA32_MCG_CTL 0x17b
119 #define MSR_IA32_EVNTSEL0 0x186
120 #define MSR_IA32_EVNTSEL1 0x187
122 #define MSR_MTRRfix64K_00000 0x250
123 #define MSR_MTRRfix16K_80000 0x258
124 #define MSR_MTRRfix16K_A0000 0x259
125 #define MSR_MTRRfix4K_C0000 0x268
126 #define MSR_MTRRfix4K_C8000 0x269
127 #define MSR_MTRRfix4K_D0000 0x26a
128 #define MSR_MTRRfix4K_D8000 0x26b
129 #define MSR_MTRRfix4K_E0000 0x26c
130 #define MSR_MTRRfix4K_E8000 0x26d
131 #define MSR_MTRRfix4K_F0000 0x26e
132 #define MSR_MTRRfix4K_F8000 0x26f
133 #define MSR_MTRRdefType 0x2ff
135 #define MSR_IA32_MC0_CTL 0x400
136 #define MSR_IA32_MC0_STATUS 0x401
137 #define MSR_IA32_MC0_ADDR 0x402
138 #define MSR_IA32_MC0_MISC 0x403
140 #define MSR_IA32_DS_AREA 0x600
142 #define MSR_IA32_APICBASE 0x1b
143 #define MSR_IA32_APICBASE_BSP (1<<8)
144 #define MSR_IA32_APICBASE_ENABLE (1<<11)
145 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
147 #define MSR_IA32_UCODE_WRITE 0x79
148 #define MSR_IA32_UCODE_REV 0x8b
150 #define MSR_IA32_BBL_CR_CTL 0x119
152 #define MSR_IA32_MCG_CAP 0x179
153 #define MSR_IA32_MCG_STATUS 0x17a
154 #define MSR_IA32_MCG_CTL 0x17b
156 #define MSR_IA32_THERM_CONTROL 0x19a
157 #define MSR_IA32_THERM_INTERRUPT 0x19b
158 #define MSR_IA32_THERM_STATUS 0x19c
159 #define MSR_IA32_MISC_ENABLE 0x1a0
161 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
162 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
163 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
165 #define MSR_IA32_DEBUGCTLMSR 0x1d9
166 #define MSR_IA32_DEBUGCTLMSR_LBR (1<<0)
167 #define MSR_IA32_DEBUGCTLMSR_BTF (1<<1)
168 #define MSR_IA32_DEBUGCTLMSR_TR (1<<2)
169 #define MSR_IA32_DEBUGCTLMSR_BTS (1<<3)
170 #define MSR_IA32_DEBUGCTLMSR_BTINT (1<<4)
172 #define MSR_IA32_LASTBRANCH_TOS 0x1da
173 #define MSR_IA32_LASTBRANCH_0 0x1db
174 #define MSR_IA32_LASTBRANCH_1 0x1dc
175 #define MSR_IA32_LASTBRANCH_2 0x1dd
176 #define MSR_IA32_LASTBRANCH_3 0x1de
178 #define MSR_IA32_MC0_CTL 0x400
179 #define MSR_IA32_MC0_STATUS 0x401
180 #define MSR_IA32_MC0_ADDR 0x402
181 #define MSR_IA32_MC0_MISC 0x403
183 #define MSR_P6_PERFCTR0 0xc1
184 #define MSR_P6_PERFCTR1 0xc2
185 #define MSR_P6_EVNTSEL0 0x186
186 #define MSR_P6_EVNTSEL1 0x187
189 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
190 #define MSR_K7_EVNTSEL0 0xC0010000
191 #define MSR_K7_PERFCTR0 0xC0010004
192 #define MSR_K7_EVNTSEL1 0xC0010001
193 #define MSR_K7_PERFCTR1 0xC0010005
194 #define MSR_K7_EVNTSEL2 0xC0010002
195 #define MSR_K7_PERFCTR2 0xC0010006
196 #define MSR_K7_EVNTSEL3 0xC0010003
197 #define MSR_K7_PERFCTR3 0xC0010007
198 #define MSR_K8_TOP_MEM1 0xC001001A
199 #define MSR_K8_TOP_MEM2 0xC001001D
200 #define MSR_K8_SYSCFG 0xC0000010
201 #define MSR_K7_HWCR 0xC0010015
202 #define MSR_K7_CLK_CTL 0xC001001b
203 #define MSR_K7_FID_VID_CTL 0xC0010041
204 #define MSR_K7_VID_STATUS 0xC0010042
206 /* K6 MSRs */
207 #define MSR_K6_EFER 0xC0000080
208 #define MSR_K6_STAR 0xC0000081
209 #define MSR_K6_WHCR 0xC0000082
210 #define MSR_K6_UWCCR 0xC0000085
211 #define MSR_K6_EPMR 0xC0000086
212 #define MSR_K6_PSOR 0xC0000087
213 #define MSR_K6_PFIR 0xC0000088
215 /* Centaur-Hauls/IDT defined MSRs. */
216 #define MSR_IDT_FCR1 0x107
217 #define MSR_IDT_FCR2 0x108
218 #define MSR_IDT_FCR3 0x109
219 #define MSR_IDT_FCR4 0x10a
221 #define MSR_IDT_MCR0 0x110
222 #define MSR_IDT_MCR1 0x111
223 #define MSR_IDT_MCR2 0x112
224 #define MSR_IDT_MCR3 0x113
225 #define MSR_IDT_MCR4 0x114
226 #define MSR_IDT_MCR5 0x115
227 #define MSR_IDT_MCR6 0x116
228 #define MSR_IDT_MCR7 0x117
229 #define MSR_IDT_MCR_CTRL 0x120
231 /* VIA Cyrix defined MSRs*/
232 #define MSR_VIA_FCR 0x1107
233 #define MSR_VIA_LONGHAUL 0x110a
234 #define MSR_VIA_BCR2 0x1147
236 /* Transmeta defined MSRs */
237 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
238 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
239 #define MSR_TMTA_LRTI_READOUT 0x80868018
240 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
242 #endif /* __ASM_MSR_H */