debuggers.hg

view xen/arch/x86/apic.c @ 4657:67c40314aa6e

bitkeeper revision 1.1356 (4267b673efcxbbD0RRVHEKvD5FY3Ng)

A few APIC cleanups. I hate '#if 0' code.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Apr 21 14:19:31 2005 +0000 (2005-04-21)
parents 8ce73ebd1311
children caaf9d543bc5
line source
1 /*
2 * based on linux-2.6.10/arch/i386/kernel/apic.c
3 *
4 * Local APIC handling, local APIC timers
5 *
6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
10 * thanks to Eric Gilmore
11 * and Rolf G. Tews
12 * for testing these extensively.
13 * Maciej W. Rozycki : Various updates and fixes.
14 * Mikael Pettersson : Power Management for UP-APIC.
15 * Pavel Machek and
16 * Mikael Pettersson : PM converted to driver model.
17 */
19 #include <xen/config.h>
20 #include <xen/perfc.h>
21 #include <xen/errno.h>
22 #include <xen/init.h>
23 #include <xen/mm.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/smp.h>
28 #include <xen/softirq.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/msr.h>
31 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/flushtlb.h>
34 #include <asm/hardirq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <asm/mach_apic.h>
38 #include <asm/io_ports.h>
40 /* Using APIC to generate smp_local_timer_interrupt? */
41 int using_apic_timer = 0;
43 static int enabled_via_apicbase;
45 int get_maxlvt(void)
46 {
47 unsigned int v, ver, maxlvt;
49 v = apic_read(APIC_LVR);
50 ver = GET_APIC_VERSION(v);
51 /* 82489DXs do not report # of LVT entries. */
52 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
53 return maxlvt;
54 }
56 void clear_local_APIC(void)
57 {
58 int maxlvt;
59 unsigned long v;
61 maxlvt = get_maxlvt();
63 /*
64 * Masking an LVT entry on a P6 can trigger a local APIC error
65 * if the vector is zero. Mask LVTERR first to prevent this.
66 */
67 if (maxlvt >= 3) {
68 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
69 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
70 }
71 /*
72 * Careful: we have to set masks only first to deassert
73 * any level-triggered sources.
74 */
75 v = apic_read(APIC_LVTT);
76 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
77 v = apic_read(APIC_LVT0);
78 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
79 v = apic_read(APIC_LVT1);
80 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
81 if (maxlvt >= 4) {
82 v = apic_read(APIC_LVTPC);
83 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
84 }
86 /*
87 * Clean APIC state for other OSs:
88 */
89 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
90 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
91 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
92 if (maxlvt >= 3)
93 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
94 if (maxlvt >= 4)
95 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
97 v = GET_APIC_VERSION(apic_read(APIC_LVR));
98 if (APIC_INTEGRATED(v)) { /* !82489DX */
99 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
100 apic_write(APIC_ESR, 0);
101 apic_read(APIC_ESR);
102 }
103 }
105 void __init connect_bsp_APIC(void)
106 {
107 if (pic_mode) {
108 /*
109 * Do not trust the local APIC being empty at bootup.
110 */
111 clear_local_APIC();
112 /*
113 * PIC mode, enable APIC mode in the IMCR, i.e.
114 * connect BSP's local APIC to INT and NMI lines.
115 */
116 printk("leaving PIC mode, enabling APIC mode.\n");
117 outb(0x70, 0x22);
118 outb(0x01, 0x23);
119 }
120 }
122 void disconnect_bsp_APIC(void)
123 {
124 if (pic_mode) {
125 /*
126 * Put the board back into PIC mode (has an effect
127 * only on certain older boards). Note that APIC
128 * interrupts, including IPIs, won't work beyond
129 * this point! The only exception are INIT IPIs.
130 */
131 printk("disabling APIC mode, entering PIC mode.\n");
132 outb(0x70, 0x22);
133 outb(0x00, 0x23);
134 }
135 }
137 void disable_local_APIC(void)
138 {
139 unsigned long value;
141 clear_local_APIC();
143 /*
144 * Disable APIC (implies clearing of registers
145 * for 82489DX!).
146 */
147 value = apic_read(APIC_SPIV);
148 value &= ~APIC_SPIV_APIC_ENABLED;
149 apic_write_around(APIC_SPIV, value);
151 if (enabled_via_apicbase) {
152 unsigned int l, h;
153 rdmsr(MSR_IA32_APICBASE, l, h);
154 l &= ~MSR_IA32_APICBASE_ENABLE;
155 wrmsr(MSR_IA32_APICBASE, l, h);
156 }
157 }
159 /*
160 * This is to verify that we're looking at a real local APIC.
161 * Check these against your board if the CPUs aren't getting
162 * started for no apparent reason.
163 */
164 int __init verify_local_APIC(void)
165 {
166 unsigned int reg0, reg1;
168 /*
169 * The version register is read-only in a real APIC.
170 */
171 reg0 = apic_read(APIC_LVR);
172 Dprintk("Getting VERSION: %x\n", reg0);
173 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
174 reg1 = apic_read(APIC_LVR);
175 Dprintk("Getting VERSION: %x\n", reg1);
177 /*
178 * The two version reads above should print the same
179 * numbers. If the second one is different, then we
180 * poke at a non-APIC.
181 */
182 if (reg1 != reg0)
183 return 0;
185 /*
186 * Check if the version looks reasonably.
187 */
188 reg1 = GET_APIC_VERSION(reg0);
189 if (reg1 == 0x00 || reg1 == 0xff)
190 return 0;
191 reg1 = get_maxlvt();
192 if (reg1 < 0x02 || reg1 == 0xff)
193 return 0;
195 /*
196 * The ID register is read/write in a real APIC.
197 */
198 reg0 = apic_read(APIC_ID);
199 Dprintk("Getting ID: %x\n", reg0);
201 /*
202 * The next two are just to see if we have sane values.
203 * They're only really relevant if we're in Virtual Wire
204 * compatibility mode, but most boxes are anymore.
205 */
206 reg0 = apic_read(APIC_LVT0);
207 Dprintk("Getting LVT0: %x\n", reg0);
208 reg1 = apic_read(APIC_LVT1);
209 Dprintk("Getting LVT1: %x\n", reg1);
211 return 1;
212 }
214 void __init sync_Arb_IDs(void)
215 {
216 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
217 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
218 if (ver >= 0x14) /* P4 or higher */
219 return;
220 /*
221 * Wait for idle.
222 */
223 apic_wait_icr_idle();
225 Dprintk("Synchronizing Arb IDs.\n");
226 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
227 | APIC_DM_INIT);
228 }
230 extern void __error_in_apic_c (void);
232 /*
233 * WAS: An initial setup of the virtual wire mode.
234 * NOW: We don't bother doing anything. All we need at this point
235 * is to receive timer ticks, so that 'jiffies' is incremented.
236 * If we're SMP, then we can assume BIOS did setup for us.
237 * If we're UP, then the APIC should be disabled (it is at reset).
238 * If we're UP and APIC is enabled, then BIOS is clever and has
239 * probably done initial interrupt routing for us.
240 */
241 void __init init_bsp_APIC(void)
242 {
243 }
245 void __init setup_local_APIC (void)
246 {
247 unsigned long oldvalue, value, ver, maxlvt;
249 /* Pound the ESR really hard over the head with a big hammer - mbligh */
250 if (esr_disable) {
251 apic_write(APIC_ESR, 0);
252 apic_write(APIC_ESR, 0);
253 apic_write(APIC_ESR, 0);
254 apic_write(APIC_ESR, 0);
255 }
257 value = apic_read(APIC_LVR);
258 ver = GET_APIC_VERSION(value);
260 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
261 __error_in_apic_c();
263 /*
264 * Double-check whether this APIC is really registered.
265 */
266 if (!apic_id_registered())
267 BUG();
269 /*
270 * Intel recommends to set DFR, LDR and TPR before enabling
271 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
272 * document number 292116). So here it goes...
273 */
274 init_apic_ldr();
276 /*
277 * Set Task Priority to 'accept all'. We never change this
278 * later on.
279 */
280 value = apic_read(APIC_TASKPRI);
281 value &= ~APIC_TPRI_MASK;
282 apic_write_around(APIC_TASKPRI, value);
284 /*
285 * Now that we are all set up, enable the APIC
286 */
287 value = apic_read(APIC_SPIV);
288 value &= ~APIC_VECTOR_MASK;
289 /*
290 * Enable APIC
291 */
292 value |= APIC_SPIV_APIC_ENABLED;
294 /*
295 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
296 * certain networking cards. If high frequency interrupts are
297 * happening on a particular IOAPIC pin, plus the IOAPIC routing
298 * entry is masked/unmasked at a high rate as well then sooner or
299 * later IOAPIC line gets 'stuck', no more interrupts are received
300 * from the device. If focus CPU is disabled then the hang goes
301 * away, oh well :-(
302 *
303 * [ This bug can be reproduced easily with a level-triggered
304 * PCI Ne2000 networking cards and PII/PIII processors, dual
305 * BX chipset. ]
306 */
307 /*
308 * Actually disabling the focus CPU check just makes the hang less
309 * frequent as it makes the interrupt distributon model be more
310 * like LRU than MRU (the short-term load is more even across CPUs).
311 * See also the comment in end_level_ioapic_irq(). --macro
312 */
313 #if 1
314 /* Enable focus processor (bit==0) */
315 value &= ~APIC_SPIV_FOCUS_DISABLED;
316 #else
317 /* Disable focus processor (bit==1) */
318 value |= APIC_SPIV_FOCUS_DISABLED;
319 #endif
320 /*
321 * Set spurious IRQ vector
322 */
323 value |= SPURIOUS_APIC_VECTOR;
324 apic_write_around(APIC_SPIV, value);
326 /*
327 * Set up LVT0, LVT1:
328 *
329 * set up through-local-APIC on the BP's LINT0. This is not
330 * strictly necessery in pure symmetric-IO mode, but sometimes
331 * we delegate interrupts to the 8259A.
332 */
333 /*
334 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
335 */
336 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
337 if (!smp_processor_id() && (pic_mode || !value)) {
338 value = APIC_DM_EXTINT;
339 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
340 } else {
341 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
342 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
343 }
344 apic_write_around(APIC_LVT0, value);
346 /*
347 * only the BP should see the LINT1 NMI signal, obviously.
348 */
349 if (!smp_processor_id())
350 value = APIC_DM_NMI;
351 else
352 value = APIC_DM_NMI | APIC_LVT_MASKED;
353 if (!APIC_INTEGRATED(ver)) /* 82489DX */
354 value |= APIC_LVT_LEVEL_TRIGGER;
355 apic_write_around(APIC_LVT1, value);
357 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
358 maxlvt = get_maxlvt();
359 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
360 apic_write(APIC_ESR, 0);
361 oldvalue = apic_read(APIC_ESR);
363 value = ERROR_APIC_VECTOR; // enables sending errors
364 apic_write_around(APIC_LVTERR, value);
365 /*
366 * spec says clear errors after enabling vector.
367 */
368 if (maxlvt > 3)
369 apic_write(APIC_ESR, 0);
370 value = apic_read(APIC_ESR);
371 if (value != oldvalue)
372 printk("ESR value before enabling vector: 0x%08lx "
373 "after: 0x%08lx\n", oldvalue, value);
374 } else {
375 if (esr_disable)
376 /*
377 * Something untraceble is creating bad interrupts on
378 * secondary quads ... for the moment, just leave the
379 * ESR disabled - we can't do anything useful with the
380 * errors anyway - mbligh
381 */
382 printk("Leaving ESR disabled.\n");
383 else
384 printk("No ESR for 82489DX.\n");
385 }
387 if (nmi_watchdog == NMI_LOCAL_APIC)
388 setup_apic_nmi_watchdog();
389 }
391 /*
392 * Detect and enable local APICs on non-SMP boards.
393 * Original code written by Keir Fraser.
394 */
396 static int __init detect_init_APIC (void)
397 {
398 u32 h, l, features;
399 extern void get_cpu_vendor(struct cpuinfo_x86*);
401 /* Workaround for us being called before identify_cpu(). */
402 get_cpu_vendor(&boot_cpu_data);
404 switch (boot_cpu_data.x86_vendor) {
405 case X86_VENDOR_AMD:
406 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
407 (boot_cpu_data.x86 == 15))
408 break;
409 goto no_apic;
410 case X86_VENDOR_INTEL:
411 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
412 (boot_cpu_data.x86 == 5 && cpu_has_apic))
413 break;
414 goto no_apic;
415 default:
416 goto no_apic;
417 }
419 if (!cpu_has_apic) {
420 /*
421 * Some BIOSes disable the local APIC in the
422 * APIC_BASE MSR. This can only be done in
423 * software for Intel P6 or later and AMD K7
424 * (Model > 1) or later.
425 */
426 rdmsr(MSR_IA32_APICBASE, l, h);
427 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
428 printk("Local APIC disabled by BIOS -- reenabling.\n");
429 l &= ~MSR_IA32_APICBASE_BASE;
430 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
431 wrmsr(MSR_IA32_APICBASE, l, h);
432 enabled_via_apicbase = 1;
433 }
434 }
436 /* The APIC feature bit should now be enabled in `cpuid' */
437 features = cpuid_edx(1);
438 if (!(features & (1 << X86_FEATURE_APIC))) {
439 printk("Could not enable APIC!\n");
440 return -1;
441 }
443 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
444 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
446 /* The BIOS may have set up the APIC at some other address */
447 rdmsr(MSR_IA32_APICBASE, l, h);
448 if (l & MSR_IA32_APICBASE_ENABLE)
449 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
451 if (nmi_watchdog != NMI_NONE)
452 nmi_watchdog = NMI_LOCAL_APIC;
454 printk("Found and enabled local APIC!\n");
456 return 0;
458 no_apic:
459 printk("No local APIC present or hardware disabled\n");
460 return -1;
461 }
463 void __init init_apic_mappings(void)
464 {
465 unsigned long apic_phys;
467 /*
468 * If no local APIC can be found then set up a fake all
469 * zeroes page to simulate the local APIC and another
470 * one for the IO-APIC.
471 */
472 if (!smp_found_config && detect_init_APIC()) {
473 apic_phys = alloc_xenheap_page();
474 apic_phys = __pa(apic_phys);
475 } else
476 apic_phys = mp_lapic_addr;
478 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
479 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
481 /*
482 * Fetch the APIC ID of the BSP in case we have a
483 * default configuration (or the MP table is broken).
484 */
485 if (boot_cpu_physical_apicid == -1U)
486 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
488 #ifdef CONFIG_X86_IO_APIC
489 {
490 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
491 int i;
493 for (i = 0; i < nr_ioapics; i++) {
494 if (smp_found_config) {
495 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
496 if (!ioapic_phys) {
497 printk(KERN_ERR
498 "WARNING: bogus zero IO-APIC "
499 "address found in MPTABLE, "
500 "disabling IO/APIC support!\n");
501 smp_found_config = 0;
502 skip_ioapic_setup = 1;
503 goto fake_ioapic_page;
504 }
505 } else {
506 fake_ioapic_page:
507 ioapic_phys = alloc_xenheap_page();
508 ioapic_phys = __pa(ioapic_phys);
509 }
510 set_fixmap_nocache(idx, ioapic_phys);
511 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
512 fix_to_virt(idx), ioapic_phys);
513 idx++;
514 }
515 }
516 #endif
517 }
519 /*****************************************************************************
520 * APIC calibration
521 *
522 * The APIC is programmed in bus cycles.
523 * Timeout values should specified in real time units.
524 * The "cheapest" time source is the cyclecounter.
525 *
526 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
527 *
528 * The calibration is currently a bit shoddy since it requires the external
529 * timer chip to generate periodic timer interupts.
530 *****************************************************************************/
532 /* used for system time scaling */
533 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
534 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
535 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
537 /*
538 * The timer chip is already set up at HZ interrupts per second here,
539 * but we do not accept timer interrupts yet. We only allow the BP
540 * to calibrate.
541 */
542 static unsigned int __init get_8254_timer_count(void)
543 {
544 /*extern spinlock_t i8253_lock;*/
545 /*unsigned long flags;*/
547 unsigned int count;
549 /*spin_lock_irqsave(&i8253_lock, flags);*/
551 outb_p(0x00, PIT_MODE);
552 count = inb_p(PIT_CH0);
553 count |= inb_p(PIT_CH0) << 8;
555 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
557 return count;
558 }
560 /* next tick in 8254 can be caught by catching timer wraparound */
561 static void __init wait_8254_wraparound(void)
562 {
563 unsigned int curr_count, prev_count=~0;
564 int delta;
566 curr_count = get_8254_timer_count();
568 do {
569 prev_count = curr_count;
570 curr_count = get_8254_timer_count();
571 delta = curr_count-prev_count;
573 /*
574 * This limit for delta seems arbitrary, but it isn't, it's slightly
575 * above the level of error a buggy Mercury/Neptune chipset timer can
576 * cause.
577 */
578 } while (delta < 300);
579 }
581 /*
582 * Default initialization for 8254 timers. If we use other timers like HPET,
583 * we override this later
584 */
585 void (*wait_timer_tick)(void) = wait_8254_wraparound;
587 /*
588 * This function sets up the local APIC timer, with a timeout of
589 * 'clocks' APIC bus clock. During calibration we actually call
590 * this function with a very large value and read the current time after
591 * a well defined period of time as expired.
592 *
593 * Calibration is only performed once, for CPU0!
594 *
595 * We do reads before writes even if unnecessary, to get around the
596 * P5 APIC double write bug.
597 */
599 #define APIC_DIVISOR 1
601 static void __setup_APIC_LVTT(unsigned int clocks)
602 {
603 unsigned int lvtt_value, tmp_value, ver;
605 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
606 /* NB. Xen uses local APIC timer in one-shot mode. */
607 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
608 if (!APIC_INTEGRATED(ver))
609 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
610 apic_write_around(APIC_LVTT, lvtt_value);
612 tmp_value = apic_read(APIC_TDCR);
613 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
615 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
616 }
618 /*
619 * this is done for every CPU from setup_APIC_clocks() below.
620 * We setup each local APIC with a zero timeout value for now.
621 * Unlike Linux, we don't have to wait for slices etc.
622 */
623 void setup_APIC_timer(void * data)
624 {
625 unsigned long flags;
626 __save_flags(flags);
627 __sti();
628 __setup_APIC_LVTT(0);
629 __restore_flags(flags);
630 }
632 /*
633 * In this function we calibrate APIC bus clocks to the external timer.
634 *
635 * As a result we have the Bus Speed and CPU speed in Hz.
636 *
637 * We want to do the calibration only once (for CPU0). CPUs connected by the
638 * same APIC bus have the very same bus frequency.
639 *
640 * This bit is a bit shoddy since we use the very same periodic timer interrupt
641 * we try to eliminate to calibrate the APIC.
642 */
644 int __init calibrate_APIC_clock(void)
645 {
646 unsigned long long t1 = 0, t2 = 0;
647 long tt1, tt2;
648 long result;
649 int i;
650 const int LOOPS = HZ/10;
652 printk("Calibrating APIC timer for CPU%d...\n", smp_processor_id());
654 /*
655 * Put whatever arbitrary (but long enough) timeout
656 * value into the APIC clock, we just want to get the
657 * counter running for calibration.
658 */
659 __setup_APIC_LVTT(1000000000);
661 /*
662 * The timer chip counts down to zero. Let's wait
663 * for a wraparound to start exact measurement:
664 * (the current tick might have been already half done)
665 */
666 wait_timer_tick();
668 /*
669 * We wrapped around just now. Let's start:
670 */
671 if (cpu_has_tsc)
672 rdtscll(t1);
673 tt1 = apic_read(APIC_TMCCT);
675 /*
676 * Let's wait LOOPS wraprounds:
677 */
678 for (i = 0; i < LOOPS; i++)
679 wait_timer_tick();
681 tt2 = apic_read(APIC_TMCCT);
682 if (cpu_has_tsc)
683 rdtscll(t2);
685 /*
686 * The APIC bus clock counter is 32 bits only, it
687 * might have overflown, but note that we use signed
688 * longs, thus no extra care needed.
689 * [underflown to be exact, as the timer counts down ;)]
690 */
692 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
694 if (cpu_has_tsc)
695 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
696 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
697 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
699 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
700 result/(1000000/HZ),
701 result%(1000000/HZ));
703 /* set up multipliers for accurate timer code */
704 bus_freq = result*HZ;
705 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
706 bus_scale = (1000*262144)/bus_cycle;
708 printk("..... bus_scale = 0x%08X\n", bus_scale);
709 /* reset APIC to zero timeout value */
710 __setup_APIC_LVTT(0);
712 return result;
713 }
715 /*
716 * initialise the APIC timers for all CPUs
717 * we start with the first and find out processor frequency and bus speed
718 */
719 void __init setup_APIC_clocks (void)
720 {
721 printk("Using local APIC timer interrupts.\n");
722 using_apic_timer = 1;
723 __cli();
724 /* calibrate CPU0 for CPU speed and BUS speed */
725 bus_freq = calibrate_APIC_clock();
726 /* Now set up the timer for real. */
727 setup_APIC_timer((void *)bus_freq);
728 __sti();
729 /* and update all other cpus */
730 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
731 }
733 #undef APIC_DIVISOR
735 /*
736 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
737 * returns 1 on success
738 * returns 0 if the timeout value is too small or in the past.
739 */
740 int reprogram_ac_timer(s_time_t timeout)
741 {
742 s_time_t now;
743 s_time_t expire;
744 u64 apic_tmict;
746 /*
747 * We use this value because we don't trust zero (we think it may just
748 * cause an immediate interrupt). At least this is guaranteed to hold it
749 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
750 */
751 if ( timeout == 0 )
752 {
753 apic_tmict = 0xffffffff;
754 goto reprogram;
755 }
757 now = NOW();
758 expire = timeout - now; /* value from now */
760 if ( expire <= 0 )
761 {
762 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
763 smp_processor_id(), (u32)(now>>32),
764 (u32)now, (u32)(timeout>>32),(u32)timeout);
765 return 0;
766 }
768 /*
769 * If we don't have local APIC then we just poll the timer list off the
770 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
771 */
772 if ( !cpu_has_apic )
773 return 1;
775 /* conversion to bus units */
776 apic_tmict = (((u64)bus_scale) * expire)>>18;
778 if ( apic_tmict >= 0xffffffff )
779 {
780 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
781 apic_tmict = 0xffffffff;
782 }
784 if ( apic_tmict == 0 )
785 {
786 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
787 return 0;
788 }
790 reprogram:
791 /* Program the timer. */
792 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
794 return 1;
795 }
797 void smp_apic_timer_interrupt(struct xen_regs * regs)
798 {
799 ack_APIC_irq();
800 perfc_incrc(apic_timer);
801 raise_softirq(AC_TIMER_SOFTIRQ);
802 }
804 /*
805 * This interrupt should _never_ happen with our APIC/SMP architecture
806 */
807 asmlinkage void smp_spurious_interrupt(struct xen_regs *regs)
808 {
809 unsigned long v;
811 /*
812 * Check if this really is a spurious interrupt and ACK it
813 * if it is a vectored one. Just in case...
814 * Spurious interrupts should not be ACKed.
815 */
816 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
817 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
818 ack_APIC_irq();
820 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
821 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
822 smp_processor_id());
823 }
825 /*
826 * This interrupt should never happen with our APIC/SMP architecture
827 */
829 asmlinkage void smp_error_interrupt(struct xen_regs *regs)
830 {
831 unsigned long v, v1;
833 /* First tickle the hardware, only then report what went on. -- REW */
834 v = apic_read(APIC_ESR);
835 apic_write(APIC_ESR, 0);
836 v1 = apic_read(APIC_ESR);
837 ack_APIC_irq();
838 atomic_inc(&irq_err_count);
840 /* Here is what the APIC error bits mean:
841 0: Send CS error
842 1: Receive CS error
843 2: Send accept error
844 3: Receive accept error
845 4: Reserved
846 5: Send illegal vector
847 6: Received illegal vector
848 7: Illegal register address
849 */
850 printk("APIC error on CPU%d: %02lx(%02lx)\n",
851 smp_processor_id(), v, v1);
852 }
854 /*
855 * This initializes the IO-APIC and APIC hardware if this is
856 * a UP kernel.
857 */
858 int __init APIC_init_uniprocessor (void)
859 {
860 if (!smp_found_config && !cpu_has_apic)
861 return -1;
863 /*
864 * Complain if the BIOS pretends there is one.
865 */
866 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
867 printk("BIOS bug, local APIC #%d not detected!...\n",
868 boot_cpu_physical_apicid);
869 return -1;
870 }
872 verify_local_APIC();
874 connect_bsp_APIC();
876 #ifdef CONFIG_SMP
877 cpu_online_map = 1;
878 #endif
879 phys_cpu_present_map = 1;
880 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
882 setup_local_APIC();
884 #ifdef CONFIG_X86_IO_APIC
885 if (smp_found_config)
886 if (!skip_ioapic_setup && nr_ioapics)
887 setup_IO_APIC();
888 #endif
889 setup_APIC_clocks();
891 return 0;
892 }