debuggers.hg

view xen/include/asm-x86/cpufeature.h @ 3545:6b76ae4b9ea7

bitkeeper revision 1.1159.212.30 (41f5268cMEdHLMEMs4o0SWqVEHZvuw)

Minor cleanup. Removed some duplicate MSRs, fixed some MSR names,
added a few new MSRs and MSR bit fields.
Signed-off-by: michael.fetterman@cl.cam.ac.uk
author mafetter@fleming.research
date Mon Jan 24 16:47:08 2005 +0000 (2005-01-24)
parents b9ab4345fd1b
children d8ba911dce48
line source
1 /*
2 * cpufeature.h
3 *
4 * Defines x86 CPU feature bits
5 */
7 #ifndef __ASM_X86_CPUFEATURE_H
8 #define __ASM_X86_CPUFEATURE_H
10 /* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
11 #define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE)
13 #define NCAPINTS 6 /* Currently we have 6 32-bit words worth of info */
15 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
16 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
17 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
18 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
19 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
20 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
21 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
22 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
23 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
24 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
25 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
26 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
27 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
28 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
29 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
30 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
31 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
32 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
33 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
34 #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
35 #define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */
36 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
37 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
38 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
39 /* of FPU context), and CR4.OSFXSR available */
40 #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
41 #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
42 #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
43 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
44 #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
45 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
47 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
48 /* Don't duplicate feature flags which are redundant with Intel! */
49 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
50 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */
51 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
52 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
53 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
54 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
56 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
57 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
58 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
59 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
61 /* Other features, Linux-defined mapping, word 3 */
62 /* This range is used for feature bits which conflict or are synthesized */
63 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
64 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
65 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
66 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
67 /* cpu types for specific tunings: */
68 #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
69 #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
70 #define X86_FEATURE_P3 (3*32+ 6) /* P3 */
71 #define X86_FEATURE_P4 (3*32+ 7) /* P4 */
73 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
74 #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
75 #define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
76 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
78 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
79 #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
82 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
83 #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
85 #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
86 #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
87 #define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
88 #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
89 #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
90 #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
91 #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
92 #define cpu_has_sse2 boot_cpu_has(X86_FEATURE_XMM2)
93 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
94 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
95 #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
96 #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
97 #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
98 #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
99 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
100 #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
101 #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
102 #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
103 #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
104 #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
106 #endif /* __ASM_X86_CPUFEATURE_H */