debuggers.hg

view xen/include/asm-x86/msr.h @ 3545:6b76ae4b9ea7

bitkeeper revision 1.1159.212.30 (41f5268cMEdHLMEMs4o0SWqVEHZvuw)

Minor cleanup. Removed some duplicate MSRs, fixed some MSR names,
added a few new MSRs and MSR bit fields.
Signed-off-by: michael.fetterman@cl.cam.ac.uk
author mafetter@fleming.research
date Mon Jan 24 16:47:08 2005 +0000 (2005-01-24)
parents b9ab4345fd1b
children d8ba911dce48
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 /*
5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
8 */
10 #define rdmsr(msr,val1,val2) \
11 __asm__ __volatile__("rdmsr" \
12 : "=a" (val1), "=d" (val2) \
13 : "c" (msr))
15 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
16 __asm__ __volatile__("rdmsr" \
17 : "=a" (a__), "=d" (b__) \
18 : "c" (msr)); \
19 val = a__ | (b__<<32); \
20 } while(0);
22 #define wrmsr(msr,val1,val2) \
23 __asm__ __volatile__("wrmsr" \
24 : /* no outputs */ \
25 : "c" (msr), "a" (val1), "d" (val2))
27 #define rdtsc(low,high) \
28 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
30 #define rdtscl(low) \
31 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
33 #if defined(__i386__)
34 #define rdtscll(val) \
35 __asm__ __volatile__("rdtsc" : "=A" (val))
36 #elif defined(__x86_64__)
37 #define rdtscll(val) do { \
38 unsigned int a,d; \
39 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
40 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
41 } while(0)
42 #endif
44 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
46 #define rdpmc(counter,low,high) \
47 __asm__ __volatile__("rdpmc" \
48 : "=a" (low), "=d" (high) \
49 : "c" (counter))
51 /* symbolic names for some interesting MSRs */
52 /* Intel defined MSRs. */
53 #define MSR_IA32_P5_MC_ADDR 0
54 #define MSR_IA32_P5_MC_TYPE 1
55 #define MSR_IA32_PLATFORM_ID 0x17
56 #define MSR_IA32_EBL_CR_POWERON 0x2a
58 /* AMD/K8 specific MSRs */
59 #define MSR_EFER 0xc0000080 /* extended feature register */
60 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
61 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
62 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
63 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
64 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
65 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
66 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */
67 /* EFER bits: */
68 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
69 #define _EFER_LME 8 /* Long mode enable */
70 #define _EFER_LMA 10 /* Long mode active (read-only) */
71 #define _EFER_NX 11 /* No execute enable */
73 #define EFER_SCE (1<<_EFER_SCE)
74 #define EFER_LME (1<<_EFER_LME)
75 #define EFER_LMA (1<<_EFER_LMA)
76 #define EFER_NX (1<<_EFER_NX)
78 /* Intel MSRs. Some also available on other CPUs */
79 #define MSR_IA32_PLATFORM_ID 0x17
81 #define MSR_IA32_PERFCTR0 0xc1
82 #define MSR_IA32_PERFCTR1 0xc2
84 #define MSR_MTRRcap 0x0fe
85 #define MSR_IA32_BBL_CR_CTL 0x119
87 #define MSR_IA32_SYSENTER_CS 0x174
88 #define MSR_IA32_SYSENTER_ESP 0x175
89 #define MSR_IA32_SYSENTER_EIP 0x176
91 #define MSR_IA32_MCG_CAP 0x179
92 #define MSR_IA32_MCG_STATUS 0x17a
93 #define MSR_IA32_MCG_CTL 0x17b
95 #define MSR_IA32_EVNTSEL0 0x186
96 #define MSR_IA32_EVNTSEL1 0x187
98 #define MSR_MTRRfix64K_00000 0x250
99 #define MSR_MTRRfix16K_80000 0x258
100 #define MSR_MTRRfix16K_A0000 0x259
101 #define MSR_MTRRfix4K_C0000 0x268
102 #define MSR_MTRRfix4K_C8000 0x269
103 #define MSR_MTRRfix4K_D0000 0x26a
104 #define MSR_MTRRfix4K_D8000 0x26b
105 #define MSR_MTRRfix4K_E0000 0x26c
106 #define MSR_MTRRfix4K_E8000 0x26d
107 #define MSR_MTRRfix4K_F0000 0x26e
108 #define MSR_MTRRfix4K_F8000 0x26f
109 #define MSR_MTRRdefType 0x2ff
111 #define MSR_IA32_MC0_CTL 0x400
112 #define MSR_IA32_MC0_STATUS 0x401
113 #define MSR_IA32_MC0_ADDR 0x402
114 #define MSR_IA32_MC0_MISC 0x403
116 #define MSR_IA32_DS_AREA 0x600
118 #define MSR_IA32_APICBASE 0x1b
119 #define MSR_IA32_APICBASE_BSP (1<<8)
120 #define MSR_IA32_APICBASE_ENABLE (1<<11)
121 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
123 #define MSR_IA32_UCODE_WRITE 0x79
124 #define MSR_IA32_UCODE_REV 0x8b
126 #define MSR_IA32_BBL_CR_CTL 0x119
128 #define MSR_IA32_MCG_CAP 0x179
129 #define MSR_IA32_MCG_STATUS 0x17a
130 #define MSR_IA32_MCG_CTL 0x17b
132 #define MSR_IA32_THERM_CONTROL 0x19a
133 #define MSR_IA32_THERM_INTERRUPT 0x19b
134 #define MSR_IA32_THERM_STATUS 0x19c
135 #define MSR_IA32_MISC_ENABLE 0x1a0
137 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
138 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
139 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
141 #define MSR_IA32_DEBUGCTLMSR 0x1d9
142 #define MSR_IA32_DEBUGCTLMSR_LBR (1<<0)
143 #define MSR_IA32_DEBUGCTLMSR_BTF (1<<1)
144 #define MSR_IA32_DEBUGCTLMSR_TR (1<<2)
145 #define MSR_IA32_DEBUGCTLMSR_BTS (1<<3)
146 #define MSR_IA32_DEBUGCTLMSR_BTINT (1<<4)
148 #define MSR_IA32_LASTBRANCH_TOS 0x1da
149 #define MSR_IA32_LASTBRANCH_0 0x1db
150 #define MSR_IA32_LASTBRANCH_1 0x1dc
151 #define MSR_IA32_LASTBRANCH_2 0x1dd
152 #define MSR_IA32_LASTBRANCH_3 0x1de
154 #define MSR_IA32_MC0_CTL 0x400
155 #define MSR_IA32_MC0_STATUS 0x401
156 #define MSR_IA32_MC0_ADDR 0x402
157 #define MSR_IA32_MC0_MISC 0x403
159 #define MSR_P6_PERFCTR0 0xc1
160 #define MSR_P6_PERFCTR1 0xc2
161 #define MSR_P6_EVNTSEL0 0x186
162 #define MSR_P6_EVNTSEL1 0x187
165 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
166 #define MSR_K7_EVNTSEL0 0xC0010000
167 #define MSR_K7_PERFCTR0 0xC0010004
168 #define MSR_K7_EVNTSEL1 0xC0010001
169 #define MSR_K7_PERFCTR1 0xC0010005
170 #define MSR_K7_EVNTSEL2 0xC0010002
171 #define MSR_K7_PERFCTR2 0xC0010006
172 #define MSR_K7_EVNTSEL3 0xC0010003
173 #define MSR_K7_PERFCTR3 0xC0010007
174 #define MSR_K8_TOP_MEM1 0xC001001A
175 #define MSR_K8_TOP_MEM2 0xC001001D
176 #define MSR_K8_SYSCFG 0xC0000010
177 #define MSR_K7_HWCR 0xC0010015
178 #define MSR_K7_CLK_CTL 0xC001001b
179 #define MSR_K7_FID_VID_CTL 0xC0010041
180 #define MSR_K7_VID_STATUS 0xC0010042
182 /* K6 MSRs */
183 #define MSR_K6_EFER 0xC0000080
184 #define MSR_K6_STAR 0xC0000081
185 #define MSR_K6_WHCR 0xC0000082
186 #define MSR_K6_UWCCR 0xC0000085
187 #define MSR_K6_EPMR 0xC0000086
188 #define MSR_K6_PSOR 0xC0000087
189 #define MSR_K6_PFIR 0xC0000088
191 /* Centaur-Hauls/IDT defined MSRs. */
192 #define MSR_IDT_FCR1 0x107
193 #define MSR_IDT_FCR2 0x108
194 #define MSR_IDT_FCR3 0x109
195 #define MSR_IDT_FCR4 0x10a
197 #define MSR_IDT_MCR0 0x110
198 #define MSR_IDT_MCR1 0x111
199 #define MSR_IDT_MCR2 0x112
200 #define MSR_IDT_MCR3 0x113
201 #define MSR_IDT_MCR4 0x114
202 #define MSR_IDT_MCR5 0x115
203 #define MSR_IDT_MCR6 0x116
204 #define MSR_IDT_MCR7 0x117
205 #define MSR_IDT_MCR_CTRL 0x120
207 /* VIA Cyrix defined MSRs*/
208 #define MSR_VIA_FCR 0x1107
209 #define MSR_VIA_LONGHAUL 0x110a
210 #define MSR_VIA_BCR2 0x1147
212 /* Transmeta defined MSRs */
213 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
214 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
215 #define MSR_TMTA_LRTI_READOUT 0x80868018
216 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
218 #endif /* __ASM_MSR_H */