debuggers.hg

view extras/mini-os/arch/ia64/__udivsi3.S @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
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children
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1 .file "__udivsi3.s"
3 // $FreeBSD: src/sys/libkern/ia64/__udivsi3.S,v 1.1.8.1 2005/01/31 23:26:21 imp Exp $
5 //-
6 // Copyright (c) 2000, Intel Corporation
7 // All rights reserved.
8 //
9 // Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache,
10 // Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab,
11 // Intel Corporation.
12 //
13 // WARRANTY DISCLAIMER
14 //
15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
19 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
22 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
23 // OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
24 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 //
27 // Intel Corporation is the author of this code, and requests that all
28 // problem reports or change requests be submitted to it directly at
29 // http://developer.intel.com/opensource.
30 //
32 .section .text
34 // 32-bit unsigned integer divide
36 .proc __udivsi3#
37 .align 32
38 .global __udivsi3#
39 .align 32
41 __udivsi3:
43 { .mii
44 alloc r31=ar.pfs,2,0,0,0
45 nop.i 0
46 nop.i 0;;
47 } { .mii
48 nop.m 0
50 // 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE
52 // general register used:
53 // r32 - 32-bit unsigned integer dividend
54 // r33 - 32-bit unsigned integer divisor
55 // r8 - 32-bit unsigned integer result
56 // r2 - scratch register
57 // floating-point registers used: f6, f7, f8, f9
58 // predicate registers used: p6
60 zxt4 r32=r32
61 zxt4 r33=r33;;
62 } { .mmb
63 setf.sig f6=r32
64 setf.sig f7=r33
65 nop.b 0;;
66 } { .mfi
67 nop.m 0
68 fcvt.xf f6=f6
69 nop.i 0
70 } { .mfi
71 nop.m 0
72 fcvt.xf f7=f7
73 mov r2 = 0x0ffdd;;
74 } { .mfi
75 setf.exp f9 = r2
76 // (1) y0
77 frcpa.s1 f8,p6=f6,f7
78 nop.i 0;;
79 } { .mfi
80 nop.m 0
81 // (2) q0 = a * y0
82 (p6) fma.s1 f6=f6,f8,f0
83 nop.i 0
84 } { .mfi
85 nop.m 0
86 // (3) e0 = 1 - b * y0
87 (p6) fnma.s1 f7=f7,f8,f1
88 nop.i 0;;
89 } { .mfi
90 nop.m 0
91 // (4) q1 = q0 + e0 * q0
92 (p6) fma.s1 f6=f7,f6,f6
93 nop.i 0
94 } { .mfi
95 nop.m 0
96 // (5) e1 = e0 * e0 + 2^-34
97 (p6) fma.s1 f7=f7,f7,f9
98 nop.i 0;;
99 } { .mfi
100 nop.m 0
101 // (6) q2 = q1 + e1 * q1
102 (p6) fma.s1 f8=f7,f6,f6
103 nop.i 0;;
104 } { .mfi
105 nop.m 0
106 // (7) q = trunc(q2)
107 fcvt.fxu.trunc.s1 f8=f8
108 nop.i 0;;
109 } { .mmi
110 // quotient will be in the least significant 32 bits of r8 (if b != 0)
111 getf.sig r8=f8
112 nop.m 0
113 nop.i 0;;
114 }
116 // 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE
118 { .mmb
119 nop.m 0
120 nop.m 0
121 br.ret.sptk b0;;
122 }
124 .endp __udivsi3