debuggers.hg

view tools/debugger/xenitp/cpu-ia64-opc.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
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1 /* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
2 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21 /* Logically, this code should be part of libopcode but since some of
22 the operand insertion/extraction functions help bfd to implement
23 relocations, this code is included as part of cpu-ia64.c. This
24 avoids circular dependencies between libopcode and libbfd and also
25 obviates the need for applications to link in libopcode when all
26 they really want is libbfd.
28 --davidm Mon Apr 13 22:14:02 1998 */
30 #include "ia64-opc.h"
32 #define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
34 static const char*
35 ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
36 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
37 {
38 return "internal error---this shouldn't happen";
39 }
41 static const char*
42 ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
43 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
44 {
45 return "internal error---this shouldn't happen";
46 }
48 static const char*
49 ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
50 ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
51 {
52 return 0;
53 }
55 static const char*
56 ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
57 ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
58 {
59 return 0;
60 }
62 static const char*
63 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
64 {
65 if (value >= 1u << self->field[0].bits)
66 return "register number out of range";
68 *code |= value << self->field[0].shift;
69 return 0;
70 }
72 static const char*
73 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
74 {
75 *valuep = ((code >> self->field[0].shift)
76 & ((1u << self->field[0].bits) - 1));
77 return 0;
78 }
80 static const char*
81 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
82 {
83 ia64_insn new = 0;
84 int i;
86 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
87 {
88 new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
89 << self->field[i].shift);
90 value >>= self->field[i].bits;
91 }
92 if (value)
93 return "integer operand out of range";
95 *code |= new;
96 return 0;
97 }
99 static const char*
100 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
101 {
102 BFD_HOST_U_64_BIT value = 0;
103 int i, bits = 0, total = 0;
105 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
106 {
107 bits = self->field[i].bits;
108 value |= ((code >> self->field[i].shift)
109 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
110 total += bits;
111 }
112 *valuep = value;
113 return 0;
114 }
116 static const char*
117 ins_immu5b (const struct ia64_operand *self, ia64_insn value,
118 ia64_insn *code)
119 {
120 if (value < 32 || value > 63)
121 return "value must be between 32 and 63";
122 return ins_immu (self, value - 32, code);
123 }
125 static const char*
126 ext_immu5b (const struct ia64_operand *self, ia64_insn code,
127 ia64_insn *valuep)
128 {
129 const char *result;
131 result = ext_immu (self, code, valuep);
132 if (result)
133 return result;
135 *valuep = *valuep + 32;
136 return 0;
137 }
139 static const char*
140 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
141 {
142 if (value & 0x7)
143 return "value not an integer multiple of 8";
144 return ins_immu (self, value >> 3, code);
145 }
147 static const char*
148 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
149 {
150 const char *result;
152 result = ext_immu (self, code, valuep);
153 if (result)
154 return result;
156 *valuep = *valuep << 3;
157 return 0;
158 }
160 static const char*
161 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
162 ia64_insn *code, int scale)
163 {
164 BFD_HOST_64_BIT svalue = value, sign_bit = 0;
165 ia64_insn new = 0;
166 int i;
168 svalue >>= scale;
170 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
171 {
172 new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
173 << self->field[i].shift);
174 sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
175 svalue >>= self->field[i].bits;
176 }
177 if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
178 return "integer operand out of range";
180 *code |= new;
181 return 0;
182 }
184 static const char*
185 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
186 ia64_insn *valuep, int scale)
187 {
188 int i, bits = 0, total = 0;
189 BFD_HOST_64_BIT val = 0, sign;
191 for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
192 {
193 bits = self->field[i].bits;
194 val |= ((code >> self->field[i].shift)
195 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
196 total += bits;
197 }
198 /* sign extend: */
199 sign = (BFD_HOST_64_BIT) 1 << (total - 1);
200 val = (val ^ sign) - sign;
202 *valuep = (val << scale);
203 return 0;
204 }
206 static const char*
207 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
208 {
209 return ins_imms_scaled (self, value, code, 0);
210 }
212 static const char*
213 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
214 {
215 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
217 return ins_imms_scaled (self, value, code, 0);
218 }
220 static const char*
221 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
222 {
223 return ext_imms_scaled (self, code, valuep, 0);
224 }
226 static const char*
227 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
228 {
229 --value;
230 return ins_imms_scaled (self, value, code, 0);
231 }
233 static const char*
234 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
235 ia64_insn *code)
236 {
237 value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
239 --value;
240 return ins_imms_scaled (self, value, code, 0);
241 }
243 static const char*
244 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
245 {
246 const char *res = ext_imms_scaled (self, code, valuep, 0);
248 ++*valuep;
249 return res;
250 }
252 static const char*
253 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
254 {
255 return ins_imms_scaled (self, value, code, 1);
256 }
258 static const char*
259 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
260 {
261 return ext_imms_scaled (self, code, valuep, 1);
262 }
264 static const char*
265 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
266 {
267 return ins_imms_scaled (self, value, code, 4);
268 }
270 static const char*
271 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
272 {
273 return ext_imms_scaled (self, code, valuep, 4);
274 }
276 static const char*
277 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
278 {
279 return ins_imms_scaled (self, value, code, 16);
280 }
282 static const char*
283 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
284 {
285 return ext_imms_scaled (self, code, valuep, 16);
286 }
288 static const char*
289 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
290 {
291 ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
292 return ins_immu (self, value ^ mask, code);
293 }
295 static const char*
296 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
297 {
298 const char *result;
299 ia64_insn mask;
301 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
302 result = ext_immu (self, code, valuep);
303 if (!result)
304 {
305 mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
306 *valuep ^= mask;
307 }
308 return result;
309 }
311 static const char*
312 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
313 {
314 --value;
315 if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
316 return "count out of range";
318 *code |= value << self->field[0].shift;
319 return 0;
320 }
322 static const char*
323 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
324 {
325 *valuep = ((code >> self->field[0].shift)
326 & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
327 return 0;
328 }
330 static const char*
331 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
332 {
333 --value;
335 if (value > 2)
336 return "count must be in range 1..3";
338 *code |= value << self->field[0].shift;
339 return 0;
340 }
342 static const char*
343 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
344 {
345 *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
346 return 0;
347 }
349 static const char*
350 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
351 {
352 switch (value)
353 {
354 case 0: value = 0; break;
355 case 7: value = 1; break;
356 case 15: value = 2; break;
357 case 16: value = 3; break;
358 default: return "count must be 0, 7, 15, or 16";
359 }
360 *code |= value << self->field[0].shift;
361 return 0;
362 }
364 static const char*
365 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
366 {
367 ia64_insn value;
369 value = (code >> self->field[0].shift) & 0x3;
370 switch (value)
371 {
372 case 0: value = 0; break;
373 case 1: value = 7; break;
374 case 2: value = 15; break;
375 case 3: value = 16; break;
376 }
377 *valuep = value;
378 return 0;
379 }
381 static const char*
382 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
383 {
384 BFD_HOST_64_BIT val = value;
385 BFD_HOST_U_64_BIT sign = 0;
387 if (val < 0)
388 {
389 sign = 0x4;
390 value = -value;
391 }
392 switch (value)
393 {
394 case 1: value = 3; break;
395 case 4: value = 2; break;
396 case 8: value = 1; break;
397 case 16: value = 0; break;
398 default: return "count must be +/- 1, 4, 8, or 16";
399 }
400 *code |= (sign | value) << self->field[0].shift;
401 return 0;
402 }
404 static const char*
405 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
406 {
407 BFD_HOST_64_BIT val;
408 int negate;
410 val = (code >> self->field[0].shift) & 0x7;
411 negate = val & 0x4;
412 switch (val & 0x3)
413 {
414 case 0: val = 16; break;
415 case 1: val = 8; break;
416 case 2: val = 4; break;
417 case 3: val = 1; break;
418 }
419 if (negate)
420 val = -val;
422 *valuep = val;
423 return 0;
424 }
426 #define CST IA64_OPND_CLASS_CST
427 #define REG IA64_OPND_CLASS_REG
428 #define IND IA64_OPND_CLASS_IND
429 #define ABS IA64_OPND_CLASS_ABS
430 #define REL IA64_OPND_CLASS_REL
432 #define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
433 #define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
435 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
436 {
437 /* constants: */
438 { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
439 { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
440 { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
441 { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
442 { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
443 { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
444 { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
445 { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
446 { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
447 { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
448 { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
449 { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
450 { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
451 { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
453 /* register operands: */
454 { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
455 "an application register" },
456 { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
457 "a branch register" },
458 { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
459 "a branch register"},
460 { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
461 "a control register"},
462 { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
463 "a floating-point register" },
464 { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
465 "a floating-point register" },
466 { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
467 "a floating-point register" },
468 { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
469 "a floating-point register" },
470 { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
471 "a predicate register" },
472 { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
473 "a predicate register" },
474 { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
475 "a general register" },
476 { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
477 "a general register" },
478 { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
479 "a general register" },
480 { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
481 "a general register r0-r3" },
483 /* memory operands: */
484 { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
485 "a memory address" },
487 /* indirect operands: */
488 { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
489 "a cpuid register" },
490 { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
491 "a dbr register" },
492 { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
493 "a dtr register" },
494 { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
495 "an itr register" },
496 { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
497 "an ibr register" },
498 { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
499 "an msr register" },
500 { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
501 "a pkr register" },
502 { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
503 "a pmc register" },
504 { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
505 "a pmd register" },
506 { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
507 "an rr register" },
509 /* immediate operands: */
510 { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
511 "a 5-bit count (0-31)" },
512 { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
513 "a 2-bit count (1-4)" },
514 { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
515 "a 2-bit count (1-3)" },
516 { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
517 "a count (0, 7, 15, or 16)" },
518 { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
519 "a 5-bit count (0-31)" },
520 { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
521 "a 6-bit count (0-63)" },
522 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
523 "a 6-bit bit pos (0-63)" },
524 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
525 "a 6-bit bit pos (0-63)" },
526 { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
527 "a 6-bit bit pos (0-63)" },
528 { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
529 "a 1-bit integer (-1, 0)" },
530 { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
531 "a 2-bit unsigned (0-3)" },
532 { ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */
533 "a 5-bit unsigned (32 + (0-31))" },
534 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
535 "a 7-bit unsigned (0-127)" },
536 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
537 "a 7-bit unsigned (0-127)" },
538 { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
539 "a frame size (register count)" },
540 { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
541 "a local register count" },
542 { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
543 "a rotating register count (integer multiple of 8)" },
544 { ABS, ins_imms, ext_imms, 0, /* IMM8 */
545 {{ 7, 13}, { 1, 36}}, SDEC,
546 "an 8-bit integer (-128-127)" },
547 { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
548 {{ 7, 13}, { 1, 36}}, SDEC,
549 "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
550 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
551 {{ 7, 13}, { 1, 36}}, SDEC,
552 "an 8-bit integer (-127-128)" },
553 { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
554 {{ 7, 13}, { 1, 36}}, SDEC,
555 "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
556 { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
557 {{ 7, 13}, { 1, 36}}, SDEC,
558 "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
559 { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
560 "a 9-bit unsigned (0-511)" },
561 { ABS, ins_imms, ext_imms, 0, /* IMM9a */
562 {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
563 "a 9-bit integer (-256-255)" },
564 { ABS, ins_imms, ext_imms, 0, /* IMM9b */
565 {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
566 "a 9-bit integer (-256-255)" },
567 { ABS, ins_imms, ext_imms, 0, /* IMM14 */
568 {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
569 "a 14-bit integer (-8192-8191)" },
570 { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
571 {{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
572 "a 17-bit integer (-65536-65535)" },
573 { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
574 "a 21-bit unsigned" },
575 { ABS, ins_imms, ext_imms, 0, /* IMM22 */
576 {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
577 "a 22-bit signed integer" },
578 { ABS, ins_immu, ext_immu, 0, /* IMMU24 */
579 {{21, 6}, { 2, 31}, { 1, 36}}, 0,
580 "a 24-bit unsigned" },
581 { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
582 "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
583 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
584 "a 62-bit unsigned" },
585 { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
586 "a 64-bit unsigned" },
587 { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
588 "an increment (+/- 1, 4, 8, or 16)" },
589 { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
590 "a 4-bit length (1-16)" },
591 { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
592 "a 6-bit length (1-64)" },
593 { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
594 "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
595 { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
596 "an 8-bit mix type" },
597 { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
598 "a 6-bit bit pos (0-63)" },
599 { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
600 "a branch tag" },
601 { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
602 "a branch tag" },
603 { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
604 "a branch target" },
605 { REL, ins_imms4, ext_imms4, 0, /* TGT25b */
606 {{ 7, 6}, {13, 20}, { 1, 36}}, 0,
607 "a branch target" },
608 { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
609 "a branch target" },
610 { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
611 "a branch target" },
613 { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
614 "ldxmov target" },
615 };