debuggers.hg

view tools/ioemu/hw/apic.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
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1 /*
2 * APIC support
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "vl.h"
22 //#define DEBUG_APIC
23 //#define DEBUG_IOAPIC
25 /* APIC Local Vector Table */
26 #define APIC_LVT_TIMER 0
27 #define APIC_LVT_THERMAL 1
28 #define APIC_LVT_PERFORM 2
29 #define APIC_LVT_LINT0 3
30 #define APIC_LVT_LINT1 4
31 #define APIC_LVT_ERROR 5
32 #define APIC_LVT_NB 6
34 /* APIC delivery modes */
35 #define APIC_DM_FIXED 0
36 #define APIC_DM_LOWPRI 1
37 #define APIC_DM_SMI 2
38 #define APIC_DM_NMI 4
39 #define APIC_DM_INIT 5
40 #define APIC_DM_SIPI 6
41 #define APIC_DM_EXTINT 7
43 /* APIC destination mode */
44 #define APIC_DESTMODE_FLAT 0xf
45 #define APIC_DESTMODE_CLUSTER 1
47 #define APIC_TRIGGER_EDGE 0
48 #define APIC_TRIGGER_LEVEL 1
50 #define APIC_LVT_TIMER_PERIODIC (1<<17)
51 #define APIC_LVT_MASKED (1<<16)
52 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
53 #define APIC_LVT_REMOTE_IRR (1<<14)
54 #define APIC_INPUT_POLARITY (1<<13)
55 #define APIC_SEND_PENDING (1<<12)
57 #define IOAPIC_NUM_PINS 0x18
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
63 #define MAX_APICS 255
64 #define MAX_APIC_WORDS 8
66 typedef struct APICState {
67 CPUState *cpu_env;
68 uint32_t apicbase;
69 uint8_t id;
70 uint8_t arb_id;
71 uint8_t tpr;
72 uint32_t spurious_vec;
73 uint8_t log_dest;
74 uint8_t dest_mode;
75 uint32_t isr[8]; /* in service register */
76 uint32_t tmr[8]; /* trigger mode register */
77 uint32_t irr[8]; /* interrupt request register */
78 uint32_t lvt[APIC_LVT_NB];
79 uint32_t esr; /* error register */
80 uint32_t icr[2];
82 uint32_t divide_conf;
83 int count_shift;
84 uint32_t initial_count;
85 int64_t initial_count_load_time, next_time;
86 QEMUTimer *timer;
87 } APICState;
89 struct IOAPICState {
90 uint8_t id;
91 uint8_t ioregsel;
93 uint32_t irr;
94 uint64_t ioredtbl[IOAPIC_NUM_PINS];
95 };
97 static int apic_io_memory;
98 static APICState *local_apics[MAX_APICS + 1];
99 static int last_apic_id = 0;
101 static void apic_init_ipi(APICState *s);
102 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
103 static void apic_update_irq(APICState *s);
105 /* Find first bit starting from msb. Return 0 if value = 0 */
106 static int fls_bit(uint32_t value)
107 {
108 unsigned int ret = 0;
110 #if defined(HOST_I386)
111 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
112 return ret;
113 #else
114 if (value > 0xffff)
115 value >>= 16, ret = 16;
116 if (value > 0xff)
117 value >>= 8, ret += 8;
118 if (value > 0xf)
119 value >>= 4, ret += 4;
120 if (value > 0x3)
121 value >>= 2, ret += 2;
122 return ret + (value >> 1);
123 #endif
124 }
126 /* Find first bit starting from lsb. Return 0 if value = 0 */
127 static int ffs_bit(uint32_t value)
128 {
129 unsigned int ret = 0;
131 #if defined(HOST_I386)
132 __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
133 return ret;
134 #else
135 if (!value)
136 return 0;
137 if (!(value & 0xffff))
138 value >>= 16, ret = 16;
139 if (!(value & 0xff))
140 value >>= 8, ret += 8;
141 if (!(value & 0xf))
142 value >>= 4, ret += 4;
143 if (!(value & 0x3))
144 value >>= 2, ret += 2;
145 if (!(value & 0x1))
146 ret++;
147 return ret;
148 #endif
149 }
151 static inline void set_bit(uint32_t *tab, int index)
152 {
153 int i, mask;
154 i = index >> 5;
155 mask = 1 << (index & 0x1f);
156 tab[i] |= mask;
157 }
159 static inline void reset_bit(uint32_t *tab, int index)
160 {
161 int i, mask;
162 i = index >> 5;
163 mask = 1 << (index & 0x1f);
164 tab[i] &= ~mask;
165 }
167 #define foreach_apic(apic, deliver_bitmask, code) \
168 {\
169 int __i, __j, __mask;\
170 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
171 __mask = deliver_bitmask[__i];\
172 if (__mask) {\
173 for(__j = 0; __j < 32; __j++) {\
174 if (__mask & (1 << __j)) {\
175 apic = local_apics[__i * 32 + __j];\
176 if (apic) {\
177 code;\
178 }\
179 }\
180 }\
181 }\
182 }\
183 }
185 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
186 uint8_t delivery_mode,
187 uint8_t vector_num, uint8_t polarity,
188 uint8_t trigger_mode)
189 {
190 APICState *apic_iter;
192 switch (delivery_mode) {
193 case APIC_DM_LOWPRI:
194 /* XXX: search for focus processor, arbitration */
195 {
196 int i, d;
197 d = -1;
198 for(i = 0; i < MAX_APIC_WORDS; i++) {
199 if (deliver_bitmask[i]) {
200 d = i * 32 + ffs_bit(deliver_bitmask[i]);
201 break;
202 }
203 }
204 if (d >= 0) {
205 apic_iter = local_apics[d];
206 if (apic_iter) {
207 apic_set_irq(apic_iter, vector_num, trigger_mode);
208 }
209 }
210 }
211 return;
213 case APIC_DM_FIXED:
214 break;
216 case APIC_DM_SMI:
217 case APIC_DM_NMI:
218 break;
220 case APIC_DM_INIT:
221 /* normal INIT IPI sent to processors */
222 foreach_apic(apic_iter, deliver_bitmask,
223 apic_init_ipi(apic_iter) );
224 return;
226 case APIC_DM_EXTINT:
227 /* handled in I/O APIC code */
228 break;
230 default:
231 return;
232 }
234 foreach_apic(apic_iter, deliver_bitmask,
235 apic_set_irq(apic_iter, vector_num, trigger_mode) );
236 }
238 void cpu_set_apic_base(CPUState *env, uint64_t val)
239 {
240 APICState *s = env->apic_state;
241 #ifdef DEBUG_APIC
242 printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
243 #endif
244 s->apicbase = (val & 0xfffff000) |
245 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
246 /* if disabled, cannot be enabled again */
247 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
248 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
249 env->cpuid_features &= ~CPUID_APIC;
250 s->spurious_vec &= ~APIC_SV_ENABLE;
251 }
252 }
254 uint64_t cpu_get_apic_base(CPUState *env)
255 {
256 APICState *s = env->apic_state;
257 #ifdef DEBUG_APIC
258 printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
259 #endif
260 return s->apicbase;
261 }
263 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
264 {
265 APICState *s = env->apic_state;
266 s->tpr = (val & 0x0f) << 4;
267 apic_update_irq(s);
268 }
270 uint8_t cpu_get_apic_tpr(CPUX86State *env)
271 {
272 APICState *s = env->apic_state;
273 return s->tpr >> 4;
274 }
276 /* return -1 if no bit is set */
277 static int get_highest_priority_int(uint32_t *tab)
278 {
279 int i;
280 for(i = 7; i >= 0; i--) {
281 if (tab[i] != 0) {
282 return i * 32 + fls_bit(tab[i]);
283 }
284 }
285 return -1;
286 }
288 static int apic_get_ppr(APICState *s)
289 {
290 int tpr, isrv, ppr;
292 tpr = (s->tpr >> 4);
293 isrv = get_highest_priority_int(s->isr);
294 if (isrv < 0)
295 isrv = 0;
296 isrv >>= 4;
297 if (tpr >= isrv)
298 ppr = s->tpr;
299 else
300 ppr = isrv << 4;
301 return ppr;
302 }
304 static int apic_get_arb_pri(APICState *s)
305 {
306 /* XXX: arbitration */
307 return 0;
308 }
310 /* signal the CPU if an irq is pending */
311 static void apic_update_irq(APICState *s)
312 {
313 int irrv, ppr;
314 if (!(s->spurious_vec & APIC_SV_ENABLE))
315 return;
316 irrv = get_highest_priority_int(s->irr);
317 if (irrv < 0)
318 return;
319 ppr = apic_get_ppr(s);
320 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
321 return;
322 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
323 }
325 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
326 {
327 set_bit(s->irr, vector_num);
328 if (trigger_mode)
329 set_bit(s->tmr, vector_num);
330 else
331 reset_bit(s->tmr, vector_num);
332 apic_update_irq(s);
333 }
335 static void apic_eoi(APICState *s)
336 {
337 int isrv;
338 isrv = get_highest_priority_int(s->isr);
339 if (isrv < 0)
340 return;
341 reset_bit(s->isr, isrv);
342 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
343 set the remote IRR bit for level triggered interrupts. */
344 apic_update_irq(s);
345 }
347 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
348 uint8_t dest, uint8_t dest_mode)
349 {
350 APICState *apic_iter;
351 int i;
353 if (dest_mode == 0) {
354 if (dest == 0xff) {
355 memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
356 } else {
357 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
358 set_bit(deliver_bitmask, dest);
359 }
360 } else {
361 /* XXX: cluster mode */
362 memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
363 for(i = 0; i < MAX_APICS; i++) {
364 apic_iter = local_apics[i];
365 if (apic_iter) {
366 if (apic_iter->dest_mode == 0xf) {
367 if (dest & apic_iter->log_dest)
368 set_bit(deliver_bitmask, i);
369 } else if (apic_iter->dest_mode == 0x0) {
370 if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
371 (dest & apic_iter->log_dest & 0x0f)) {
372 set_bit(deliver_bitmask, i);
373 }
374 }
375 }
376 }
377 }
378 }
381 static void apic_init_ipi(APICState *s)
382 {
383 int i;
385 s->tpr = 0;
386 s->spurious_vec = 0xff;
387 s->log_dest = 0;
388 s->dest_mode = 0xf;
389 memset(s->isr, 0, sizeof(s->isr));
390 memset(s->tmr, 0, sizeof(s->tmr));
391 memset(s->irr, 0, sizeof(s->irr));
392 for(i = 0; i < APIC_LVT_NB; i++)
393 s->lvt[i] = 1 << 16; /* mask LVT */
394 s->esr = 0;
395 memset(s->icr, 0, sizeof(s->icr));
396 s->divide_conf = 0;
397 s->count_shift = 0;
398 s->initial_count = 0;
399 s->initial_count_load_time = 0;
400 s->next_time = 0;
401 }
403 /* send a SIPI message to the CPU to start it */
404 static void apic_startup(APICState *s, int vector_num)
405 {
406 CPUState *env = s->cpu_env;
407 if (!(env->hflags & HF_HALTED_MASK))
408 return;
409 env->eip = 0;
410 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
411 0xffff, 0);
412 env->hflags &= ~HF_HALTED_MASK;
413 }
415 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
416 uint8_t delivery_mode, uint8_t vector_num,
417 uint8_t polarity, uint8_t trigger_mode)
418 {
419 uint32_t deliver_bitmask[MAX_APIC_WORDS];
420 int dest_shorthand = (s->icr[0] >> 18) & 3;
421 APICState *apic_iter;
423 switch (dest_shorthand) {
424 case 0:
425 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
426 break;
427 case 1:
428 memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
429 set_bit(deliver_bitmask, s->id);
430 break;
431 case 2:
432 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
433 break;
434 case 3:
435 memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
436 reset_bit(deliver_bitmask, s->id);
437 break;
438 }
440 switch (delivery_mode) {
441 case APIC_DM_INIT:
442 {
443 int trig_mode = (s->icr[0] >> 15) & 1;
444 int level = (s->icr[0] >> 14) & 1;
445 if (level == 0 && trig_mode == 1) {
446 foreach_apic(apic_iter, deliver_bitmask,
447 apic_iter->arb_id = apic_iter->id );
448 return;
449 }
450 }
451 break;
453 case APIC_DM_SIPI:
454 foreach_apic(apic_iter, deliver_bitmask,
455 apic_startup(apic_iter, vector_num) );
456 return;
457 }
459 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
460 trigger_mode);
461 }
463 int apic_get_interrupt(CPUState *env)
464 {
465 APICState *s = env->apic_state;
466 int intno;
468 /* if the APIC is installed or enabled, we let the 8259 handle the
469 IRQs */
470 if (!s)
471 return -1;
472 if (!(s->spurious_vec & APIC_SV_ENABLE))
473 return -1;
475 /* XXX: spurious IRQ handling */
476 intno = get_highest_priority_int(s->irr);
477 if (intno < 0)
478 return -1;
479 if (s->tpr && intno <= s->tpr)
480 return s->spurious_vec & 0xff;
481 reset_bit(s->irr, intno);
482 set_bit(s->isr, intno);
483 apic_update_irq(s);
484 return intno;
485 }
487 static uint32_t apic_get_current_count(APICState *s)
488 {
489 int64_t d;
490 uint32_t val;
491 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
492 s->count_shift;
493 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
494 /* periodic */
495 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
496 } else {
497 if (d >= s->initial_count)
498 val = 0;
499 else
500 val = s->initial_count - d;
501 }
502 return val;
503 }
505 static void apic_timer_update(APICState *s, int64_t current_time)
506 {
507 int64_t next_time, d;
509 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
510 d = (current_time - s->initial_count_load_time) >>
511 s->count_shift;
512 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
513 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
514 } else {
515 if (d >= s->initial_count)
516 goto no_timer;
517 d = (uint64_t)s->initial_count + 1;
518 }
519 next_time = s->initial_count_load_time + (d << s->count_shift);
520 qemu_mod_timer(s->timer, next_time);
521 s->next_time = next_time;
522 } else {
523 no_timer:
524 qemu_del_timer(s->timer);
525 }
526 }
528 static void apic_timer(void *opaque)
529 {
530 APICState *s = opaque;
532 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
533 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
534 }
535 apic_timer_update(s, s->next_time);
536 }
538 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
539 {
540 return 0;
541 }
543 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
544 {
545 return 0;
546 }
548 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
549 {
550 }
552 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
553 {
554 }
556 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
557 {
558 CPUState *env;
559 APICState *s;
560 uint32_t val;
561 int index;
563 env = cpu_single_env;
564 if (!env)
565 return 0;
566 s = env->apic_state;
568 index = (addr >> 4) & 0xff;
569 switch(index) {
570 case 0x02: /* id */
571 val = s->id << 24;
572 break;
573 case 0x03: /* version */
574 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
575 break;
576 case 0x08:
577 val = s->tpr;
578 break;
579 case 0x09:
580 val = apic_get_arb_pri(s);
581 break;
582 case 0x0a:
583 /* ppr */
584 val = apic_get_ppr(s);
585 break;
586 case 0x0d:
587 val = s->log_dest << 24;
588 break;
589 case 0x0e:
590 val = s->dest_mode << 28;
591 break;
592 case 0x0f:
593 val = s->spurious_vec;
594 break;
595 case 0x10 ... 0x17:
596 val = s->isr[index & 7];
597 break;
598 case 0x18 ... 0x1f:
599 val = s->tmr[index & 7];
600 break;
601 case 0x20 ... 0x27:
602 val = s->irr[index & 7];
603 break;
604 case 0x28:
605 val = s->esr;
606 break;
607 case 0x30:
608 case 0x31:
609 val = s->icr[index & 1];
610 break;
611 case 0x32 ... 0x37:
612 val = s->lvt[index - 0x32];
613 break;
614 case 0x38:
615 val = s->initial_count;
616 break;
617 case 0x39:
618 val = apic_get_current_count(s);
619 break;
620 case 0x3e:
621 val = s->divide_conf;
622 break;
623 default:
624 s->esr |= ESR_ILLEGAL_ADDRESS;
625 val = 0;
626 break;
627 }
628 #ifdef DEBUG_APIC
629 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
630 #endif
631 return val;
632 }
634 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
635 {
636 CPUState *env;
637 APICState *s;
638 int index;
640 env = cpu_single_env;
641 if (!env)
642 return;
643 s = env->apic_state;
645 #ifdef DEBUG_APIC
646 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
647 #endif
649 index = (addr >> 4) & 0xff;
650 switch(index) {
651 case 0x02:
652 s->id = (val >> 24);
653 break;
654 case 0x03:
655 break;
656 case 0x08:
657 s->tpr = val;
658 apic_update_irq(s);
659 break;
660 case 0x09:
661 case 0x0a:
662 break;
663 case 0x0b: /* EOI */
664 apic_eoi(s);
665 break;
666 case 0x0d:
667 s->log_dest = val >> 24;
668 break;
669 case 0x0e:
670 s->dest_mode = val >> 28;
671 break;
672 case 0x0f:
673 s->spurious_vec = val & 0x1ff;
674 apic_update_irq(s);
675 break;
676 case 0x10 ... 0x17:
677 case 0x18 ... 0x1f:
678 case 0x20 ... 0x27:
679 case 0x28:
680 break;
681 case 0x30:
682 s->icr[0] = val;
683 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
684 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
685 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
686 break;
687 case 0x31:
688 s->icr[1] = val;
689 break;
690 case 0x32 ... 0x37:
691 {
692 int n = index - 0x32;
693 s->lvt[n] = val;
694 if (n == APIC_LVT_TIMER)
695 apic_timer_update(s, qemu_get_clock(vm_clock));
696 }
697 break;
698 case 0x38:
699 s->initial_count = val;
700 s->initial_count_load_time = qemu_get_clock(vm_clock);
701 apic_timer_update(s, s->initial_count_load_time);
702 break;
703 case 0x39:
704 break;
705 case 0x3e:
706 {
707 int v;
708 s->divide_conf = val & 0xb;
709 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
710 s->count_shift = (v + 1) & 7;
711 }
712 break;
713 default:
714 s->esr |= ESR_ILLEGAL_ADDRESS;
715 break;
716 }
717 }
719 static void apic_save(QEMUFile *f, void *opaque)
720 {
721 APICState *s = opaque;
722 int i;
724 qemu_put_be32s(f, &s->apicbase);
725 qemu_put_8s(f, &s->id);
726 qemu_put_8s(f, &s->arb_id);
727 qemu_put_8s(f, &s->tpr);
728 qemu_put_be32s(f, &s->spurious_vec);
729 qemu_put_8s(f, &s->log_dest);
730 qemu_put_8s(f, &s->dest_mode);
731 for (i = 0; i < 8; i++) {
732 qemu_put_be32s(f, &s->isr[i]);
733 qemu_put_be32s(f, &s->tmr[i]);
734 qemu_put_be32s(f, &s->irr[i]);
735 }
736 for (i = 0; i < APIC_LVT_NB; i++) {
737 qemu_put_be32s(f, &s->lvt[i]);
738 }
739 qemu_put_be32s(f, &s->esr);
740 qemu_put_be32s(f, &s->icr[0]);
741 qemu_put_be32s(f, &s->icr[1]);
742 qemu_put_be32s(f, &s->divide_conf);
743 qemu_put_be32s(f, &s->count_shift);
744 qemu_put_be32s(f, &s->initial_count);
745 qemu_put_be64s(f, &s->initial_count_load_time);
746 qemu_put_be64s(f, &s->next_time);
748 qemu_put_timer(f, s->timer);
749 }
751 static int apic_load(QEMUFile *f, void *opaque, int version_id)
752 {
753 APICState *s = opaque;
754 int i;
756 if (version_id > 2)
757 return -EINVAL;
759 /* XXX: what if the base changes? (registered memory regions) */
760 qemu_get_be32s(f, &s->apicbase);
761 qemu_get_8s(f, &s->id);
762 qemu_get_8s(f, &s->arb_id);
763 qemu_get_8s(f, &s->tpr);
764 qemu_get_be32s(f, &s->spurious_vec);
765 qemu_get_8s(f, &s->log_dest);
766 qemu_get_8s(f, &s->dest_mode);
767 for (i = 0; i < 8; i++) {
768 qemu_get_be32s(f, &s->isr[i]);
769 qemu_get_be32s(f, &s->tmr[i]);
770 qemu_get_be32s(f, &s->irr[i]);
771 }
772 for (i = 0; i < APIC_LVT_NB; i++) {
773 qemu_get_be32s(f, &s->lvt[i]);
774 }
775 qemu_get_be32s(f, &s->esr);
776 qemu_get_be32s(f, &s->icr[0]);
777 qemu_get_be32s(f, &s->icr[1]);
778 qemu_get_be32s(f, &s->divide_conf);
779 qemu_get_be32s(f, &s->count_shift);
780 qemu_get_be32s(f, &s->initial_count);
781 qemu_get_be64s(f, &s->initial_count_load_time);
782 qemu_get_be64s(f, &s->next_time);
784 if (version_id >= 2)
785 qemu_get_timer(f, s->timer);
786 return 0;
787 }
789 static void apic_reset(void *opaque)
790 {
791 APICState *s = opaque;
792 apic_init_ipi(s);
793 }
795 static CPUReadMemoryFunc *apic_mem_read[3] = {
796 apic_mem_readb,
797 apic_mem_readw,
798 apic_mem_readl,
799 };
801 static CPUWriteMemoryFunc *apic_mem_write[3] = {
802 apic_mem_writeb,
803 apic_mem_writew,
804 apic_mem_writel,
805 };
807 int apic_init(CPUState *env)
808 {
809 APICState *s;
811 if (last_apic_id >= MAX_APICS)
812 return -1;
813 s = qemu_mallocz(sizeof(APICState));
814 if (!s)
815 return -1;
816 env->apic_state = s;
817 apic_init_ipi(s);
818 s->id = last_apic_id++;
819 s->cpu_env = env;
820 s->apicbase = 0xfee00000 |
821 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
823 /* XXX: mapping more APICs at the same memory location */
824 if (apic_io_memory == 0) {
825 /* NOTE: the APIC is directly connected to the CPU - it is not
826 on the global memory bus. */
827 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
828 apic_mem_write, NULL);
829 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
830 apic_io_memory);
831 }
832 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
834 register_savevm("apic", 0, 2, apic_save, apic_load, s);
835 qemu_register_reset(apic_reset, s);
837 local_apics[s->id] = s;
838 return 0;
839 }
841 static void ioapic_service(IOAPICState *s)
842 {
843 uint8_t i;
844 uint8_t trig_mode;
845 uint8_t vector;
846 uint8_t delivery_mode;
847 uint32_t mask;
848 uint64_t entry;
849 uint8_t dest;
850 uint8_t dest_mode;
851 uint8_t polarity;
852 uint32_t deliver_bitmask[MAX_APIC_WORDS];
854 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
855 mask = 1 << i;
856 if (s->irr & mask) {
857 entry = s->ioredtbl[i];
858 if (!(entry & APIC_LVT_MASKED)) {
859 trig_mode = ((entry >> 15) & 1);
860 dest = entry >> 56;
861 dest_mode = (entry >> 11) & 1;
862 delivery_mode = (entry >> 8) & 7;
863 polarity = (entry >> 13) & 1;
864 if (trig_mode == APIC_TRIGGER_EDGE)
865 s->irr &= ~mask;
866 if (delivery_mode == APIC_DM_EXTINT)
867 vector = pic_read_irq(isa_pic);
868 else
869 vector = entry & 0xff;
871 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
872 apic_bus_deliver(deliver_bitmask, delivery_mode,
873 vector, polarity, trig_mode);
874 }
875 }
876 }
877 }
879 void ioapic_set_irq(void *opaque, int vector, int level)
880 {
881 IOAPICState *s = opaque;
883 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
884 uint32_t mask = 1 << vector;
885 uint64_t entry = s->ioredtbl[vector];
887 if ((entry >> 15) & 1) {
888 /* level triggered */
889 if (level) {
890 s->irr |= mask;
891 ioapic_service(s);
892 } else {
893 s->irr &= ~mask;
894 }
895 } else {
896 /* edge triggered */
897 if (level) {
898 s->irr |= mask;
899 ioapic_service(s);
900 }
901 }
902 }
903 }
905 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
906 {
907 IOAPICState *s = opaque;
908 int index;
909 uint32_t val = 0;
911 addr &= 0xff;
912 if (addr == 0x00) {
913 val = s->ioregsel;
914 } else if (addr == 0x10) {
915 switch (s->ioregsel) {
916 case 0x00:
917 val = s->id << 24;
918 break;
919 case 0x01:
920 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
921 break;
922 case 0x02:
923 val = 0;
924 break;
925 default:
926 index = (s->ioregsel - 0x10) >> 1;
927 if (index >= 0 && index < IOAPIC_NUM_PINS) {
928 if (s->ioregsel & 1)
929 val = s->ioredtbl[index] >> 32;
930 else
931 val = s->ioredtbl[index] & 0xffffffff;
932 }
933 }
934 #ifdef DEBUG_IOAPIC
935 printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
936 #endif
937 }
938 return val;
939 }
941 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 {
943 IOAPICState *s = opaque;
944 int index;
946 addr &= 0xff;
947 if (addr == 0x00) {
948 s->ioregsel = val;
949 return;
950 } else if (addr == 0x10) {
951 #ifdef DEBUG_IOAPIC
952 printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
953 #endif
954 switch (s->ioregsel) {
955 case 0x00:
956 s->id = (val >> 24) & 0xff;
957 return;
958 case 0x01:
959 case 0x02:
960 return;
961 default:
962 index = (s->ioregsel - 0x10) >> 1;
963 if (index >= 0 && index < IOAPIC_NUM_PINS) {
964 if (s->ioregsel & 1) {
965 s->ioredtbl[index] &= 0xffffffff;
966 s->ioredtbl[index] |= (uint64_t)val << 32;
967 } else {
968 s->ioredtbl[index] &= ~0xffffffffULL;
969 s->ioredtbl[index] |= val;
970 }
971 ioapic_service(s);
972 }
973 }
974 }
975 }
977 static void ioapic_save(QEMUFile *f, void *opaque)
978 {
979 IOAPICState *s = opaque;
980 int i;
982 qemu_put_8s(f, &s->id);
983 qemu_put_8s(f, &s->ioregsel);
984 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
985 qemu_put_be64s(f, &s->ioredtbl[i]);
986 }
987 }
989 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
990 {
991 IOAPICState *s = opaque;
992 int i;
994 if (version_id != 1)
995 return -EINVAL;
997 qemu_get_8s(f, &s->id);
998 qemu_get_8s(f, &s->ioregsel);
999 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1000 qemu_get_be64s(f, &s->ioredtbl[i]);
1002 return 0;
1005 static void ioapic_reset(void *opaque)
1007 IOAPICState *s = opaque;
1008 int i;
1010 memset(s, 0, sizeof(*s));
1011 for(i = 0; i < IOAPIC_NUM_PINS; i++)
1012 s->ioredtbl[i] = 1 << 16; /* mask LVT */
1015 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1016 ioapic_mem_readl,
1017 ioapic_mem_readl,
1018 ioapic_mem_readl,
1019 };
1021 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1022 ioapic_mem_writel,
1023 ioapic_mem_writel,
1024 ioapic_mem_writel,
1025 };
1027 IOAPICState *ioapic_init(void)
1029 IOAPICState *s;
1030 int io_memory;
1032 s = qemu_mallocz(sizeof(IOAPICState));
1033 if (!s)
1034 return NULL;
1035 ioapic_reset(s);
1036 s->id = last_apic_id++;
1038 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1039 ioapic_mem_write, s);
1040 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1042 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1043 qemu_register_reset(ioapic_reset, s);
1045 return s;