debuggers.hg

view tools/ioemu/hw/iommu.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
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1 /*
2 * QEMU SPARC iommu emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 /* debug iommu */
27 //#define DEBUG_IOMMU
29 #ifdef DEBUG_IOMMU
30 #define DPRINTF(fmt, args...) \
31 do { printf("IOMMU: " fmt , ##args); } while (0)
32 #else
33 #define DPRINTF(fmt, args...)
34 #endif
36 #define IOMMU_NREGS (3*4096/4)
37 #define IOMMU_CTRL (0x0000 >> 2)
38 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
39 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
40 #define IOMMU_VERSION 0x04000000
41 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
42 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
43 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
44 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
45 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
46 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
47 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
48 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
49 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
50 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
51 #define IOMMU_CTRL_MASK 0x0000001d
53 #define IOMMU_BASE (0x0004 >> 2)
54 #define IOMMU_BASE_MASK 0x07fffc00
56 #define IOMMU_TLBFLUSH (0x0014 >> 2)
57 #define IOMMU_TLBFLUSH_MASK 0xffffffff
59 #define IOMMU_PGFLUSH (0x0018 >> 2)
60 #define IOMMU_PGFLUSH_MASK 0xffffffff
62 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
63 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
64 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
65 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
66 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
67 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
68 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
69 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
70 produced by this device as pure
71 physical. */
72 #define IOMMU_SBCFG_MASK 0x00010003
74 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
75 #define IOMMU_ARBEN_MASK 0x001f0000
76 #define IOMMU_MID 0x00000008
78 /* The format of an iopte in the page tables */
79 #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
80 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
81 #define IOPTE_WRITE 0x00000004 /* Writeable */
82 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
83 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
85 #if defined(__i386__) || defined(__x86_64__)
86 #define PAGE_SHIFT 12
87 #elif defined(__ia64__)
88 #define PAGE_SHIFT 14
89 #endif
90 #define PAGE_SIZE (1 << PAGE_SHIFT)
91 #define PAGE_MASK (PAGE_SIZE - 1)
93 typedef struct IOMMUState {
94 uint32_t addr;
95 uint32_t regs[IOMMU_NREGS];
96 uint32_t iostart;
97 } IOMMUState;
99 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
100 {
101 IOMMUState *s = opaque;
102 uint32_t saddr;
104 saddr = (addr - s->addr) >> 2;
105 switch (saddr) {
106 default:
107 DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
108 return s->regs[saddr];
109 break;
110 }
111 return 0;
112 }
114 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
115 {
116 IOMMUState *s = opaque;
117 uint32_t saddr;
119 saddr = (addr - s->addr) >> 2;
120 DPRINTF("write reg[%d] = %x\n", saddr, val);
121 switch (saddr) {
122 case IOMMU_CTRL:
123 switch (val & IOMMU_CTRL_RNGE) {
124 case IOMMU_RNGE_16MB:
125 s->iostart = 0xff000000;
126 break;
127 case IOMMU_RNGE_32MB:
128 s->iostart = 0xfe000000;
129 break;
130 case IOMMU_RNGE_64MB:
131 s->iostart = 0xfc000000;
132 break;
133 case IOMMU_RNGE_128MB:
134 s->iostart = 0xf8000000;
135 break;
136 case IOMMU_RNGE_256MB:
137 s->iostart = 0xf0000000;
138 break;
139 case IOMMU_RNGE_512MB:
140 s->iostart = 0xe0000000;
141 break;
142 case IOMMU_RNGE_1GB:
143 s->iostart = 0xc0000000;
144 break;
145 default:
146 case IOMMU_RNGE_2GB:
147 s->iostart = 0x80000000;
148 break;
149 }
150 DPRINTF("iostart = %x\n", s->iostart);
151 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
152 break;
153 case IOMMU_BASE:
154 s->regs[saddr] = val & IOMMU_BASE_MASK;
155 break;
156 case IOMMU_TLBFLUSH:
157 DPRINTF("tlb flush %x\n", val);
158 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
159 break;
160 case IOMMU_PGFLUSH:
161 DPRINTF("page flush %x\n", val);
162 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
163 break;
164 case IOMMU_SBCFG0:
165 case IOMMU_SBCFG1:
166 case IOMMU_SBCFG2:
167 case IOMMU_SBCFG3:
168 s->regs[saddr] = val & IOMMU_SBCFG_MASK;
169 break;
170 case IOMMU_ARBEN:
171 // XXX implement SBus probing: fault when reading unmapped
172 // addresses, fault cause and address stored to MMU/IOMMU
173 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
174 break;
175 default:
176 s->regs[saddr] = val;
177 break;
178 }
179 }
181 static CPUReadMemoryFunc *iommu_mem_read[3] = {
182 iommu_mem_readw,
183 iommu_mem_readw,
184 iommu_mem_readw,
185 };
187 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
188 iommu_mem_writew,
189 iommu_mem_writew,
190 iommu_mem_writew,
191 };
193 static uint32_t iommu_page_get_flags(IOMMUState *s, uint32_t addr)
194 {
195 uint32_t iopte;
197 iopte = s->regs[1] << 4;
198 addr &= ~s->iostart;
199 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
200 return ldl_phys(iopte);
201 }
203 static uint32_t iommu_translate_pa(IOMMUState *s, uint32_t addr, uint32_t pa)
204 {
205 uint32_t tmppte;
207 tmppte = pa;
208 pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
209 DPRINTF("xlate dva %x => pa %x (iopte = %x)\n", addr, pa, tmppte);
210 return pa;
211 }
213 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
214 uint8_t *buf, int len, int is_write)
215 {
216 int l, flags;
217 target_ulong page, phys_addr;
219 while (len > 0) {
220 page = addr & TARGET_PAGE_MASK;
221 l = (page + TARGET_PAGE_SIZE) - addr;
222 if (l > len)
223 l = len;
224 flags = iommu_page_get_flags(opaque, page);
225 if (!(flags & IOPTE_VALID))
226 return;
227 phys_addr = iommu_translate_pa(opaque, addr, flags);
228 if (is_write) {
229 if (!(flags & IOPTE_WRITE))
230 return;
231 cpu_physical_memory_write(phys_addr, buf, len);
232 } else {
233 cpu_physical_memory_read(phys_addr, buf, len);
234 }
235 len -= l;
236 buf += l;
237 addr += l;
238 }
239 }
241 static void iommu_save(QEMUFile *f, void *opaque)
242 {
243 IOMMUState *s = opaque;
244 int i;
246 qemu_put_be32s(f, &s->addr);
247 for (i = 0; i < IOMMU_NREGS; i++)
248 qemu_put_be32s(f, &s->regs[i]);
249 qemu_put_be32s(f, &s->iostart);
250 }
252 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
253 {
254 IOMMUState *s = opaque;
255 int i;
257 if (version_id != 1)
258 return -EINVAL;
260 qemu_get_be32s(f, &s->addr);
261 for (i = 0; i < IOMMU_NREGS; i++)
262 qemu_put_be32s(f, &s->regs[i]);
263 qemu_get_be32s(f, &s->iostart);
265 return 0;
266 }
268 static void iommu_reset(void *opaque)
269 {
270 IOMMUState *s = opaque;
272 memset(s->regs, 0, IOMMU_NREGS * 4);
273 s->iostart = 0;
274 s->regs[0] = IOMMU_VERSION;
275 }
277 void *iommu_init(uint32_t addr)
278 {
279 IOMMUState *s;
280 int iommu_io_memory;
282 s = qemu_mallocz(sizeof(IOMMUState));
283 if (!s)
284 return NULL;
286 s->addr = addr;
288 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
289 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
291 register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
292 qemu_register_reset(iommu_reset, s);
293 return s;
294 }