debuggers.hg

view tools/ioemu/hw/pci.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 5c0bf00e371d
line source
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 //#define DEBUG_PCI
28 struct PCIBus {
29 int bus_num;
30 int devfn_min;
31 pci_set_irq_fn set_irq;
32 pci_map_irq_fn map_irq;
33 uint32_t config_reg; /* XXX: suppress */
34 /* low level pic */
35 SetIRQFunc *low_set_irq;
36 void *irq_opaque;
37 PCIDevice *devices[256];
38 PCIDevice *parent_dev;
39 PCIBus *next;
40 /* The bus IRQ state is the logical OR of the connected devices.
41 Keep a count of the number of devices with raised IRQs. */
42 int irq_count[];
43 };
45 static void pci_update_mappings(PCIDevice *d);
47 target_phys_addr_t pci_mem_base;
48 static int pci_irq_index;
49 static PCIBus *first_bus;
51 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
52 void *pic, int devfn_min, int nirq)
53 {
54 PCIBus *bus;
55 bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
56 bus->set_irq = set_irq;
57 bus->map_irq = map_irq;
58 bus->irq_opaque = pic;
59 bus->devfn_min = devfn_min;
60 first_bus = bus;
61 return bus;
62 }
64 PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
65 {
66 PCIBus *bus;
67 bus = qemu_mallocz(sizeof(PCIBus));
68 bus->map_irq = map_irq;
69 bus->parent_dev = dev;
70 bus->next = dev->bus->next;
71 dev->bus->next = bus;
72 return bus;
73 }
75 int pci_bus_num(PCIBus *s)
76 {
77 return s->bus_num;
78 }
80 void pci_device_save(PCIDevice *s, QEMUFile *f)
81 {
82 uint8_t irq_state = 0;
83 int i;
84 qemu_put_be32(f, 2); /* PCI device version */
85 qemu_put_buffer(f, s->config, 256);
86 for (i = 0; i < 4; i++)
87 irq_state |= !!s->irq_state[i] << i;
88 qemu_put_buffer(f, &irq_state, 1);
89 }
91 int pci_device_load(PCIDevice *s, QEMUFile *f)
92 {
93 uint32_t version_id;
94 version_id = qemu_get_be32(f);
95 if (version_id != 1 && version_id != 2)
96 return -EINVAL;
97 qemu_get_buffer(f, s->config, 256);
98 pci_update_mappings(s);
99 if (version_id == 2) {
100 uint8_t irq_state;
101 int i;
102 qemu_get_buffer(f, &irq_state, 1);
103 for (i = 0; i < 4; i++)
104 pci_set_irq(s, i, (irq_state >> i) & 1);
105 }
106 return 0;
107 }
109 /* -1 for devfn means auto assign */
110 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
111 int instance_size, int devfn,
112 PCIConfigReadFunc *config_read,
113 PCIConfigWriteFunc *config_write)
114 {
115 PCIDevice *pci_dev;
117 if (pci_irq_index >= PCI_DEVICES_MAX)
118 return NULL;
120 if (devfn < 0) {
121 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
122 if ( !bus->devices[devfn] &&
123 !( devfn >= PHP_DEVFN_START && devfn < PHP_DEVFN_END ) )
124 goto found;
125 }
126 return NULL;
127 found: ;
128 }
129 pci_dev = qemu_mallocz(instance_size);
130 if (!pci_dev)
131 return NULL;
132 pci_dev->bus = bus;
133 pci_dev->devfn = devfn;
134 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
135 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
137 if (!config_read)
138 config_read = pci_default_read_config;
139 if (!config_write)
140 config_write = pci_default_write_config;
141 pci_dev->config_read = config_read;
142 pci_dev->config_write = config_write;
143 pci_dev->irq_index = pci_irq_index++;
144 bus->devices[devfn] = pci_dev;
145 return pci_dev;
146 }
148 void pci_hide_device(PCIDevice *pci_dev)
149 {
150 PCIBus *bus = pci_dev->bus;
151 bus->devices[pci_dev->devfn] = NULL;
152 }
154 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
155 uint32_t size, int type,
156 PCIMapIORegionFunc *map_func)
157 {
158 PCIIORegion *r;
159 uint32_t addr;
161 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
162 return;
163 r = &pci_dev->io_regions[region_num];
164 r->addr = -1;
165 r->size = size;
166 r->type = type;
167 r->map_func = map_func;
168 if (region_num == PCI_ROM_SLOT) {
169 addr = 0x30;
170 } else {
171 addr = 0x10 + region_num * 4;
172 }
173 *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
174 }
176 target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
177 {
178 return addr + pci_mem_base;
179 }
181 static void pci_update_mappings(PCIDevice *d)
182 {
183 PCIIORegion *r;
184 int cmd, i;
185 uint32_t last_addr, new_addr, config_ofs;
187 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
188 for(i = 0; i < PCI_NUM_REGIONS; i++) {
189 r = &d->io_regions[i];
190 if (i == PCI_ROM_SLOT) {
191 config_ofs = 0x30;
192 } else {
193 config_ofs = 0x10 + i * 4;
194 }
195 if (r->size != 0) {
196 if (r->type & PCI_ADDRESS_SPACE_IO) {
197 if (cmd & PCI_COMMAND_IO) {
198 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
199 config_ofs));
200 new_addr = new_addr & ~(r->size - 1);
201 last_addr = new_addr + r->size - 1;
202 /* NOTE: we have only 64K ioports on PC */
203 if (last_addr <= new_addr || new_addr == 0 ||
204 last_addr >= 0x10000) {
205 new_addr = -1;
206 }
207 } else {
208 new_addr = -1;
209 }
210 } else {
211 if (cmd & PCI_COMMAND_MEMORY) {
212 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
213 config_ofs));
214 /* the ROM slot has a specific enable bit */
215 if (i == PCI_ROM_SLOT && !(new_addr & 1))
216 goto no_mem_map;
217 new_addr = new_addr & ~(r->size - 1);
218 last_addr = new_addr + r->size - 1;
219 /* NOTE: we do not support wrapping */
220 /* XXX: as we cannot support really dynamic
221 mappings, we handle specific values as invalid
222 mappings. */
223 if (last_addr <= new_addr || new_addr == 0 ||
224 last_addr == -1) {
225 new_addr = -1;
226 }
227 } else {
228 no_mem_map:
229 new_addr = -1;
230 }
231 }
232 /* now do the real mapping */
233 if (new_addr != r->addr) {
234 if (r->addr != -1) {
235 if (r->type & PCI_ADDRESS_SPACE_IO) {
236 int class;
237 /* NOTE: specific hack for IDE in PC case:
238 only one byte must be mapped. */
239 class = d->config[0x0a] | (d->config[0x0b] << 8);
240 if (class == 0x0101 && r->size == 4) {
241 isa_unassign_ioport(r->addr + 2, 1);
242 } else {
243 isa_unassign_ioport(r->addr, r->size);
244 }
245 } else {
246 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
247 r->size,
248 IO_MEM_UNASSIGNED);
249 }
250 }
251 r->addr = new_addr;
252 if (r->addr != -1) {
253 r->map_func(d, i, r->addr, r->size, r->type);
254 }
255 }
256 }
257 }
258 }
260 uint32_t pci_default_read_config(PCIDevice *d,
261 uint32_t address, int len)
262 {
263 uint32_t val;
265 switch(len) {
266 default:
267 case 4:
268 if (address <= 0xfc) {
269 val = le32_to_cpu(*(uint32_t *)(d->config + address));
270 break;
271 }
272 /* fall through */
273 case 2:
274 if (address <= 0xfe) {
275 val = le16_to_cpu(*(uint16_t *)(d->config + address));
276 break;
277 }
278 /* fall through */
279 case 1:
280 val = d->config[address];
281 break;
282 }
283 return val;
284 }
286 void pci_default_write_config(PCIDevice *d,
287 uint32_t address, uint32_t val, int len)
288 {
289 int can_write, i;
290 uint32_t end, addr;
292 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
293 (address >= 0x30 && address < 0x34))) {
294 PCIIORegion *r;
295 int reg;
297 if ( address >= 0x30 ) {
298 reg = PCI_ROM_SLOT;
299 }else{
300 reg = (address - 0x10) >> 2;
301 }
302 r = &d->io_regions[reg];
303 if (r->size == 0)
304 goto default_config;
305 /* compute the stored value */
306 if (reg == PCI_ROM_SLOT) {
307 /* keep ROM enable bit */
308 val &= (~(r->size - 1)) | 1;
309 } else {
310 val &= ~(r->size - 1);
311 val |= r->type;
312 }
313 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
314 pci_update_mappings(d);
315 return;
316 }
317 default_config:
318 /* not efficient, but simple */
319 addr = address;
320 for(i = 0; i < len; i++) {
321 /* default read/write accesses */
322 switch(d->config[0x0e]) {
323 case 0x00:
324 case 0x80:
325 switch(addr) {
326 case 0x00:
327 case 0x01:
328 case 0x02:
329 case 0x03:
330 case 0x08:
331 case 0x09:
332 case 0x0a:
333 case 0x0b:
334 case 0x0e:
335 case 0x10 ... 0x27: /* base */
336 case 0x2c ... 0x2f: /* subsystem vendor id, subsystem id */
337 case 0x30 ... 0x33: /* rom */
338 case 0x3d:
339 can_write = 0;
340 break;
341 default:
342 can_write = 1;
343 break;
344 }
345 break;
346 default:
347 case 0x01:
348 switch(addr) {
349 case 0x00:
350 case 0x01:
351 case 0x02:
352 case 0x03:
353 case 0x08:
354 case 0x09:
355 case 0x0a:
356 case 0x0b:
357 case 0x0e:
358 case 0x38 ... 0x3b: /* rom */
359 case 0x3d:
360 can_write = 0;
361 break;
362 default:
363 can_write = 1;
364 break;
365 }
366 break;
367 }
368 if (can_write) {
369 if( addr == 0x05 ) {
370 /* In Command Register, bits 15:11 are reserved */
371 val &= 0x07;
372 } else if ( addr == 0x06 ) {
373 /* In Status Register, bits 6, 2:0 are reserved, */
374 /* and bits 7,5,4,3 are read only */
375 val = d->config[addr];
376 } else if ( addr == 0x07 ) {
377 /* In Status Register, bits 10,9 are reserved, */
378 val = (val & ~0x06) | (d->config[addr] & 0x06);
379 }
381 d->config[addr] = val;
382 }
383 if (++addr > 0xff)
384 break;
385 val >>= 8;
386 }
388 end = address + len;
389 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
390 /* if the command register is modified, we must modify the mappings */
391 pci_update_mappings(d);
392 }
393 }
395 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
396 {
397 PCIBus *s = opaque;
398 PCIDevice *pci_dev;
399 int config_addr, bus_num;
401 #if defined(DEBUG_PCI) && 0
402 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
403 addr, val, len);
404 #endif
405 bus_num = (addr >> 16) & 0xff;
406 while (s && s->bus_num != bus_num)
407 s = s->next;
408 if (!s)
409 return;
410 pci_dev = s->devices[(addr >> 8) & 0xff];
411 if (!pci_dev)
412 return;
413 config_addr = addr & 0xff;
414 #if defined(DEBUG_PCI)
415 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
416 pci_dev->name, config_addr, val, len);
417 #endif
418 pci_dev->config_write(pci_dev, config_addr, val, len);
419 }
421 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
422 {
423 PCIBus *s = opaque;
424 PCIDevice *pci_dev;
425 int config_addr, bus_num;
426 uint32_t val;
428 bus_num = (addr >> 16) & 0xff;
429 while (s && s->bus_num != bus_num)
430 s= s->next;
431 if (!s)
432 goto fail;
433 pci_dev = s->devices[(addr >> 8) & 0xff];
434 if (!pci_dev) {
435 fail:
436 switch(len) {
437 case 1:
438 val = 0xff;
439 break;
440 case 2:
441 val = 0xffff;
442 break;
443 default:
444 case 4:
445 val = 0xffffffff;
446 break;
447 }
448 goto the_end;
449 }
450 config_addr = addr & 0xff;
451 val = pci_dev->config_read(pci_dev, config_addr, len);
452 #if defined(DEBUG_PCI)
453 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
454 pci_dev->name, config_addr, val, len);
455 #endif
456 the_end:
457 #if defined(DEBUG_PCI) && 0
458 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
459 addr, val, len);
460 #endif
461 return val;
462 }
464 /***********************************************************/
465 /* generic PCI irq support */
467 /* 0 <= irq_num <= 3. level must be 0 or 1 */
468 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
469 {
470 PCIBus *bus;
471 int change;
473 change = level - pci_dev->irq_state[irq_num];
474 if (!change)
475 return;
477 pci_dev->irq_state[irq_num] = level;
478 for (;;) {
479 bus = pci_dev->bus;
480 irq_num = bus->map_irq(pci_dev, irq_num);
481 if (bus->set_irq)
482 break;
483 pci_dev = bus->parent_dev;
484 }
485 bus->irq_count[irq_num] += change;
486 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
487 }
489 /***********************************************************/
490 /* monitor info on PCI */
492 typedef struct {
493 uint16_t class;
494 const char *desc;
495 } pci_class_desc;
497 static pci_class_desc pci_class_descriptions[] =
498 {
499 { 0x0100, "SCSI controller"},
500 { 0x0101, "IDE controller"},
501 { 0x0200, "Ethernet controller"},
502 { 0x0300, "VGA controller"},
503 { 0x0600, "Host bridge"},
504 { 0x0601, "ISA bridge"},
505 { 0x0604, "PCI bridge"},
506 { 0x0c03, "USB controller"},
507 { 0, NULL}
508 };
510 static void pci_info_device(PCIDevice *d)
511 {
512 int i, class;
513 PCIIORegion *r;
514 pci_class_desc *desc;
516 term_printf(" Bus %2d, device %3d, function %d:\n",
517 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
518 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
519 term_printf(" ");
520 desc = pci_class_descriptions;
521 while (desc->desc && class != desc->class)
522 desc++;
523 if (desc->desc) {
524 term_printf("%s", desc->desc);
525 } else {
526 term_printf("Class %04x", class);
527 }
528 term_printf(": PCI device %04x:%04x\n",
529 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
530 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
532 if (d->config[PCI_INTERRUPT_PIN] != 0) {
533 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
534 }
535 if (class == 0x0604) {
536 term_printf(" BUS %d.\n", d->config[0x19]);
537 }
538 for(i = 0;i < PCI_NUM_REGIONS; i++) {
539 r = &d->io_regions[i];
540 if (r->size != 0) {
541 term_printf(" BAR%d: ", i);
542 if (r->type & PCI_ADDRESS_SPACE_IO) {
543 term_printf("I/O at 0x%04x [0x%04x].\n",
544 r->addr, r->addr + r->size - 1);
545 } else {
546 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
547 r->addr, r->addr + r->size - 1);
548 }
549 }
550 }
551 if (class == 0x0604 && d->config[0x19] != 0) {
552 pci_for_each_device(d->config[0x19], pci_info_device);
553 }
554 }
556 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
557 {
558 PCIBus *bus = first_bus;
559 PCIDevice *d;
560 int devfn;
562 while (bus && bus->bus_num != bus_num)
563 bus = bus->next;
564 if (bus) {
565 for(devfn = 0; devfn < 256; devfn++) {
566 d = bus->devices[devfn];
567 if (d)
568 fn(d);
569 }
570 }
571 }
573 void pci_info(void)
574 {
575 pci_for_each_device(0, pci_info_device);
576 }
578 /* Initialize a PCI NIC. */
579 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn)
580 {
581 if (strcmp(nd->model, "ne2k_pci") == 0) {
582 pci_ne2000_init(bus, nd, devfn);
583 } else if (strcmp(nd->model, "rtl8139") == 0) {
584 pci_rtl8139_init(bus, nd, devfn);
585 } else if (strcmp(nd->model, "pcnet") == 0) {
586 pci_pcnet_init(bus, nd, devfn);
587 } else if (strcmp(nd->model, "e100") == 0) {
588 pci_e100_init(bus, nd);
589 } else if (strcmp(nd->model, "e1000") == 0) {
590 pci_e1000_init(bus, nd, devfn);
591 } else {
592 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
593 exit (1);
594 }
595 }
597 typedef struct {
598 PCIDevice dev;
599 PCIBus *bus;
600 } PCIBridge;
602 void pci_bridge_write_config(PCIDevice *d,
603 uint32_t address, uint32_t val, int len)
604 {
605 PCIBridge *s = (PCIBridge *)d;
607 if (address == 0x19 || (address == 0x18 && len > 1)) {
608 if (address == 0x19)
609 s->bus->bus_num = val & 0xff;
610 else
611 s->bus->bus_num = (val >> 8) & 0xff;
612 #if defined(DEBUG_PCI)
613 printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
614 #endif
615 }
616 pci_default_write_config(d, address, val, len);
617 }
619 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
620 pci_map_irq_fn map_irq, const char *name)
621 {
622 PCIBridge *s;
623 s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
624 devfn, NULL, pci_bridge_write_config);
625 s->dev.config[0x00] = id >> 16;
626 s->dev.config[0x01] = id > 24;
627 s->dev.config[0x02] = id; // device_id
628 s->dev.config[0x03] = id >> 8;
629 s->dev.config[0x04] = 0x06; // command = bus master, pci mem
630 s->dev.config[0x05] = 0x00;
631 s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
632 s->dev.config[0x07] = 0x00; // status = fast devsel
633 s->dev.config[0x08] = 0x00; // revision
634 s->dev.config[0x09] = 0x00; // programming i/f
635 s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
636 s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
637 s->dev.config[0x0D] = 0x10; // latency_timer
638 s->dev.config[0x0E] = 0x81; // header_type
639 s->dev.config[0x1E] = 0xa0; // secondary status
641 s->bus = pci_register_secondary_bus(&s->dev, map_irq);
642 return s->bus;
643 }