debuggers.hg

view tools/ioemu/hw/serial.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 5c0bf00e371d
line source
1 /*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "vl.h"
26 #include <sys/time.h>
27 #include <time.h>
28 #include <assert.h>
29 #include <termios.h>
30 #include <sys/ioctl.h>
32 //#define DEBUG_SERIAL
34 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
36 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
37 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
38 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
39 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
41 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
42 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
44 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
45 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
46 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
47 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
48 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
50 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
51 #define UART_IIR_FE 0xC0 /* Fifo enabled */
53 /*
54 * These are the definitions for the Modem Control Register
55 */
56 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
57 #define UART_MCR_OUT2 0x08 /* Out2 complement */
58 #define UART_MCR_OUT1 0x04 /* Out1 complement */
59 #define UART_MCR_RTS 0x02 /* RTS complement */
60 #define UART_MCR_DTR 0x01 /* DTR complement */
62 /*
63 * These are the definitions for the Modem Status Register
64 */
65 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
66 #define UART_MSR_RI 0x40 /* Ring Indicator */
67 #define UART_MSR_DSR 0x20 /* Data Set Ready */
68 #define UART_MSR_CTS 0x10 /* Clear to Send */
69 #define UART_MSR_DDCD 0x08 /* Delta DCD */
70 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
71 #define UART_MSR_DDSR 0x02 /* Delta DSR */
72 #define UART_MSR_DCTS 0x01 /* Delta CTS */
73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the msr delta bits */
75 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
76 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
77 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
78 #define UART_LSR_FE 0x08 /* Frame error indicator */
79 #define UART_LSR_PE 0x04 /* Parity error indicator */
80 #define UART_LSR_OE 0x02 /* Overrun error indicator */
81 #define UART_LSR_DR 0x01 /* Receiver data ready */
82 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
86 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
87 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
88 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
89 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
91 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
92 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
93 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
94 #define UART_FCR_FE 0x01 /* FIFO Enable */
96 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
98 #define XMIT_FIFO 0
99 #define RECV_FIFO 1
100 #define MAX_XMIT_RETRY 4
102 struct SerialFIFO {
103 uint8_t data[UART_FIFO_LENGTH];
104 uint8_t count;
105 uint8_t itl; /* Interrupt Trigger Level */
106 uint8_t tail;
107 uint8_t head;
108 } typedef SerialFIFO;
110 struct SerialState {
111 uint16_t divider;
112 uint8_t rbr; /* receive register */
113 uint8_t thr; /* transmit holding register */
114 uint8_t tsr; /* transmit shift register */
115 uint8_t ier;
116 uint8_t iir; /* read only */
117 uint8_t lcr;
118 uint8_t mcr;
119 uint8_t lsr; /* read only */
120 uint8_t msr; /* read only */
121 uint8_t scr;
122 uint8_t fcr;
123 /* NOTE: this hidden state is necessary for tx irq generation as
124 it can be reset while reading iir */
125 int thr_ipending;
126 SetIRQFunc *set_irq;
127 void *irq_opaque;
128 int irq;
129 CharDriverState *chr;
130 int last_break_enable;
131 target_ulong base;
132 int it_shift;
133 int tsr_retry;
135 uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
136 SerialFIFO recv_fifo;
137 SerialFIFO xmit_fifo;
139 struct QEMUTimer *fifo_timeout_timer;
140 int timeout_ipending; /* timeout interrupt pending state */
141 struct QEMUTimer *transmit_timer;
144 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
145 int poll_msl;
147 struct QEMUTimer *modem_status_poll;
148 };
150 /* Rate limit serial requests so that e.g. grub on a serial console
151 doesn't kill dom0. Simple token bucket. If we get some actual
152 data from the user, instantly refil the bucket. */
154 /* How long it takes to generate a token, in microseconds. */
155 #define TOKEN_PERIOD 1000
156 /* Maximum and initial size of token bucket */
157 #define TOKENS_MAX 100000
159 static int tokens_avail;
161 static void fifo_clear(SerialState *s, int fifo) {
162 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
163 memset(f->data, 0, UART_FIFO_LENGTH);
164 f->count = 0;
165 f->head = 0;
166 f->tail = 0;
167 }
169 static int fifo_put(SerialState *s, int fifo, uint8_t chr) {
170 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
172 f->data[f->head++] = chr;
174 if (f->head == UART_FIFO_LENGTH)
175 f->head = 0;
176 f->count++;
178 tokens_avail = TOKENS_MAX;
180 return 1;
181 }
183 uint8_t fifo_get(SerialState *s, int fifo) {
184 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
185 uint8_t c;
187 if( f->count == 0 )
188 return 0;
190 c = f->data[f->tail++];
191 if (f->tail == UART_FIFO_LENGTH)
192 f->tail = 0;
193 f->count--;
195 tokens_avail = TOKENS_MAX;
197 return c;
198 }
200 static void serial_update_irq(SerialState *s)
201 {
202 uint8_t tmp_iir = UART_IIR_NO_INT;
204 if (!s->ier) {
205 s->set_irq(s->irq_opaque, s->irq, 0);
206 return;
207 }
209 if ( ( s->ier & UART_IER_RLSI ) && (s->lsr & UART_LSR_INT_ANY ) ) {
210 tmp_iir = UART_IIR_RLSI;
211 } else if ( s->timeout_ipending ) {
212 tmp_iir = UART_IIR_CTI;
213 } else if ( ( s->ier & UART_IER_RDI ) && (s->lsr & UART_LSR_DR ) ) {
214 if ( !(s->iir & UART_FCR_FE) ) {
215 tmp_iir = UART_IIR_RDI;
216 } else if ( s->recv_fifo.count >= s->recv_fifo.itl ) {
217 tmp_iir = UART_IIR_RDI;
218 }
219 } else if ( (s->ier & UART_IER_THRI) && s->thr_ipending ) {
220 tmp_iir = UART_IIR_THRI;
221 } else if ( (s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA) ) {
222 tmp_iir = UART_IIR_MSI;
223 }
225 s->iir = tmp_iir | ( s->iir & 0xF0 );
227 if ( tmp_iir != UART_IIR_NO_INT ) {
228 s->set_irq(s->irq_opaque, s->irq, 1);
229 } else {
230 s->set_irq(s->irq_opaque, s->irq, 0);
231 }
232 }
234 static void serial_update_parameters(SerialState *s)
235 {
236 int speed, parity, data_bits, stop_bits, frame_size;
237 QEMUSerialSetParams ssp;
239 if (s->divider == 0)
240 return;
242 frame_size = 1;
243 if (s->lcr & 0x08) {
244 if (s->lcr & 0x10)
245 parity = 'E';
246 else
247 parity = 'O';
248 } else {
249 parity = 'N';
250 frame_size = 0;
251 }
252 if (s->lcr & 0x04)
253 stop_bits = 2;
254 else
255 stop_bits = 1;
257 data_bits = (s->lcr & 0x03) + 5;
258 frame_size += data_bits + stop_bits;
260 speed = 115200 / s->divider;
261 ssp.speed = speed;
262 ssp.parity = parity;
263 ssp.data_bits = data_bits;
264 ssp.stop_bits = stop_bits;
265 s->char_transmit_time = ( ticks_per_sec / speed ) * frame_size;
266 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
267 #if 0
268 printf("speed=%d parity=%c data=%d stop=%d\n",
269 speed, parity, data_bits, stop_bits);
270 #endif
271 }
273 static void serial_get_token(void)
274 {
275 static struct timeval last_refil_time;
276 static int started;
278 assert(tokens_avail >= 0);
279 if (!tokens_avail) {
280 struct timeval delta, now;
281 int generated;
283 if (!started) {
284 gettimeofday(&last_refil_time, NULL);
285 tokens_avail = TOKENS_MAX;
286 started = 1;
287 return;
288 }
289 retry:
290 gettimeofday(&now, NULL);
291 delta.tv_sec = now.tv_sec - last_refil_time.tv_sec;
292 delta.tv_usec = now.tv_usec - last_refil_time.tv_usec;
293 if (delta.tv_usec < 0) {
294 delta.tv_usec += 1000000;
295 delta.tv_sec--;
296 }
297 assert(delta.tv_usec >= 0 && delta.tv_sec >= 0);
298 if (delta.tv_usec < TOKEN_PERIOD) {
299 struct timespec ts;
300 /* Wait until at least one token is available. */
301 ts.tv_sec = TOKEN_PERIOD / 1000000;
302 ts.tv_nsec = (TOKEN_PERIOD % 1000000) * 1000;
303 while (nanosleep(&ts, &ts) < 0 && errno == EINTR)
304 ;
305 goto retry;
306 }
307 generated = (delta.tv_sec * 1000000) / TOKEN_PERIOD;
308 generated +=
309 ((delta.tv_sec * 1000000) % TOKEN_PERIOD + delta.tv_usec) / TOKEN_PERIOD;
310 assert(generated > 0);
312 last_refil_time.tv_usec += (generated * TOKEN_PERIOD) % 1000000;
313 last_refil_time.tv_sec += last_refil_time.tv_usec / 1000000;
314 last_refil_time.tv_usec %= 1000000;
315 last_refil_time.tv_sec += (generated * TOKEN_PERIOD) / 1000000;
316 if (generated > TOKENS_MAX)
317 generated = TOKENS_MAX;
318 tokens_avail = generated;
319 }
320 tokens_avail--;
321 }
323 static void serial_update_msl( SerialState *s )
324 {
325 uint8_t omsr;
326 int flags;
328 qemu_del_timer(s->modem_status_poll);
330 if ( qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP ) {
331 s->poll_msl = -1;
332 return;
333 }
335 omsr = s->msr;
337 s->msr = ( flags & TIOCM_CTS ) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
338 s->msr = ( flags & TIOCM_DSR ) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
339 s->msr = ( flags & TIOCM_CAR ) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
340 s->msr = ( flags & TIOCM_RI ) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
342 if ( s->msr != omsr ) {
343 /* Set delta bits */
344 s->msr = s->msr | ( ( s->msr >> 4 ) ^ ( omsr >> 4 ) );
345 /* UART_MSR_TERI only if change was from 1 -> 0 */
346 if ( ( s->msr & UART_MSR_TERI ) && !( omsr & UART_MSR_RI ) )
347 s->msr &= ~UART_MSR_TERI;
348 serial_update_irq(s);
349 }
351 /* The real 16550A apparently has a 250ns response latency to line status changes.
352 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
354 if ( s->poll_msl )
355 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
356 }
358 static void serial_xmit(void *opaque) {
359 SerialState *s = opaque;
360 uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
362 if ( s->tsr_retry <= 0 ) {
363 if (s->fcr & UART_FCR_FE) {
364 s->tsr = fifo_get(s,XMIT_FIFO);
365 if ( !s->xmit_fifo.count )
366 s->lsr |= UART_LSR_THRE;
367 } else {
368 s->tsr = s->thr;
369 s->lsr |= UART_LSR_THRE;
370 }
371 }
373 if ( qemu_chr_write(s->chr, &s->tsr, 1) != 1 ) {
374 if ( ( s->tsr_retry > 0 ) && ( s->tsr_retry <= MAX_XMIT_RETRY ) ) {
375 s->tsr_retry++;
376 qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time );
377 return;
378 } else if ( s->poll_msl < 0 ) {
379 /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
380 drop any further failed writes instantly, until we get one that goes through.
381 This is to prevent guests that log to unconnected pipes or pty's from stalling. */
382 s->tsr_retry = -1;
383 }
384 }
385 else {
386 s->tsr_retry = 0;
387 }
389 s->last_xmit_ts = qemu_get_clock(vm_clock);
390 if ( !(s->lsr & UART_LSR_THRE) )
391 qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time );
393 if ( s->lsr & UART_LSR_THRE ) {
394 s->lsr |= UART_LSR_TEMT;
395 s->thr_ipending = 1;
396 serial_update_irq(s);
397 }
398 }
401 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
402 {
403 SerialState *s = opaque;
405 addr &= 7;
406 #ifdef DEBUG_SERIAL
407 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
408 #endif
409 switch(addr) {
410 default:
411 case 0:
412 if (s->lcr & UART_LCR_DLAB) {
413 s->divider = (s->divider & 0xff00) | val;
414 serial_update_parameters(s);
415 } else {
416 s->thr = (uint8_t) val;
417 if(s->fcr & UART_FCR_FE) {
418 fifo_put(s, XMIT_FIFO, s->thr);
419 s->thr_ipending = 0;
420 s->lsr &= ~UART_LSR_TEMT;
421 s->lsr &= ~UART_LSR_THRE;
422 serial_update_irq(s);
423 } else {
424 s->thr_ipending = 0;
425 s->lsr &= ~UART_LSR_THRE;
426 serial_update_irq(s);
427 }
428 serial_xmit(s);
429 }
430 break;
431 case 1:
432 if (s->lcr & UART_LCR_DLAB) {
433 s->divider = (s->divider & 0x00ff) | (val << 8);
434 serial_update_parameters(s);
435 } else {
436 s->ier = val & 0x0f;
437 /* If the backend device is a real serial port, turn polling of the modem
438 status lines on physical port on or off depending on UART_IER_MSI state */
439 if ( s->poll_msl >= 0 ) {
440 if ( s->ier & UART_IER_MSI ) {
441 s->poll_msl = 1;
442 serial_update_msl(s);
443 } else {
444 qemu_del_timer(s->modem_status_poll);
445 s->poll_msl = 0;
446 }
447 }
448 if (s->lsr & UART_LSR_THRE) {
449 s->thr_ipending = 1;
450 serial_update_irq(s);
451 }
452 }
453 break;
454 case 2:
455 val = val & 0xFF;
457 if ( s->fcr == val)
458 break;
460 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
461 if ( (val ^ s->fcr) & UART_FCR_FE )
462 val |= UART_FCR_XFR | UART_FCR_RFR;
464 /* FIFO clear */
466 if ( val & UART_FCR_RFR ) {
467 qemu_del_timer(s->fifo_timeout_timer);
468 s->timeout_ipending=0;
469 fifo_clear(s,RECV_FIFO);
470 }
472 if ( val & UART_FCR_XFR ) {
473 fifo_clear(s,XMIT_FIFO);
474 }
476 if ( val & UART_FCR_FE ) {
477 s->iir |= UART_IIR_FE;
478 /* Set RECV_FIFO trigger Level */
479 switch ( val & 0xC0 ) {
480 case UART_FCR_ITL_1:
481 s->recv_fifo.itl = 1;
482 break;
483 case UART_FCR_ITL_2:
484 s->recv_fifo.itl = 4;
485 break;
486 case UART_FCR_ITL_3:
487 s->recv_fifo.itl = 8;
488 break;
489 case UART_FCR_ITL_4:
490 s->recv_fifo.itl = 14;
491 break;
492 }
493 } else
494 s->iir &= ~UART_IIR_FE;
496 /* Set fcr - or at least the bits in it that are supposed to "stick" */
497 s->fcr = val & 0xC9;
498 serial_update_irq(s);
499 break;
500 case 3:
501 {
502 int break_enable;
503 s->lcr = val;
504 serial_update_parameters(s);
505 break_enable = (val >> 6) & 1;
506 if (break_enable != s->last_break_enable) {
507 s->last_break_enable = break_enable;
508 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
509 &break_enable);
510 }
511 }
512 break;
513 case 4:
514 {
515 int flags;
516 int old_mcr = s->mcr;
517 s->mcr = val & 0x1f;
518 if ( val & UART_MCR_LOOP )
519 break;
521 if ( s->poll_msl >= 0 && old_mcr != s->mcr ) {
523 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
525 flags &= ~( TIOCM_RTS | TIOCM_DTR );
527 if ( val & UART_MCR_RTS )
528 flags |= TIOCM_RTS;
529 if ( val & UART_MCR_DTR )
530 flags |= TIOCM_DTR;
532 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
533 /* Update the modem status after a one-character-send wait-time, since there may be a response
534 from the device/computer at the other end of the serial line */
535 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time );
536 }
537 }
538 break;
539 case 5:
540 break;
541 case 6:
542 break;
543 case 7:
544 s->scr = val;
545 break;
546 }
547 }
549 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
550 {
551 SerialState *s = opaque;
552 uint32_t ret;
554 addr &= 7;
555 switch(addr) {
556 default:
557 case 0:
558 if (s->lcr & UART_LCR_DLAB) {
559 ret = s->divider & 0xff;
560 } else {
561 if(s->fcr & UART_FCR_FE) {
562 ret = fifo_get(s,RECV_FIFO);
563 if ( s->recv_fifo.count == 0 )
564 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
565 else
566 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4 );
567 s->timeout_ipending = 0;
568 } else {
569 ret = s->rbr;
570 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
571 }
572 serial_update_irq(s);
573 }
574 break;
575 case 1:
576 if (s->lcr & UART_LCR_DLAB) {
577 ret = (s->divider >> 8) & 0xff;
578 } else {
579 ret = s->ier;
580 }
581 break;
582 case 2:
583 ret = s->iir;
584 s->thr_ipending = 0;
585 serial_update_irq(s);
586 break;
587 case 3:
588 ret = s->lcr;
589 break;
590 case 4:
591 ret = s->mcr;
592 break;
593 case 5:
594 serial_get_token();
595 ret = s->lsr;
596 /* Clear break interrupt */
597 if ( s->lsr & UART_LSR_BI ) {
598 s->lsr &= ~UART_LSR_BI;
599 serial_update_irq(s);
600 }
601 break;
602 case 6:
603 serial_get_token();
604 if (s->mcr & UART_MCR_LOOP) {
605 /* in loopback, the modem output pins are connected to the
606 inputs */
607 ret = (s->mcr & 0x0c) << 4;
608 ret |= (s->mcr & 0x02) << 3;
609 ret |= (s->mcr & 0x01) << 5;
610 } else {
611 if ( s->poll_msl >= 0 )
612 serial_update_msl(s);
613 ret = s->msr;
614 /* Clear delta bits & msr int after read, if they were set */
615 if ( s->msr & UART_MSR_ANY_DELTA ) {
616 s->msr &= 0xF0;
617 serial_update_irq(s);
618 }
619 }
620 break;
621 case 7:
622 ret = s->scr;
623 break;
624 }
625 #ifdef DEBUG_SERIAL
626 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
627 #endif
628 return ret;
629 }
631 static int serial_can_receive(SerialState *s)
632 {
633 if(s->fcr & UART_FCR_FE) {
634 if(s->recv_fifo.count < UART_FIFO_LENGTH)
635 /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
636 advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
637 effectively overriding the ITL that the guest has set. */
638 return ( s->recv_fifo.count <= s->recv_fifo.itl ) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
639 else
640 return 0;
641 } else {
642 return !(s->lsr & UART_LSR_DR);
643 }
644 }
646 static void serial_receive_break(SerialState *s)
647 {
648 s->rbr = 0;
649 s->lsr |= UART_LSR_BI | UART_LSR_DR;
650 serial_update_irq(s);
651 }
653 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
654 static void fifo_timeout_int (void *opaque) {
655 SerialState *s = opaque;
656 if ( s->recv_fifo.count ) {
657 s->timeout_ipending = 1;
658 serial_update_irq(s);
659 }
660 }
662 static int serial_can_receive1(void *opaque)
663 {
664 SerialState *s = opaque;
665 return serial_can_receive(s);
666 }
668 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
669 {
670 SerialState *s = opaque;
671 tokens_avail = TOKENS_MAX;
672 if(s->fcr & UART_FCR_FE) {
673 int i;
674 for (i = 0; i < size; i++) {
675 fifo_put(s, RECV_FIFO, buf[i]);
676 }
677 s->lsr |= UART_LSR_DR;
678 /* call the timeout receive callback in 4 char transmit time */
679 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
680 } else {
681 s->rbr = buf[0];
682 s->lsr |= UART_LSR_DR;
683 }
684 serial_update_irq(s);
685 }
687 static void serial_event(void *opaque, int event)
688 {
689 SerialState *s = opaque;
690 tokens_avail = TOKENS_MAX;
691 if (event == CHR_EVENT_BREAK)
692 serial_receive_break(s);
693 }
695 static void serial_save(QEMUFile *f, void *opaque)
696 {
697 SerialState *s = opaque;
699 qemu_put_be16s(f,&s->divider);
700 qemu_put_8s(f,&s->rbr);
701 qemu_put_8s(f,&s->ier);
702 qemu_put_8s(f,&s->iir);
703 qemu_put_8s(f,&s->lcr);
704 qemu_put_8s(f,&s->mcr);
705 qemu_put_8s(f,&s->lsr);
706 qemu_put_8s(f,&s->msr);
707 qemu_put_8s(f,&s->scr);
708 qemu_put_8s(f,&s->fcr);
709 }
711 static int serial_load(QEMUFile *f, void *opaque, int version_id)
712 {
713 SerialState *s = opaque;
714 uint8_t fcr = 0;
716 if(version_id > 2)
717 return -EINVAL;
719 if (version_id >= 2)
720 qemu_get_be16s(f, &s->divider);
721 else
722 s->divider = qemu_get_byte(f);
723 qemu_get_8s(f,&s->rbr);
724 qemu_get_8s(f,&s->ier);
725 qemu_get_8s(f,&s->iir);
726 qemu_get_8s(f,&s->lcr);
727 qemu_get_8s(f,&s->mcr);
728 qemu_get_8s(f,&s->lsr);
729 qemu_get_8s(f,&s->msr);
730 qemu_get_8s(f,&s->scr);
731 qemu_get_8s(f,&s->fcr);
733 if (version_id >= 2)
734 qemu_get_8s(f,&fcr);
736 /* Initialize fcr via setter to perform essential side-effects */
737 serial_ioport_write(s, 0x02, fcr);
738 return 0;
739 }
741 /* If fd is zero, it means that the serial device uses the console */
742 SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
743 int base, int irq, CharDriverState *chr)
744 {
745 SerialState *s;
747 s = qemu_mallocz(sizeof(SerialState));
748 if (!s)
749 return NULL;
750 s->set_irq = set_irq;
751 s->irq_opaque = opaque;
752 s->irq = irq;
753 s->ier = 0;
754 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
755 s->iir = UART_IIR_NO_INT;
756 s->mcr = UART_MCR_OUT2;
757 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
758 /* Default to 9600 baud, no parity, one stop bit */
759 s->divider = 0x0C;
760 s->tsr_retry = 0;
761 s->char_transmit_time = ( ticks_per_sec / 9600 ) * 9;
763 s->modem_status_poll = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_update_msl, s);
765 s->poll_msl = 0;
767 fifo_clear(s,RECV_FIFO);
768 fifo_clear(s,XMIT_FIFO);
769 s->last_xmit_ts = qemu_get_clock(vm_clock);
770 s->fifo_timeout_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) fifo_timeout_int, s);
771 s->transmit_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_xmit, s);
773 register_savevm("serial", base, 2, serial_save, serial_load, s);
775 register_ioport_write(base, 8, 1, serial_ioport_write, s);
776 register_ioport_read(base, 8, 1, serial_ioport_read, s);
777 s->chr = chr;
778 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
779 serial_event, s);
780 serial_update_msl(s);
781 return s;
782 }