debuggers.hg

view tools/ioemu/target-i386-dm/exec-dm.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 5c0bf00e371d
line source
1 /*
2 * virtual page mapping and translated block handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #ifdef _WIN32
22 #include <windows.h>
23 #else
24 #include <sys/types.h>
25 #include <sys/mman.h>
26 #endif
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdarg.h>
30 #include <string.h>
31 #include <errno.h>
32 #include <unistd.h>
33 #include <inttypes.h>
35 #include "cpu.h"
36 #include "exec-all.h"
37 #include "vl.h"
39 //#define DEBUG_TB_INVALIDATE
40 //#define DEBUG_FLUSH
41 //#define DEBUG_TLB
43 /* make various TB consistency checks */
44 //#define DEBUG_TB_CHECK
45 //#define DEBUG_TLB_CHECK
47 #ifndef CONFIG_DM
48 /* threshold to flush the translated code buffer */
49 #define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
51 #define SMC_BITMAP_USE_THRESHOLD 10
53 #define MMAP_AREA_START 0x00000000
54 #define MMAP_AREA_END 0xa8000000
56 TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
57 TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
58 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
59 int nb_tbs;
60 /* any access to the tbs or the page table must use this lock */
61 spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
63 uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
64 uint8_t *code_gen_ptr;
65 #endif /* !CONFIG_DM */
67 uint64_t phys_ram_size;
68 extern uint64_t ram_size;
69 int phys_ram_fd;
70 uint8_t *phys_ram_base;
71 uint8_t *phys_ram_dirty;
73 CPUState *first_cpu;
74 /* current CPU in the current thread. It is only valid inside
75 cpu_exec() */
76 CPUState *cpu_single_env;
78 typedef struct PageDesc {
79 /* list of TBs intersecting this ram page */
80 TranslationBlock *first_tb;
81 /* in order to optimize self modifying code, we count the number
82 of lookups we do to a given page to use a bitmap */
83 unsigned int code_write_count;
84 uint8_t *code_bitmap;
85 #if defined(CONFIG_USER_ONLY)
86 unsigned long flags;
87 #endif
88 } PageDesc;
90 typedef struct PhysPageDesc {
91 /* offset in host memory of the page + io_index in the low 12 bits */
92 unsigned long phys_offset;
93 } PhysPageDesc;
95 typedef struct VirtPageDesc {
96 /* physical address of code page. It is valid only if 'valid_tag'
97 matches 'virt_valid_tag' */
98 target_ulong phys_addr;
99 unsigned int valid_tag;
100 #if !defined(CONFIG_SOFTMMU)
101 /* original page access rights. It is valid only if 'valid_tag'
102 matches 'virt_valid_tag' */
103 unsigned int prot;
104 #endif
105 } VirtPageDesc;
107 #define L2_BITS 10
108 #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
110 #define L1_SIZE (1 << L1_BITS)
111 #define L2_SIZE (1 << L2_BITS)
113 unsigned long qemu_real_host_page_size;
114 unsigned long qemu_host_page_bits;
115 unsigned long qemu_host_page_size;
116 unsigned long qemu_host_page_mask;
118 /* io memory support */
119 CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
120 CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
121 void *io_mem_opaque[IO_MEM_NB_ENTRIES];
122 static int io_mem_nb = 1;
124 /* log support */
125 FILE *logfile;
126 int loglevel;
128 void cpu_exec_init(CPUState *env)
129 {
130 CPUState **penv;
131 int cpu_index;
133 env->next_cpu = NULL;
134 penv = &first_cpu;
135 cpu_index = 0;
136 while (*penv != NULL) {
137 penv = (CPUState **)&(*penv)->next_cpu;
138 cpu_index++;
139 }
140 env->cpu_index = cpu_index;
141 *penv = env;
143 /* alloc dirty bits array */
144 phys_ram_dirty = qemu_malloc(phys_ram_size >> TARGET_PAGE_BITS);
145 }
147 /* enable or disable low levels log */
148 void cpu_set_log(int log_flags)
149 {
150 loglevel = log_flags;
151 if (!logfile)
152 logfile = stderr;
153 }
155 void cpu_set_log_filename(const char *filename)
156 {
157 logfile = fopen(filename, "w");
158 if (!logfile) {
159 perror(filename);
160 _exit(1);
161 }
162 #if !defined(CONFIG_SOFTMMU)
163 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
164 {
165 static uint8_t logfile_buf[4096];
166 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
167 }
168 #else
169 setvbuf(logfile, NULL, _IOLBF, 0);
170 #endif
171 dup2(fileno(logfile), 1);
172 dup2(fileno(logfile), 2);
173 }
175 /* mask must never be zero, except for A20 change call */
176 void cpu_interrupt(CPUState *env, int mask)
177 {
178 env->interrupt_request |= mask;
179 }
181 void cpu_reset_interrupt(CPUState *env, int mask)
182 {
183 env->interrupt_request &= ~mask;
184 }
186 CPULogItem cpu_log_items[] = {
187 { CPU_LOG_TB_OUT_ASM, "out_asm",
188 "show generated host assembly code for each compiled TB" },
189 { CPU_LOG_TB_IN_ASM, "in_asm",
190 "show target assembly code for each compiled TB" },
191 { CPU_LOG_TB_OP, "op",
192 "show micro ops for each compiled TB (only usable if 'in_asm' used)" },
193 #ifdef TARGET_I386
194 { CPU_LOG_TB_OP_OPT, "op_opt",
195 "show micro ops after optimization for each compiled TB" },
196 #endif
197 { CPU_LOG_INT, "int",
198 "show interrupts/exceptions in short format" },
199 { CPU_LOG_EXEC, "exec",
200 "show trace before each executed TB (lots of logs)" },
201 { CPU_LOG_TB_CPU, "cpu",
202 "show CPU state before bloc translation" },
203 #ifdef TARGET_I386
204 { CPU_LOG_PCALL, "pcall",
205 "show protected mode far calls/returns/exceptions" },
206 #endif
207 #ifdef DEBUG_IOPORT
208 { CPU_LOG_IOPORT, "ioport",
209 "show all i/o ports accesses" },
210 #endif
211 { 0, NULL, NULL },
212 };
214 static int cmp1(const char *s1, int n, const char *s2)
215 {
216 if (strlen(s2) != n)
217 return 0;
218 return memcmp(s1, s2, n) == 0;
219 }
221 /* takes a comma separated list of log masks. Return 0 if error. */
222 int cpu_str_to_log_mask(const char *str)
223 {
224 CPULogItem *item;
225 int mask;
226 const char *p, *p1;
228 p = str;
229 mask = 0;
230 for(;;) {
231 p1 = strchr(p, ',');
232 if (!p1)
233 p1 = p + strlen(p);
234 if(cmp1(p,p1-p,"all")) {
235 for(item = cpu_log_items; item->mask != 0; item++) {
236 mask |= item->mask;
237 }
238 } else {
239 for(item = cpu_log_items; item->mask != 0; item++) {
240 if (cmp1(p, p1 - p, item->name))
241 goto found;
242 }
243 return 0;
244 }
245 found:
246 mask |= item->mask;
247 if (*p1 != ',')
248 break;
249 p = p1 + 1;
250 }
251 return mask;
252 }
254 void cpu_abort(CPUState *env, const char *fmt, ...)
255 {
256 va_list ap;
258 va_start(ap, fmt);
259 fprintf(stderr, "qemu: fatal: ");
260 vfprintf(stderr, fmt, ap);
261 fprintf(stderr, "\n");
262 va_end(ap);
263 abort();
264 }
267 /* XXX: Simple implementation. Fix later */
268 #define MAX_MMIO 32
269 struct mmio_space {
270 target_phys_addr_t start;
271 unsigned long size;
272 unsigned long io_index;
273 } mmio[MAX_MMIO];
274 unsigned long mmio_cnt;
276 /* register physical memory. 'size' must be a multiple of the target
277 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
278 io memory page */
279 void cpu_register_physical_memory(target_phys_addr_t start_addr,
280 unsigned long size,
281 unsigned long phys_offset)
282 {
283 int i;
285 for (i = 0; i < mmio_cnt; i++) {
286 if(mmio[i].start == start_addr) {
287 mmio[i].io_index = phys_offset;
288 mmio[i].size = size;
289 return;
290 }
291 }
293 if (mmio_cnt == MAX_MMIO) {
294 fprintf(logfile, "too many mmio regions\n");
295 exit(-1);
296 }
298 mmio[mmio_cnt].io_index = phys_offset;
299 mmio[mmio_cnt].start = start_addr;
300 mmio[mmio_cnt++].size = size;
301 }
303 /* mem_read and mem_write are arrays of functions containing the
304 function to access byte (index 0), word (index 1) and dword (index
305 2). All functions must be supplied. If io_index is non zero, the
306 corresponding io zone is modified. If it is zero, a new io zone is
307 allocated. The return value can be used with
308 cpu_register_physical_memory(). (-1) is returned if error. */
309 int cpu_register_io_memory(int io_index,
310 CPUReadMemoryFunc **mem_read,
311 CPUWriteMemoryFunc **mem_write,
312 void *opaque)
313 {
314 int i;
316 if (io_index <= 0) {
317 if (io_index >= IO_MEM_NB_ENTRIES)
318 return -1;
319 io_index = io_mem_nb++;
320 } else {
321 if (io_index >= IO_MEM_NB_ENTRIES)
322 return -1;
323 }
325 for(i = 0;i < 3; i++) {
326 io_mem_read[io_index][i] = mem_read[i];
327 io_mem_write[io_index][i] = mem_write[i];
328 }
329 io_mem_opaque[io_index] = opaque;
330 return io_index << IO_MEM_SHIFT;
331 }
333 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
334 {
335 return io_mem_write[io_index >> IO_MEM_SHIFT];
336 }
338 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
339 {
340 return io_mem_read[io_index >> IO_MEM_SHIFT];
341 }
343 #ifdef __ia64__
345 #define __ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
346 #define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
347 #define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
349 /* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
350 * So to emulate right behavior that guest OS is assumed, we need to flush
351 * I/D cache here.
352 */
353 static void sync_icache(uint8_t *address, int len)
354 {
355 unsigned long addr = (unsigned long)address;
356 unsigned long end = addr + len;
358 for (addr &= ~(32UL-1); addr < end; addr += 32UL)
359 __ia64_fc(addr);
361 ia64_sync_i();
362 ia64_srlz_i();
363 }
364 #endif
366 /* physical memory access (slow version, mainly for debug) */
367 #if defined(CONFIG_USER_ONLY)
368 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
369 int len, int is_write)
370 {
371 int l, flags;
372 target_ulong page;
374 while (len > 0) {
375 page = addr & TARGET_PAGE_MASK;
376 l = (page + TARGET_PAGE_SIZE) - addr;
377 if (l > len)
378 l = len;
379 flags = page_get_flags(page);
380 if (!(flags & PAGE_VALID))
381 return;
382 if (is_write) {
383 if (!(flags & PAGE_WRITE))
384 return;
385 memcpy((uint8_t *)addr, buf, len);
386 } else {
387 if (!(flags & PAGE_READ))
388 return;
389 memcpy(buf, (uint8_t *)addr, len);
390 }
391 len -= l;
392 buf += l;
393 addr += l;
394 }
395 }
396 #else
398 int iomem_index(target_phys_addr_t addr)
399 {
400 int i;
402 for (i = 0; i < mmio_cnt; i++) {
403 unsigned long start, end;
405 start = mmio[i].start;
406 end = mmio[i].start + mmio[i].size;
408 if ((addr >= start) && (addr < end)){
409 return (mmio[i].io_index >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
410 }
411 }
412 return 0;
413 }
415 #if defined(__i386__) || defined(__x86_64__)
416 #define phys_ram_addr(x) (qemu_map_cache(x))
417 #elif defined(__ia64__)
418 #define phys_ram_addr(x) (((x) < ram_size) ? (phys_ram_base + (x)) : NULL)
419 #endif
421 extern unsigned long *logdirty_bitmap;
422 extern unsigned long logdirty_bitmap_size;
424 /*
425 * Replace the standard byte memcpy with a word memcpy for appropriately sized
426 * memory copy operations. Some users (USB-UHCI) can not tolerate the possible
427 * word tearing that can result from a guest concurrently writing a memory
428 * structure while the qemu device model is modifying the same location.
429 * Forcing a word-sized read/write prevents the guest from seeing a partially
430 * written word-sized atom.
431 */
432 #if defined(__x86_64__) || defined(__i386__)
433 static void memcpy_words(void *dst, void *src, size_t n)
434 {
435 asm volatile (
436 " movl %%edx,%%ecx \n"
437 #ifdef __x86_64__
438 " shrl $3,%%ecx \n"
439 " rep movsq \n"
440 " test $4,%%edx \n"
441 " jz 1f \n"
442 " movsl \n"
443 #else /* __i386__ */
444 " shrl $2,%%ecx \n"
445 " rep movsl \n"
446 #endif
447 "1: test $2,%%edx \n"
448 " jz 1f \n"
449 " movsw \n"
450 "1: test $1,%%edx \n"
451 " jz 1f \n"
452 " movsb \n"
453 "1: \n"
454 : "+S" (src), "+D" (dst) : "d" (n) : "ecx", "memory" );
455 }
456 #else
457 static void memcpy_words(void *dst, void *src, size_t n)
458 {
459 /* Some architectures do not like unaligned accesses. */
460 if (((unsigned long)dst | (unsigned long)src) & 3) {
461 memcpy(dst, src, n);
462 return;
463 }
465 while (n >= sizeof(uint32_t)) {
466 *((uint32_t *)dst) = *((uint32_t *)src);
467 dst = ((uint32_t *)dst) + 1;
468 src = ((uint32_t *)src) + 1;
469 n -= sizeof(uint32_t);
470 }
472 if (n & 2) {
473 *((uint16_t *)dst) = *((uint16_t *)src);
474 dst = ((uint16_t *)dst) + 1;
475 src = ((uint16_t *)src) + 1;
476 }
478 if (n & 1) {
479 *((uint8_t *)dst) = *((uint8_t *)src);
480 dst = ((uint8_t *)dst) + 1;
481 src = ((uint8_t *)src) + 1;
482 }
483 }
484 #endif
486 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
487 int len, int is_write)
488 {
489 int l, io_index;
490 uint8_t *ptr;
491 uint32_t val;
493 mapcache_lock();
495 while (len > 0) {
496 /* How much can we copy before the next page boundary? */
497 l = TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK);
498 if (l > len)
499 l = len;
501 io_index = iomem_index(addr);
502 if (is_write) {
503 if (io_index) {
504 if (l >= 4 && ((addr & 3) == 0)) {
505 /* 32 bit read access */
506 val = ldl_raw(buf);
507 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
508 l = 4;
509 } else if (l >= 2 && ((addr & 1) == 0)) {
510 /* 16 bit read access */
511 val = lduw_raw(buf);
512 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
513 l = 2;
514 } else {
515 /* 8 bit access */
516 val = ldub_raw(buf);
517 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
518 l = 1;
519 }
520 } else if ((ptr = phys_ram_addr(addr)) != NULL) {
521 /* Writing to RAM */
522 memcpy_words(ptr, buf, l);
523 if (logdirty_bitmap != NULL) {
524 /* Record that we have dirtied this frame */
525 unsigned long pfn = addr >> TARGET_PAGE_BITS;
526 if (pfn / 8 >= logdirty_bitmap_size) {
527 fprintf(logfile, "dirtying pfn %lx >= bitmap "
528 "size %lx\n", pfn, logdirty_bitmap_size * 8);
529 } else {
530 logdirty_bitmap[pfn / HOST_LONG_BITS]
531 |= 1UL << pfn % HOST_LONG_BITS;
532 }
533 }
534 #ifdef __ia64__
535 sync_icache(ptr, l);
536 #endif
537 }
538 } else {
539 if (io_index) {
540 if (l >= 4 && ((addr & 3) == 0)) {
541 /* 32 bit read access */
542 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
543 stl_raw(buf, val);
544 l = 4;
545 } else if (l >= 2 && ((addr & 1) == 0)) {
546 /* 16 bit read access */
547 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
548 stw_raw(buf, val);
549 l = 2;
550 } else {
551 /* 8 bit access */
552 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
553 stb_raw(buf, val);
554 l = 1;
555 }
556 } else if ((ptr = phys_ram_addr(addr)) != NULL) {
557 /* Reading from RAM */
558 memcpy_words(buf, ptr, l);
559 } else {
560 /* Neither RAM nor known MMIO space */
561 memset(buf, 0xff, len);
562 }
563 }
564 len -= l;
565 buf += l;
566 addr += l;
567 }
569 mapcache_unlock();
570 }
571 #endif
573 /* virtual memory access for debug */
574 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
575 uint8_t *buf, int len, int is_write)
576 {
577 int l;
578 target_ulong page, phys_addr;
580 while (len > 0) {
581 page = addr & TARGET_PAGE_MASK;
582 phys_addr = cpu_get_phys_page_debug(env, page);
583 /* if no physical page mapped, return an error */
584 if (phys_addr == -1)
585 return -1;
586 l = (page + TARGET_PAGE_SIZE) - addr;
587 if (l > len)
588 l = len;
589 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
590 buf, l, is_write);
591 len -= l;
592 buf += l;
593 addr += l;
594 }
595 return 0;
596 }
598 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
599 int dirty_flags)
600 {
601 unsigned long length;
602 int i, mask, len;
603 uint8_t *p;
605 start &= TARGET_PAGE_MASK;
606 end = TARGET_PAGE_ALIGN(end);
608 length = end - start;
609 if (length == 0)
610 return;
611 mask = ~dirty_flags;
612 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
613 len = length >> TARGET_PAGE_BITS;
614 for(i = 0; i < len; i++)
615 p[i] &= mask;
617 return;
618 }